CN100397610C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN100397610C
CN100397610C CNB2004100883504A CN200410088350A CN100397610C CN 100397610 C CN100397610 C CN 100397610C CN B2004100883504 A CNB2004100883504 A CN B2004100883504A CN 200410088350 A CN200410088350 A CN 200410088350A CN 100397610 C CN100397610 C CN 100397610C
Authority
CN
China
Prior art keywords
layer
trench
forming
semiconductor device
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2004100883504A
Other languages
English (en)
Chinese (zh)
Other versions
CN1617321A (zh
Inventor
伊藤将之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CN1617321A publication Critical patent/CN1617321A/zh
Application granted granted Critical
Publication of CN100397610C publication Critical patent/CN100397610C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Electrodes Of Semiconductors (AREA)
CNB2004100883504A 2003-11-10 2004-11-10 半导体器件及其制造方法 Expired - Fee Related CN100397610C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003379835 2003-11-10
JP2003379835A JP2005142481A (ja) 2003-11-10 2003-11-10 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
CN1617321A CN1617321A (zh) 2005-05-18
CN100397610C true CN100397610C (zh) 2008-06-25

Family

ID=34431385

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004100883504A Expired - Fee Related CN100397610C (zh) 2003-11-10 2004-11-10 半导体器件及其制造方法

Country Status (4)

Country Link
US (2) US7259073B2 (enExample)
EP (1) EP1530233A3 (enExample)
JP (1) JP2005142481A (enExample)
CN (1) CN100397610C (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060078560A1 (en) * 2003-06-23 2006-04-13 Neopharm, Inc. Method of inducing apoptosis and inhibiting cardiolipin synthesis
JP2009283488A (ja) * 2008-05-19 2009-12-03 Toshiba Corp 不揮発性メモリ及びその製造方法
US8378416B2 (en) * 2008-12-01 2013-02-19 Maxpower Semiconductor, Inc. MOS-gated power devices, methods, and integrated circuits
US9159808B2 (en) * 2009-01-26 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Selective etch-back process for semiconductor devices
CN104979196B (zh) * 2014-04-01 2018-09-25 中芯国际集成电路制造(上海)有限公司 一种沟槽型半导体器件结构的制作方法
CN105118775B (zh) * 2015-08-18 2019-02-05 上海华虹宏力半导体制造有限公司 屏蔽栅晶体管形成方法
US10164982B1 (en) 2017-11-28 2018-12-25 Cyberark Software Ltd. Actively identifying and neutralizing network hot spots
CN107993976B (zh) * 2017-12-07 2020-07-14 德淮半导体有限公司 半导体装置及其制造方法
CN111354788B (zh) * 2020-03-24 2023-05-16 成都森未科技有限公司 一种深沟槽绝缘栅极器件及其制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980747A (en) * 1986-12-22 1990-12-25 Texas Instruments Inc. Deep trench isolation with surface contact to substrate
US5773871A (en) * 1993-06-24 1998-06-30 Northern Telecom Limited Integrated circuit structure and method of fabrication thereof

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4356211A (en) * 1980-12-19 1982-10-26 International Business Machines Corporation Forming air-dielectric isolation regions in a monocrystalline silicon substrate by differential oxidation of polysilicon
US4926235A (en) * 1986-10-13 1990-05-15 Yoichi Tamaki Semiconductor device
DE3752286T2 (de) 1986-12-22 2000-01-13 Texas Instruments Inc., Dallas In einem tiefen Graben formierte Isolation mit Kontakt an der Oberfläche des Substrates
JPH0223630A (ja) * 1988-07-12 1990-01-25 Seiko Epson Corp 半導体装置の製造方法
JPH0358470A (ja) * 1989-07-26 1991-03-13 Takehide Shirato 半導体装置
US5433794A (en) * 1992-12-10 1995-07-18 Micron Technology, Inc. Spacers used to form isolation trenches with improved corners
JPH0870101A (ja) * 1994-08-11 1996-03-12 Northern Telecom Ltd 集積回路コンデンサ構造およびその製造方法
JPH08288509A (ja) * 1995-04-14 1996-11-01 Sony Corp 半導体装置及びその製造方法
US5834811A (en) * 1996-06-17 1998-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Salicide process for FETs
US5751040A (en) * 1996-09-16 1998-05-12 Taiwan Semiconductor Manufacturing Company Ltd. Self-aligned source/drain mask ROM memory cell using trench etched channel
US5773821A (en) * 1996-10-15 1998-06-30 University Of Utah Research Foundation Radiological surveying as a method for mapping fossilized bone sites
KR100268930B1 (ko) * 1996-11-12 2000-10-16 김영환 박막트랜지스터의 구조 및 그 제조방법
US5763315A (en) * 1997-01-28 1998-06-09 International Business Machines Corporation Shallow trench isolation with oxide-nitride/oxynitride liner
JP3519579B2 (ja) * 1997-09-09 2004-04-19 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US6960818B1 (en) 1997-12-30 2005-11-01 Siemens Aktiengesellschaft Recessed shallow trench isolation structure nitride liner and method for making same
US6165843A (en) * 1998-03-20 2000-12-26 Mosel Vitelic, Inc. Covered slit isolation between integrated circuit devices
US6037018A (en) * 1998-07-01 2000-03-14 Taiwan Semiconductor Maufacturing Company Shallow trench isolation filled by high density plasma chemical vapor deposition
JP2000077535A (ja) * 1998-09-02 2000-03-14 Hitachi Ltd 半導体装置及びその製造方法
US6180976B1 (en) * 1999-02-02 2001-01-30 Conexant Systems, Inc. Thin-film capacitors and methods for forming the same
US6248641B1 (en) * 1999-02-05 2001-06-19 United Microelectronics Corp. Method of fabricating shallow trench isolation
US6403445B1 (en) * 1999-04-06 2002-06-11 Advanced Micro Devices, Inc. Enhanced trench isolation structure
JP2001135718A (ja) * 1999-11-08 2001-05-18 Nec Corp トレンチ分離構造の作製方法
US6277697B1 (en) * 1999-11-12 2001-08-21 United Microelectronics Corp. Method to reduce inverse-narrow-width effect
TW469635B (en) * 2000-05-16 2001-12-21 Nanya Technology Corp Fabrication method of semiconductor memory cell transistor
JP2002237518A (ja) 2001-02-08 2002-08-23 Sony Corp 半導体装置及びその製造方法
KR100407567B1 (ko) * 2001-04-10 2003-12-01 삼성전자주식회사 덴트 없는 트렌치 격리 형성 방법
US6593192B2 (en) * 2001-04-27 2003-07-15 Micron Technology, Inc. Method of forming a dual-gated semiconductor-on-insulator device
US6645795B2 (en) * 2001-05-03 2003-11-11 International Business Machines Corporation Polysilicon doped transistor using silicon-on-insulator and double silicon-on-insulator
KR100389031B1 (ko) * 2001-06-19 2003-06-25 삼성전자주식회사 트렌치 소자분리 구조를 가지는 반도체 소자의 제조방법
US6566200B2 (en) * 2001-07-03 2003-05-20 Texas Instruments Incorporated Flash memory array structure and method of forming
DE10143997B4 (de) * 2001-09-07 2006-12-14 Infineon Technologies Ag Verfahren zur Herstellung einer integrierten Halbleiterschaltung mit einem Isolationsgraben
TW533536B (en) * 2002-04-24 2003-05-21 Nanya Technology Corp Manufacturing method of shallow trench isolation
US6653203B1 (en) * 2002-05-23 2003-11-25 Taiwan Semiconductor Manufacturing Company Thin sidewall multi-step HDP deposition method to achieve completely filled high aspect ratio trenches
US6750117B1 (en) * 2002-12-23 2004-06-15 Macronix International Co., Ltd. Shallow trench isolation process
JP2004207564A (ja) * 2002-12-26 2004-07-22 Fujitsu Ltd 半導体装置の製造方法と半導体装置
US6864152B1 (en) * 2003-05-20 2005-03-08 Lsi Logic Corporation Fabrication of trenches with multiple depths on the same substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980747A (en) * 1986-12-22 1990-12-25 Texas Instruments Inc. Deep trench isolation with surface contact to substrate
US5773871A (en) * 1993-06-24 1998-06-30 Northern Telecom Limited Integrated circuit structure and method of fabrication thereof

Also Published As

Publication number Publication date
JP2005142481A (ja) 2005-06-02
US20070018276A1 (en) 2007-01-25
CN1617321A (zh) 2005-05-18
US20050101074A1 (en) 2005-05-12
EP1530233A2 (en) 2005-05-11
US7259073B2 (en) 2007-08-21
EP1530233A3 (en) 2006-03-22

Similar Documents

Publication Publication Date Title
TWI249774B (en) Forming method of self-aligned contact for semiconductor device
JP4190164B2 (ja) ダミー絶縁層を用いた集積回路素子の導電性コンタクト体の形成方法
US6277709B1 (en) Method of forming shallow trench isolation structure
US7033908B2 (en) Methods of forming integrated circuit devices including insulation layers
US7148113B2 (en) Semiconductor device and fabricating method thereof
KR100750943B1 (ko) 반도체 장치의 배선 구조물 및 그 형성 방법
US7049225B2 (en) Method for manufacturing vias between conductive patterns utilizing etching mask patterns formed on the conductive patterns
CN100397610C (zh) 半导体器件及其制造方法
JPH11195704A (ja) 半導体装置およびその製造方法
KR100454128B1 (ko) 금속간 절연막 패턴 및 그 형성 방법
KR100475118B1 (ko) 2중 콘택 스페이서를 포함하는 반도체 소자의 제조방법
KR100845103B1 (ko) 반도체소자의 제조방법
JP4565847B2 (ja) 半導体装置およびその製造方法
CN100394552C (zh) 接触窗开口的形成方法与半导体元件的制造方法
US7790605B2 (en) Formation of interconnects through lift-off processing
KR100506050B1 (ko) 반도체소자의 콘택 형성방법
KR20010053647A (ko) 반도체장치의 콘택 형성방법
KR0154190B1 (ko) 반도체 소자의 텅스텐-플러그 형성방법
KR100226735B1 (ko) 격리막 형성 방법
JP2007081347A (ja) 半導体装置の製造方法
KR100552847B1 (ko) 반도체 소자의 트랜치 아이솔레이션 형성 방법
KR19990055791A (ko) 반도체 소자의 소자분리막 제조방법
KR100422949B1 (ko) 소자분리막 형성 방법
KR19990057376A (ko) 반도체 소자의 소자분리막 형성방법
KR20070076025A (ko) 반도체 장치의 배선 구조물의 형성 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C56 Change in the name or address of the patentee

Owner name: RENESAS ELECTRONICS CO., LTD.

Free format text: FORMER NAME: NEC CORP.

CP01 Change in the name or title of a patent holder

Address after: Kanagawa, Japan

Patentee after: Renesas Electronics Corporation

Address before: Kanagawa, Japan

Patentee before: NEC Corp.

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20080625

Termination date: 20141110

EXPY Termination of patent right or utility model