CN100364052C - 晶格调谐半导体衬底的形成 - Google Patents

晶格调谐半导体衬底的形成 Download PDF

Info

Publication number
CN100364052C
CN100364052C CNB038209543A CN03820954A CN100364052C CN 100364052 C CN100364052 C CN 100364052C CN B038209543 A CNB038209543 A CN B038209543A CN 03820954 A CN03820954 A CN 03820954A CN 100364052 C CN100364052 C CN 100364052C
Authority
CN
China
Prior art keywords
sige layer
layer
insulating mechanism
sige
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB038209543A
Other languages
English (en)
Chinese (zh)
Other versions
CN1714427A (zh
Inventor
亚当·丹尼尔·开普维尔
蒂莫西·约翰·格拉斯彼
埃文·休伯特·克雷斯威尔·帕克
特伦斯·霍尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AdvanceSis Ltd
Original Assignee
University of Warwick
AdvanceSis Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Warwick, AdvanceSis Ltd filed Critical University of Warwick
Publication of CN1714427A publication Critical patent/CN1714427A/zh
Application granted granted Critical
Publication of CN100364052C publication Critical patent/CN100364052C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/276—Lateral overgrowth
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3204—Materials thereof being Group IVA semiconducting materials
    • H10P14/3211—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V

Landscapes

  • Recrystallisation Techniques (AREA)
CNB038209543A 2002-09-03 2003-08-12 晶格调谐半导体衬底的形成 Expired - Fee Related CN100364052C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0220438.6A GB0220438D0 (en) 2002-09-03 2002-09-03 Formation of lattice-turning semiconductor substrates
GB0220438.6 2002-09-03

Publications (2)

Publication Number Publication Date
CN1714427A CN1714427A (zh) 2005-12-28
CN100364052C true CN100364052C (zh) 2008-01-23

Family

ID=9943412

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB038209543A Expired - Fee Related CN100364052C (zh) 2002-09-03 2003-08-12 晶格调谐半导体衬底的形成

Country Status (8)

Country Link
US (1) US7179727B2 (https=)
EP (1) EP1540715A1 (https=)
JP (1) JP2005537672A (https=)
KR (1) KR20050038037A (https=)
CN (1) CN100364052C (https=)
AU (1) AU2003251376A1 (https=)
GB (1) GB0220438D0 (https=)
WO (1) WO2004023536A1 (https=)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006011107A1 (en) * 2004-07-22 2006-02-02 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device and semiconductor device obtained with such a method
GB2418531A (en) * 2004-09-22 2006-03-29 Univ Warwick Formation of lattice-tuning semiconductor substrates
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
KR101329388B1 (ko) 2005-07-26 2013-11-14 앰버웨이브 시스템즈 코포레이션 다른 액티브 영역 물질의 집적회로 집적을 위한 솔루션
US7638842B2 (en) 2005-09-07 2009-12-29 Amberwave Systems Corporation Lattice-mismatched semiconductor structures on insulators
US7777250B2 (en) * 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
US7476606B2 (en) * 2006-03-28 2009-01-13 Northrop Grumman Corporation Eutectic bonding of ultrathin semiconductors
US8173551B2 (en) 2006-09-07 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Defect reduction using aspect ratio trapping
US7875958B2 (en) 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
US20080187018A1 (en) 2006-10-19 2008-08-07 Amberwave Systems Corporation Distributed feedback lasers formed via aspect ratio trapping
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US9508890B2 (en) * 2007-04-09 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Photovoltaics on silicon
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
WO2009035746A2 (en) * 2007-09-07 2009-03-19 Amberwave Systems Corporation Multi-junction solar cells
US8716836B2 (en) * 2007-12-28 2014-05-06 Sumitomo Chemical Company, Limited Semiconductor wafer, semiconductor wafer manufacturing method, and electronic device
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
US20100072515A1 (en) * 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
WO2010033813A2 (en) 2008-09-19 2010-03-25 Amberwave System Corporation Formation of devices by epitaxial layer overgrowth
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
TW201019377A (en) * 2008-10-02 2010-05-16 Sumitomo Chemical Co Wafer for a semiconductor device, semiconductor device apparatus, design system, manufacturing method, and design method
SG171987A1 (en) 2009-04-02 2011-07-28 Taiwan Semiconductor Mfg Devices formed from a non-polar plane of a crystalline material and method of making the same
WO2010134334A1 (ja) * 2009-05-22 2010-11-25 住友化学株式会社 半導体基板、電子デバイス、半導体基板の製造方法及び電子デバイスの製造方法
JP6706414B2 (ja) * 2015-11-27 2020-06-10 国立研究開発法人情報通信研究機構 Ｇｅ単結晶薄膜の製造方法及び光デバイス

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2215514A (en) * 1988-03-04 1989-09-20 Plessey Co Plc Terminating dislocations in semiconductor epitaxial layers
US5108947A (en) * 1989-01-31 1992-04-28 Agfa-Gevaert N.V. Integration of gaas on si substrates
US5158907A (en) * 1990-08-02 1992-10-27 At&T Bell Laboratories Method for making semiconductor devices with low dislocation defects
US5238869A (en) * 1988-07-25 1993-08-24 Texas Instruments Incorporated Method of forming an epitaxial layer on a heterointerface
US5272105A (en) * 1988-02-11 1993-12-21 Gte Laboratories Incorporated Method of manufacturing an heteroepitaxial semiconductor structure
US5410167A (en) * 1992-07-10 1995-04-25 Fujitsu Limited Semiconductor device with reduced side gate effect
US5442205A (en) * 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
US6039803A (en) * 1996-06-28 2000-03-21 Massachusetts Institute Of Technology Utilization of miscut substrates to improve relaxed graded silicon-germanium and germanium layers on silicon
EP1052684A1 (en) * 1999-05-10 2000-11-15 Toyoda Gosei Co., Ltd. A method for manufacturing group III nitride compound semiconductor and a light-emitting device using group III nitride compound semiconductor
WO2001001465A1 (en) * 1999-06-25 2001-01-04 Massachusetts Institute Of Technology Cyclic thermal anneal for dislocation reduction
CN1336684A (zh) * 2000-08-01 2002-02-20 三菱麻铁里亚尔株式会社 半导体衬底、场效应晶体管、锗化硅层形成方法及其制造方法
CN1364309A (zh) * 2000-03-27 2002-08-14 松下电器产业株式会社 半导体晶片及其制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04315419A (ja) * 1991-04-12 1992-11-06 Nec Corp 元素半導体基板上の絶縁膜／化合物半導体積層構造
JPH06260427A (ja) * 1993-03-05 1994-09-16 Nec Corp 半導体膜の選択成長方法
US20010006249A1 (en) 1997-09-16 2001-07-05 Eugene A Fitzgerald Co-planar si and ge composite substrate and method of producing same
DE19802977A1 (de) 1998-01-27 1999-07-29 Forschungszentrum Juelich Gmbh Verfahren zur Herstellung einer einkristallinen Schicht auf einem nicht gitterangepaßten Substrat, sowie eine oder mehrere solcher Schichten enthaltendes Bauelement
JP4345244B2 (ja) * 2001-05-31 2009-10-14 株式会社Ｓｕｍｃｏ ＳｉＧｅ層の形成方法及びこれを用いた歪みＳｉ層の形成方法と電界効果型トランジスタの製造方法
JP2004055943A (ja) * 2002-07-23 2004-02-19 Matsushita Electric Ind Co Ltd 半導体装置とその製造方法

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5272105A (en) * 1988-02-11 1993-12-21 Gte Laboratories Incorporated Method of manufacturing an heteroepitaxial semiconductor structure
GB2215514A (en) * 1988-03-04 1989-09-20 Plessey Co Plc Terminating dislocations in semiconductor epitaxial layers
US5238869A (en) * 1988-07-25 1993-08-24 Texas Instruments Incorporated Method of forming an epitaxial layer on a heterointerface
US5108947A (en) * 1989-01-31 1992-04-28 Agfa-Gevaert N.V. Integration of gaas on si substrates
US5158907A (en) * 1990-08-02 1992-10-27 At&T Bell Laboratories Method for making semiconductor devices with low dislocation defects
US5442205A (en) * 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
US5410167A (en) * 1992-07-10 1995-04-25 Fujitsu Limited Semiconductor device with reduced side gate effect
US6039803A (en) * 1996-06-28 2000-03-21 Massachusetts Institute Of Technology Utilization of miscut substrates to improve relaxed graded silicon-germanium and germanium layers on silicon
EP1052684A1 (en) * 1999-05-10 2000-11-15 Toyoda Gosei Co., Ltd. A method for manufacturing group III nitride compound semiconductor and a light-emitting device using group III nitride compound semiconductor
WO2001001465A1 (en) * 1999-06-25 2001-01-04 Massachusetts Institute Of Technology Cyclic thermal anneal for dislocation reduction
CN1364309A (zh) * 2000-03-27 2002-08-14 松下电器产业株式会社 半导体晶片及其制造方法
CN1336684A (zh) * 2000-08-01 2002-02-20 三菱麻铁里亚尔株式会社 半导体衬底、场效应晶体管、锗化硅层形成方法及其制造方法

Also Published As

Publication number Publication date
US20050245055A1 (en) 2005-11-03
CN1714427A (zh) 2005-12-28
US7179727B2 (en) 2007-02-20
EP1540715A1 (en) 2005-06-15
JP2005537672A (ja) 2005-12-08
KR20050038037A (ko) 2005-04-25
WO2004023536A1 (en) 2004-03-18
AU2003251376A1 (en) 2004-03-29
GB0220438D0 (en) 2002-10-09

Similar Documents

Publication Publication Date Title
CN100364052C (zh) 晶格调谐半导体衬底的形成
KR101115091B1 (ko) 상이한 격자 상수를 갖는 재료들을 구비한 반도체 구조체및 그 형성 방법
JP7074393B2 (ja) 異なる歪み状態を有するフィン構造を含む半導体構造を作製するための方法及び関連する半導体構造
JP6440600B2 (ja) 集積回路のトランジスタ構造
JP4182986B2 (ja) 半導体装置とその製造方法
CN101641792B (zh) 半导体器件及其制造方法
CN104813442B (zh) 图案化的衬底上的外延膜生长
CN100444323C (zh) 形成晶格调制半导体基片
TW201344758A (zh) 半導體裝置及其製造方法
CN102034689A (zh) 形成集成电路结构的方法
US7547914B2 (en) Single-crystal layer on a dielectric layer
TW201205802A (en) Semiconductor device and method for forming the same
US10043663B2 (en) Enhanced defect reduction for heteroepitaxy by seed shape engineering
KR20190098715A (ko) 상향식 핀 구조 형성을 위한 방법들
US7749817B2 (en) Single-crystal layer on a dielectric layer
JP2007506290A (ja) 絶縁構造部上の半導体チャンネル
JP3153632B2 (ja) Ｓｏｉ構造の製造方法
JP2008514021A (ja) 格子調整半導体基板の作製
US20070004212A1 (en) Method for manufacturing a semiconductor substrate and method for manufacturing a semiconductor device
JP4221928B2 (ja) 半導体基板及び電界効果型トランジスタ並びにこれらの製造方法
CN120388882A (zh) 在soi衬底上生长锗硅层的方法及半导体器件
CN103855005B (zh) 双应力异质soi半导体结构及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: ADVANCESIS LTD

Free format text: FORMER OWNER: UNIV WARWICK

Effective date: 20061020

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20061020

Address after: coventry

Applicant after: Advancesis Ltd.

Address before: Warwick County of Coventry city in Britain

Applicant before: Univ Warwick

C14 Grant of patent or utility model
GR01 Patent grant
CI03 Correction of invention patent

Correction item: Description

Correct: Reprint the correct instruction sheet, page 7-8

False: Incorrect instructions, page 7-8

Number: 4

Volume: 24

COR Change of bibliographic data

Free format text: CORRECT: DESCRIPTION; FROM: FALSE INSTRUCTIONS PAGE 7-8 TO: REPUBLISH PAGES 7-8 OF THE CORRECT SPECIFICATION

C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20080123

Termination date: 20120812