CH711536B1 - Verfahren für die Montage von mit Bumps versehenen Halbleiterchips auf Substratplätzen eines Substrats. - Google Patents

Verfahren für die Montage von mit Bumps versehenen Halbleiterchips auf Substratplätzen eines Substrats. Download PDF

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Publication number
CH711536B1
CH711536B1 CH01404/15A CH14042015A CH711536B1 CH 711536 B1 CH711536 B1 CH 711536B1 CH 01404/15 A CH01404/15 A CH 01404/15A CH 14042015 A CH14042015 A CH 14042015A CH 711536 B1 CH711536 B1 CH 711536B1
Authority
CH
Switzerland
Prior art keywords
substrate
camera
flip chip
cavity
image
Prior art date
Application number
CH01404/15A
Other languages
German (de)
English (en)
Other versions
CH711536A1 (de
Inventor
speer Florian
Original Assignee
Besi Switzerland Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Besi Switzerland Ag filed Critical Besi Switzerland Ag
Priority to DE102016113328.0A priority Critical patent/DE102016113328B4/de
Priority to SG10201606167WA priority patent/SG10201606167WA/en
Priority to JP2016156305A priority patent/JP6868982B2/ja
Priority to MYPI2016702921A priority patent/MY176667A/en
Priority to KR1020160103073A priority patent/KR102597252B1/ko
Priority to CN201610754833.6A priority patent/CN106486400B/zh
Priority to US15/250,796 priority patent/US9721819B2/en
Priority to TW105127781A priority patent/TWI700767B/zh
Publication of CH711536A1 publication Critical patent/CH711536A1/de
Publication of CH711536B1 publication Critical patent/CH711536B1/de

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
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    • H01L21/67005—Apparatus not specifically provided for elsewhere
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    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H—ELECTRICITY
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    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
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    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75702—Means for aligning in the upper part of the bonding apparatus, e.g. in the bonding head
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    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/758—Means for moving parts
    • H01L2224/75821—Upper part of the bonding apparatus, i.e. bonding head
    • H01L2224/75824—Translational mechanism
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/81132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
CH01404/15A 2015-08-31 2015-09-28 Verfahren für die Montage von mit Bumps versehenen Halbleiterchips auf Substratplätzen eines Substrats. CH711536B1 (de)

Priority Applications (8)

Application Number Priority Date Filing Date Title
DE102016113328.0A DE102016113328B4 (de) 2015-08-31 2016-07-20 Verfahren für die Montage von mit Bumps versehenen Halbleiterchips auf Substratplätzen eines Substrats
SG10201606167WA SG10201606167WA (en) 2015-08-31 2016-07-26 Method for mounting semiconductors provided with bumps on substrate locations of a substrate
JP2016156305A JP6868982B2 (ja) 2015-08-31 2016-08-09 隆起部が設けられている半導体を基板の基板位置に取り付けるための方法
MYPI2016702921A MY176667A (en) 2015-08-31 2016-08-11 Method for mounting semiconductors provided with bumps on substrate locations of a substrate
KR1020160103073A KR102597252B1 (ko) 2015-08-31 2016-08-12 범프를 구비하는 반도체를 기판의 기판 위치상에 장착하기 위한 방법
CN201610754833.6A CN106486400B (zh) 2015-08-31 2016-08-18 用于在基板的基板定位上安装设有凸块的半导体的方法
US15/250,796 US9721819B2 (en) 2015-08-31 2016-08-29 Method for mounting semiconductors provided with bumps on substrate locations of a substrate
TW105127781A TWI700767B (zh) 2015-08-31 2016-08-30 用於將設有凸塊的半導體晶片安裝在基板的基板定位的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH12482015 2015-08-31

Publications (2)

Publication Number Publication Date
CH711536A1 CH711536A1 (de) 2017-03-15
CH711536B1 true CH711536B1 (de) 2019-02-15

Family

ID=58264157

Family Applications (1)

Application Number Title Priority Date Filing Date
CH01404/15A CH711536B1 (de) 2015-08-31 2015-09-28 Verfahren für die Montage von mit Bumps versehenen Halbleiterchips auf Substratplätzen eines Substrats.

Country Status (7)

Country Link
JP (1) JP6868982B2 (enrdf_load_stackoverflow)
KR (1) KR102597252B1 (enrdf_load_stackoverflow)
CN (1) CN106486400B (enrdf_load_stackoverflow)
CH (1) CH711536B1 (enrdf_load_stackoverflow)
MY (1) MY176667A (enrdf_load_stackoverflow)
SG (1) SG10201606167WA (enrdf_load_stackoverflow)
TW (1) TWI700767B (enrdf_load_stackoverflow)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7164314B2 (ja) * 2017-04-28 2022-11-01 ベシ スウィッツァーランド エージー 部品を基板上に搭載する装置及び方法
CN109079367B (zh) * 2018-07-23 2020-07-24 中电科技（合肥）博微信息发展有限责任公司 一种芯片智能焊接方法
JP7582928B2 (ja) * 2021-11-25 2024-11-13 キヤノン株式会社 接合装置および接合方法

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JP2833996B2 (ja) * 1994-05-25 1998-12-09 日本電気株式会社 フレキシブルフィルム及びこれを有する半導体装置
JPH10209208A (ja) * 1997-01-23 1998-08-07 Hitachi Ltd 半導体製造方法および装置
US7842599B2 (en) * 1997-05-27 2010-11-30 Wstp, Llc Bumping electronic components using transfer substrates
JP2001060795A (ja) * 1999-08-20 2001-03-06 Matsushita Electric Ind Co Ltd 電子部品実装装置
US7033842B2 (en) * 2002-03-25 2006-04-25 Matsushita Electric Industrial Co., Ltd. Electronic component mounting apparatus and electronic component mounting method
JP4334892B2 (ja) * 2003-03-20 2009-09-30 パナソニック株式会社 部品実装方法
JP4516354B2 (ja) * 2004-05-17 2010-08-04 パナソニック株式会社 部品供給方法
JP2007173801A (ja) * 2005-12-22 2007-07-05 Unaxis Internatl Trading Ltd フリップチップを基板に取り付ける方法
JP2008168225A (ja) * 2007-01-12 2008-07-24 Fujifilm Corp スリット塗布方法及び装置、並びにカラーフィルタの製造方法
CH698718B1 (de) * 2007-01-31 2009-10-15 Oerlikon Assembly Equipment Ag Vorrichtung für die Montage eines Flipchips auf einem Substrat.
CH698720B1 (de) * 2007-02-14 2009-10-15 Oerlikon Assembly Equipment Ag Verfahren und Montageautomat für die Montage von Halbleiterchips als Flipchip auf einem Substrat.
CH698334B1 (de) * 2007-10-09 2011-07-29 Esec Ag Verfahren für die Entnahme und Montage von auf einem Wafertisch bereitgestellten Halbleiterchips auf einem Substrat.
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CH711536A1 (de) 2017-03-15
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KR20170026136A (ko) 2017-03-08

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