CA2836845C - Method for forming a vertical electrical connection in a layered semiconductor structure - Google Patents

Method for forming a vertical electrical connection in a layered semiconductor structure Download PDF

Info

Publication number
CA2836845C
CA2836845C CA2836845A CA2836845A CA2836845C CA 2836845 C CA2836845 C CA 2836845C CA 2836845 A CA2836845 A CA 2836845A CA 2836845 A CA2836845 A CA 2836845A CA 2836845 C CA2836845 C CA 2836845C
Authority
CA
Canada
Prior art keywords
copper
support substrate
insulating layer
semiconductor structure
layered semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CA2836845A
Other languages
English (en)
French (fr)
Other versions
CA2836845A1 (en
Inventor
Dominique Suhr
Vincent Mevellec
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alchimer SA
Original Assignee
Alchimer SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alchimer SA filed Critical Alchimer SA
Publication of CA2836845A1 publication Critical patent/CA2836845A1/en
Application granted granted Critical
Publication of CA2836845C publication Critical patent/CA2836845C/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H10P14/47—Electrolytic deposition, i.e. electroplating; Electroless plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/23—Cleaning during device manufacture during, before or after processing of insulating materials
    • H10P70/234—Cleaning during device manufacture during, before or after processing of insulating materials the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0265—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the sidewall insulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/044—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroless plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/094—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by transforming insulators into conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemically Coating (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
CA2836845A 2011-05-23 2012-05-22 Method for forming a vertical electrical connection in a layered semiconductor structure Active CA2836845C (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201161489015P 2011-05-23 2011-05-23
EP11305632.9A EP2528089B1 (en) 2011-05-23 2011-05-23 Method for forming a vertical electrical connection in a layered semiconductor structure
EP11305632.9 2011-05-23
US61/489,015 2011-05-23
PCT/EP2012/059503 WO2012160063A1 (en) 2011-05-23 2012-05-22 Method for forming a vertical electrical connection in a layered semiconductor structure

Publications (2)

Publication Number Publication Date
CA2836845A1 CA2836845A1 (en) 2012-11-29
CA2836845C true CA2836845C (en) 2020-06-30

Family

ID=44789383

Family Applications (1)

Application Number Title Priority Date Filing Date
CA2836845A Active CA2836845C (en) 2011-05-23 2012-05-22 Method for forming a vertical electrical connection in a layered semiconductor structure

Country Status (10)

Country Link
US (1) US9368397B2 (https=)
EP (1) EP2528089B1 (https=)
JP (1) JP6347744B2 (https=)
KR (1) KR102014891B1 (https=)
CN (1) CN103582942B (https=)
CA (1) CA2836845C (https=)
IL (1) IL229519B (https=)
SG (1) SG194863A1 (https=)
TW (1) TWI594387B (https=)
WO (1) WO2012160063A1 (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367139B (zh) * 2013-07-11 2016-08-24 华进半导体封装先导技术研发中心有限公司 一种tsv孔底部介质层刻蚀方法
JP2015041691A (ja) * 2013-08-21 2015-03-02 株式会社東芝 半導体装置および半導体装置の製造方法
US9321635B2 (en) * 2013-11-28 2016-04-26 Solid State System Co., Ltd. Method to release diaphragm in MEMS device
WO2017209296A1 (ja) * 2016-06-03 2017-12-07 大日本印刷株式会社 貫通電極基板及びその製造方法、並びに実装基板
CN109835867B (zh) * 2017-11-24 2023-07-14 中芯国际集成电路制造(上海)有限公司 刻蚀溶液和刻蚀方法
CN109082216B (zh) * 2018-05-23 2019-12-27 同济大学 一种弹性导电膜及其制备方法
CN111180416B (zh) * 2018-11-13 2025-04-25 长鑫存储技术有限公司 半导体结构及其制备工艺以及半导体器件
CN110634837A (zh) * 2019-09-27 2019-12-31 哈尔滨理工大学 一种用于铜互联电路中的扩散阻挡层
US11276650B2 (en) * 2019-10-31 2022-03-15 Avago Technologies International Sales Pte. Limited Stress mitigation structure
JP7419877B2 (ja) * 2020-02-28 2024-01-23 セイコーエプソン株式会社 振動デバイス、電子機器および移動体
CN116547787A (zh) * 2020-10-23 2023-08-04 华为技术有限公司 封装结构及封装结构的制备方法
JP7581915B2 (ja) 2021-01-26 2024-11-13 セイコーエプソン株式会社 振動デバイスおよび振動デバイスの製造方法
CN113594132A (zh) * 2021-07-29 2021-11-02 日月光半导体制造股份有限公司 半导体封装装置及其制造方法
EP4195246A1 (fr) * 2021-12-07 2023-06-14 STMicroelectronics Crolles 2 SAS Procédé de fabrication d'un via
JP2023157102A (ja) 2022-04-14 2023-10-26 セイコーエプソン株式会社 発振器の製造方法
FI20235748A1 (en) * 2023-06-28 2024-12-29 Canatu Finland Oy Functionalization of carbon nanostructures

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE510776A (https=) 1951-04-20
US3642549A (en) * 1969-01-15 1972-02-15 Ibm Etching composition indication
US4230523A (en) * 1978-12-29 1980-10-28 International Business Machines Corporation Etchant for silicon dioxide films disposed atop silicon or metallic silicides
US4442421A (en) * 1981-07-31 1984-04-10 Jacobus Otha J Semiconducting coordination polymers and electrical applications thereof
JP2678701B2 (ja) * 1992-02-19 1997-11-17 石原薬品 株式会社 電気銅めっき液
JP4189141B2 (ja) * 2000-12-21 2008-12-03 株式会社東芝 基板処理装置及びこれを用いた基板処理方法
US6645832B2 (en) 2002-02-20 2003-11-11 Intel Corporation Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack
EP1245697A3 (de) * 2002-07-17 2003-02-19 ATOTECH Deutschland GmbH Verfahren zum aussenstromlosen Abscheiden von Silber
US7297190B1 (en) * 2006-06-28 2007-11-20 Lam Research Corporation Plating solutions for electroless deposition of copper
US7060624B2 (en) 2003-08-13 2006-06-13 International Business Machines Corporation Deep filled vias
US7101792B2 (en) 2003-10-09 2006-09-05 Micron Technology, Inc. Methods of plating via interconnects
US8158532B2 (en) * 2003-10-20 2012-04-17 Novellus Systems, Inc. Topography reduction and control by selective accelerator removal
US7598167B2 (en) * 2004-08-24 2009-10-06 Micron Technology, Inc. Method of forming vias in semiconductor substrates without damaging active regions thereof and resulting structures
JP2006093227A (ja) * 2004-09-21 2006-04-06 Mitsubishi Electric Corp 半導体装置及びその製造方法
FR2890984B1 (fr) * 2005-09-20 2009-03-27 Alchimer Sa Procede d'electrodeposition destine au revetement d'une surface d'un substrat par un metal.
US7579274B2 (en) * 2006-02-21 2009-08-25 Alchimer Method and compositions for direct copper plating and filing to form interconnects in the fabrication of semiconductor devices
EP1989345B1 (fr) 2006-02-28 2015-03-11 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Procede de formation de films organiques sur des surfaces conductrices ou semi-conductrices de l'electricite a partir de solutions aqueuses
US7285477B1 (en) * 2006-05-16 2007-10-23 International Business Machines Corporation Dual wired integrated circuit chips
JP5245135B2 (ja) * 2007-06-30 2013-07-24 株式会社ザイキューブ 貫通導電体を有する半導体装置およびその製造方法
EP2255386B1 (en) * 2008-03-19 2016-05-04 Imec Method of fabricating through-substrate vias and semiconductor chip prepared for being provided with a through-substrate via
FR2933425B1 (fr) * 2008-07-01 2010-09-10 Alchimer Procede de preparation d'un film isolant electrique et application pour la metallisation de vias traversants
US8742588B2 (en) * 2008-10-15 2014-06-03 ÅAC Microtec AB Method for making via interconnection
CN102132409A (zh) * 2008-11-21 2011-07-20 松下电器产业株式会社 半导体装置及其制造方法
JP2010129952A (ja) * 2008-12-01 2010-06-10 Nippon Telegr & Teleph Corp <Ntt> 貫通電極配線の製造方法
US8043965B2 (en) * 2009-02-11 2011-10-25 Northrop Grumann Systems Corporation Method of forming a through substrate via in a compound semiconductor
JP2010205921A (ja) * 2009-03-03 2010-09-16 Olympus Corp 半導体装置および半導体装置の製造方法
FR2943688B1 (fr) * 2009-03-27 2012-07-20 Alchimer Dispositif et procede pour realiser une reaction electrochimique sur une surface d'un substrat semi-conducteur
FR2950633B1 (fr) * 2009-09-30 2011-11-25 Alchimer Solution et procede d'activation de la surface oxydee d'un substrat semi-conducteur.
FR2961220B1 (fr) 2010-06-11 2012-08-17 Alchimer Composition d'electrodeposition de cuivre et procede de remplissage d'une cavite d'un substrat semi-conducteur utilisant cette composition

Also Published As

Publication number Publication date
KR20140053912A (ko) 2014-05-08
JP2014519201A (ja) 2014-08-07
CN103582942A (zh) 2014-02-12
TWI594387B (zh) 2017-08-01
US9368397B2 (en) 2016-06-14
US20140084474A1 (en) 2014-03-27
CA2836845A1 (en) 2012-11-29
SG194863A1 (en) 2013-12-30
KR102014891B1 (ko) 2019-10-21
IL229519B (en) 2018-01-31
CN103582942B (zh) 2017-05-24
WO2012160063A1 (en) 2012-11-29
EP2528089A1 (en) 2012-11-28
EP2528089B1 (en) 2014-03-05
TW201304105A (zh) 2013-01-16
JP6347744B2 (ja) 2018-06-27
IL229519A0 (en) 2014-01-30

Similar Documents

Publication Publication Date Title
CA2836845C (en) Method for forming a vertical electrical connection in a layered semiconductor structure
US12154880B2 (en) Method and structures for low temperature device bonding
US7625814B2 (en) Filling deep features with conductors in semiconductor manufacturing
KR101679434B1 (ko) 전기적 절연 필름을 제조하는 방법 및 스루 비아의 금속화반응에 대한 적용
JP5689411B2 (ja) 電着組成物、及び、該組成物を用いた半導体基板のコーティング方法
CN102484095B (zh) 半导体衬底中的通孔及导电布线层
CN102569251A (zh) 三维封装用金属间化合物填充的垂直通孔互连结构及制备方法
CN111769076B (zh) 一种用于2.5d封装的tsv转接板及其制备方法
JP2013536314A (ja) 銅電着組成物及びこの組成物を用いた半導体基板の空洞の充填方法
CN103258791A (zh) 通过制备超细间距微凸点实现金属互连的方法及相应器件
US8524512B2 (en) Method for repairing copper diffusion barrier layers on a semiconductor solid substrate and repair kit for implementing this method
CN102376641B (zh) 铜填充硅通孔的制作方法
TW575948B (en) Tungsten encapsulated copper interconnections using electroplating
WO2011018478A1 (en) Electrolyte and method for the electroplating of copper on a barrier layer, and semiconductor substrate obtained with said method
CN1499616A (zh) 具有全金属化过孔的封装接口基板晶片的制造技术
Lannon et al. Process integration and testing of TSV Si interposers for 3D integration applications
WO2010133550A1 (en) Method for coating a semiconductor substrate by electrodeposition

Legal Events

Date Code Title Description
EEER Examination request

Effective date: 20170328

H13 Ip right lapsed

Free format text: ST27 STATUS EVENT CODE: N-4-6-H10-H13-H100 (AS PROVIDED BY THE NATIONAL OFFICE); EVENT TEXT: MAINTENANCE FEE AND LATE FEE NOT PAID BY DEADLINE OF NOTICE

Effective date: 20251106

W00 Other event occurred

Free format text: ST27 STATUS EVENT CODE: N-6-6-W10-W00-W100 (AS PROVIDED BY THE NATIONAL OFFICE); EVENT TEXT: LETTER SENT

Effective date: 20251110

H11 Ip right ceased following rejected request for revival

Free format text: ST27 STATUS EVENT CODE: T-6-6-H10-H11-H101 (AS PROVIDED BY THE NATIONAL OFFICE); EVENT TEXT: TIME LIMIT FOR REVERSAL EXPIRED

Effective date: 20251124

W00 Other event occurred

Free format text: ST27 STATUS EVENT CODE: N-6-6-W10-W00-W100 (AS PROVIDED BY THE NATIONAL OFFICE); EVENT TEXT: LETTER SENT

Effective date: 20251125

H13 Ip right lapsed

Free format text: ST27 STATUS EVENT CODE: N-6-6-H10-H13-H100 (AS PROVIDED BY THE NATIONAL OFFICE); EVENT TEXT: MAINTENANCE FEE AND LATE FEE NOT PAID BY DEADLINE OF NOTICE

Effective date: 20260223

W00 Other event occurred

Free format text: ST27 STATUS EVENT CODE: N-6-6-W10-W00-W100 (AS PROVIDED BY THE NATIONAL OFFICE); EVENT TEXT: LETTER SENT

Effective date: 20260224