BRPI0909624A2 - multiplexação de endereço em memória de porta pseudo-dual - Google Patents
multiplexação de endereço em memória de porta pseudo-dualInfo
- Publication number
- BRPI0909624A2 BRPI0909624A2 BRPI0909624A BRPI0909624A BRPI0909624A2 BR PI0909624 A2 BRPI0909624 A2 BR PI0909624A2 BR PI0909624 A BRPI0909624 A BR PI0909624A BR PI0909624 A BRPI0909624 A BR PI0909624A BR PI0909624 A2 BRPI0909624 A2 BR PI0909624A2
- Authority
- BR
- Brazil
- Prior art keywords
- pseudo
- memory address
- dual port
- port memory
- address multiplexing
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/047,593 US7760562B2 (en) | 2008-03-13 | 2008-03-13 | Address multiplexing in pseudo-dual port memory |
| PCT/US2009/035371 WO2009114288A1 (en) | 2008-03-13 | 2009-02-27 | Address multiplexing in pseudo-dual port memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| BRPI0909624A2 true BRPI0909624A2 (pt) | 2018-05-29 |
Family
ID=40577669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| BRPI0909624A BRPI0909624A2 (pt) | 2008-03-13 | 2009-02-27 | multiplexação de endereço em memória de porta pseudo-dual |
Country Status (12)
| Country | Link |
|---|---|
| US (2) | US7760562B2 (pt) |
| EP (1) | EP2263235B1 (pt) |
| JP (1) | JP2011515002A (pt) |
| KR (1) | KR101153109B1 (pt) |
| CN (1) | CN101971263A (pt) |
| BR (1) | BRPI0909624A2 (pt) |
| CA (1) | CA2717842C (pt) |
| ES (1) | ES2540058T3 (pt) |
| MX (1) | MX2010009991A (pt) |
| RU (1) | RU2490731C2 (pt) |
| TW (1) | TW201005749A (pt) |
| WO (1) | WO2009114288A1 (pt) |
Families Citing this family (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7760562B2 (en) * | 2008-03-13 | 2010-07-20 | Qualcomm Incorporated | Address multiplexing in pseudo-dual port memory |
| CN101908366A (zh) * | 2010-05-26 | 2010-12-08 | 秉亮科技（苏州）有限公司 | 用单端口存储单元实现多端口存储器的自定时控制方法 |
| KR101332514B1 (ko) | 2010-12-27 | 2013-11-22 | 엘지디스플레이 주식회사 | 표시장치의 감마 설정 방법 |
| CN103065670A (zh) * | 2011-10-24 | 2013-04-24 | 迈实电子(上海)有限公司 | 双端口存储器及其制造方法 |
| US8699277B2 (en) | 2011-11-16 | 2014-04-15 | Qualcomm Incorporated | Memory configured to provide simultaneous read/write access to multiple banks |
| US9911470B2 (en) | 2011-12-15 | 2018-03-06 | Nvidia Corporation | Fast-bypass memory circuit |
| US8811109B2 (en) | 2012-02-27 | 2014-08-19 | Qualcomm Incorporated | Memory pre-decoder circuits employing pulse latch(es) for reducing memory access times, and related systems and methods |
| CN103594110B (zh) * | 2012-08-15 | 2017-09-15 | 上海华虹集成电路有限责任公司 | 替代双端口静态存储器的存储器结构 |
| CN103632712A (zh) | 2012-08-27 | 2014-03-12 | 辉达公司 | 存储单元和存储器 |
| US9685207B2 (en) | 2012-12-04 | 2017-06-20 | Nvidia Corporation | Sequential access memory with master-slave latch pairs and method of operating |
| CN103106918B (zh) * | 2012-12-24 | 2015-12-02 | 西安华芯半导体有限公司 | 一种使用单端口存储单元的两端口静态随机存储器 |
| US9208841B2 (en) * | 2013-03-15 | 2015-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tracking circuit |
| US10141930B2 (en) | 2013-06-04 | 2018-11-27 | Nvidia Corporation | Three state latch |
| US9418730B2 (en) * | 2013-06-04 | 2016-08-16 | Nvidia Corporation | Handshaking sense amplifier |
| US9418714B2 (en) | 2013-07-12 | 2016-08-16 | Nvidia Corporation | Sense amplifier with transistor threshold compensation |
| US9076553B2 (en) * | 2013-11-13 | 2015-07-07 | Taiwan Semiconductor Manufacturing Company Limited | SPSRAM wrapper |
| TWI602196B (zh) * | 2014-04-02 | 2017-10-11 | 補丁科技股份有限公司 | 記憶體元件的控制方法、記憶體元件以及記憶體系統 |
| US9324416B2 (en) * | 2014-08-20 | 2016-04-26 | Qualcomm Incorporated | Pseudo dual port memory with dual latch flip-flop |
| US9520165B1 (en) * | 2015-06-19 | 2016-12-13 | Qualcomm Incorporated | High-speed pseudo-dual-port memory with separate precharge controls |
| US10061542B2 (en) * | 2015-09-15 | 2018-08-28 | Qualcomm Incorporated | Pseudo dual port memory |
| GB201603589D0 (en) | 2016-03-01 | 2016-04-13 | Surecore Ltd | Memory unit |
| US9978444B2 (en) | 2016-03-22 | 2018-05-22 | Qualcomm Incorporated | Sense amplifier enabling scheme |
| US10298348B2 (en) * | 2016-04-01 | 2019-05-21 | Ipg Photonics Corporation | Transparent clocking in a cross connect system |
| JP6682367B2 (ja) | 2016-06-08 | 2020-04-15 | ルネサスエレクトロニクス株式会社 | マルチポートメモリ、メモリマクロおよび半導体装置 |
| US10032506B2 (en) | 2016-12-12 | 2018-07-24 | Stmicroelectronics International N.V. | Configurable pseudo dual port architecture for use with single port SRAM |
| US11164614B1 (en) * | 2020-07-10 | 2021-11-02 | Taiwan Semiconductor Manufacturing Company Limited | Memory architecture |
| US11398274B2 (en) * | 2020-08-25 | 2022-07-26 | Qualcomm Incorporated | Pseudo-triple-port SRAM |
| US11955169B2 (en) * | 2021-03-23 | 2024-04-09 | Qualcomm Incorporated | High-speed multi-port memory supporting collision |
| CN114550770B (zh) * | 2022-02-28 | 2024-05-03 | 上海华力微电子有限公司 | 一种双端口sram控制电路及其控制方法 |
| CN118538263A (zh) * | 2024-07-25 | 2024-08-23 | 中科亿海微电子科技（苏州）有限公司 | 一种对fpga bram读写冲突的时序控制方法及电路 |
Family Cites Families (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SU1569904A1 (ru) * | 1988-07-15 | 1990-06-07 | Харьковский политехнический институт им.В.И.Ленина | Устройство дл контрол блоков пам ти |
| RU1817134C (ru) | 1990-03-05 | 1993-05-23 | Научно-производственное объединение "Интеграл" | Устройство разрешени конфликтной ситуаций в двухпортовом запоминающем устройстве |
| SU1718270A1 (ru) | 1990-03-29 | 1992-03-07 | Институт Точной Механики И Вычислительной Техники Им.С.А.Лебедева | Многопортовое запоминающее устройство |
| JP4018159B2 (ja) * | 1993-06-28 | 2007-12-05 | 株式会社ルネサステクノロジ | 半導体集積回路 |
| JP3304577B2 (ja) * | 1993-12-24 | 2002-07-22 | 三菱電機株式会社 | 半導体記憶装置とその動作方法 |
| CA2146472C (en) | 1994-04-22 | 2007-10-09 | Kevin Elliott Bridgewater | Packet video signal inverse transport processor with memory address circuitry |
| KR0142968B1 (ko) * | 1995-06-30 | 1998-08-17 | 김광호 | 반도체 메모리 장치의 클럭 발생 장치 |
| US5612923A (en) * | 1996-05-09 | 1997-03-18 | Northern Telecom Limited | Multi-port random access memory |
| US5781480A (en) * | 1997-07-29 | 1998-07-14 | Motorola, Inc. | Pipelined dual port integrated circuit memory |
| US5956286A (en) * | 1997-10-28 | 1999-09-21 | International Business Machines Corporation | Data processing system and method for implementing a multi-port memory cell |
| US5907508A (en) * | 1997-10-28 | 1999-05-25 | International Business Machines Corporation | Method and apparatus for single clocked, non-overlapping access in a multi-port memory cell |
| JP3871813B2 (ja) * | 1998-08-10 | 2007-01-24 | 株式会社ルネサステクノロジ | マルチポートメモリ、データプロセッサ及びデータ処理システム |
| JP2000173270A (ja) * | 1998-12-04 | 2000-06-23 | Matsushita Electric Ind Co Ltd | 半導体メモリ |
| US6252814B1 (en) * | 1999-04-29 | 2001-06-26 | International Business Machines Corp. | Dummy wordline circuitry |
| KR100415192B1 (ko) * | 2001-04-18 | 2004-01-16 | 삼성전자주식회사 | 반도체 메모리 장치에서 읽기와 쓰기 방법 및 장치 |
| RU20972U1 (ru) * | 2001-06-04 | 2001-12-10 | Федеральное государственное унитарное предприятие "Научно-производственное предприятие "Рубин" | Управляющий аппаратно-программный комплекс для обработки радиолокационной информации |
| US6882562B2 (en) * | 2001-11-01 | 2005-04-19 | Agilent Technologies, Inc. | Method and apparatus for providing pseudo 2-port RAM functionality using a 1-port memory cell |
| RU2273879C2 (ru) | 2002-05-28 | 2006-04-10 | Владимир Владимирович Насыпный | Способ синтеза самообучающейся системы извлечения знаний из текстовых документов для поисковых систем |
| JP4405215B2 (ja) * | 2002-09-12 | 2010-01-27 | パナソニック株式会社 | メモリ装置 |
| JP2004259318A (ja) * | 2003-02-24 | 2004-09-16 | Renesas Technology Corp | 同期型半導体記憶装置 |
| US6809983B2 (en) * | 2003-03-25 | 2004-10-26 | Lsi Logic Corporation | Clock generator for pseudo dual port memory |
| JP2005044334A (ja) * | 2003-07-09 | 2005-02-17 | Hitachi Ltd | 非同期制御回路と半導体集積回路装置 |
| JP4568522B2 (ja) * | 2004-04-14 | 2010-10-27 | 株式会社リコー | 半導体記憶装置 |
| RU50018U1 (ru) * | 2005-08-24 | 2005-12-10 | Открытое акционерное общество "Научно-производственное предприятие "Рубин" (ОАО "НПП "Рубин") | Мультиплексор передачи данных |
| US7319632B2 (en) * | 2005-11-17 | 2008-01-15 | Qualcomm Incorporated | Pseudo-dual port memory having a clock for each port |
| US7251193B2 (en) * | 2005-11-17 | 2007-07-31 | Qualcomm Incorporated | Pseudo-dual port memory where ratio of first to second memory access is clock duty cycle independent |
| US8315693B2 (en) * | 2006-02-28 | 2012-11-20 | Physio-Control, Inc. | Electrocardiogram monitoring |
| US7499347B2 (en) | 2006-08-09 | 2009-03-03 | Qualcomm Incorporated | Self-timing circuit with programmable delay and programmable accelerator circuits |
| US7760562B2 (en) * | 2008-03-13 | 2010-07-20 | Qualcomm Incorporated | Address multiplexing in pseudo-dual port memory |
-
2008
- 2008-03-13 US US12/047,593 patent/US7760562B2/en active Active
-
2009
- 2009-02-27 KR KR1020107022886A patent/KR101153109B1/ko not_active IP Right Cessation
- 2009-02-27 EP EP09718990.6A patent/EP2263235B1/en active Active
- 2009-02-27 CN CN2009801088515A patent/CN101971263A/zh active Pending
- 2009-02-27 ES ES09718990.6T patent/ES2540058T3/es active Active
- 2009-02-27 WO PCT/US2009/035371 patent/WO2009114288A1/en active Application Filing
- 2009-02-27 CA CA2717842A patent/CA2717842C/en not_active Expired - Fee Related
- 2009-02-27 RU RU2010141856/08A patent/RU2490731C2/ru not_active IP Right Cessation
- 2009-02-27 BR BRPI0909624A patent/BRPI0909624A2/pt not_active Application Discontinuation
- 2009-02-27 MX MX2010009991A patent/MX2010009991A/es active IP Right Grant
- 2009-02-27 JP JP2010550746A patent/JP2011515002A/ja active Pending
- 2009-03-10 TW TW098107770A patent/TW201005749A/zh unknown
-
2010
- 2010-06-14 US US12/814,682 patent/US8570818B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| KR20100135804A (ko) | 2010-12-27 |
| US7760562B2 (en) | 2010-07-20 |
| EP2263235A1 (en) | 2010-12-22 |
| CA2717842C (en) | 2014-08-26 |
| CN101971263A (zh) | 2011-02-09 |
| RU2010141856A (ru) | 2012-04-20 |
| US20090231937A1 (en) | 2009-09-17 |
| CA2717842A1 (en) | 2009-09-17 |
| US20110051537A1 (en) | 2011-03-03 |
| KR101153109B1 (ko) | 2012-06-04 |
| US8570818B2 (en) | 2013-10-29 |
| TW201005749A (en) | 2010-02-01 |
| WO2009114288A1 (en) | 2009-09-17 |
| RU2490731C2 (ru) | 2013-08-20 |
| MX2010009991A (es) | 2010-12-21 |
| JP2011515002A (ja) | 2011-05-12 |
| EP2263235B1 (en) | 2015-03-25 |
| ES2540058T3 (es) | 2015-07-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| B06F | Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette] | ||
| B06T | Formal requirements before examination [chapter 6.20 patent gazette] | ||
| B15K | Others concerning applications: alteration of classification |
Free format text: AS CLASSIFICACOES ANTERIORES ERAM: G11C 7/22 , G11C 8/16 Ipc: G11C 7/10 (2000.01), G11C 7/22 (2000.01) |
|
| B09B | Patent application refused [chapter 9.2 patent gazette] | ||
| B09B | Patent application refused [chapter 9.2 patent gazette] |
Free format text: MANTIDO O INDEFERIMENTO UMA VEZ QUE NAO FOI APRESENTADO RECURSO DENTRO DO PRAZO LEGAL |