BRPI0510077A - laço de atraso travado de freqüência ajustável - Google Patents

laço de atraso travado de freqüência ajustável

Info

Publication number
BRPI0510077A
BRPI0510077A BRPI0510077-1A BRPI0510077A BRPI0510077A BR PI0510077 A BRPI0510077 A BR PI0510077A BR PI0510077 A BRPI0510077 A BR PI0510077A BR PI0510077 A BRPI0510077 A BR PI0510077A
Authority
BR
Brazil
Prior art keywords
frequency
adjustable frequency
generating
phase
clock
Prior art date
Application number
BRPI0510077-1A
Other languages
English (en)
Inventor
Jeffrey B Wilhite
Joseph A Charaska
Manuel P Gabato Jr
Paul H Gailus
Robert E Stengel
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of BRPI0510077A publication Critical patent/BRPI0510077A/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)

Abstract

LAçO DE ATRASO TRAVADO DE FREQüêNCIA AJUSTáVEL Um laço de atraso travado 300, que inclui: uma fonte de freqüência ajustável (320) para a geração de um sinal de relógio (322) tendo uma freqüência ajustável; um controlador de ajuste e seleção de derivação (310) para a determinação de uma primeira freqüência como uma função de uma segunda freqüência e para fazer com que a fonte de freqüência ajuste a freqüência do sinal de relógio para substancialmente a primeira freqüência, a segunda freqüência sendo a freqüência desejada de um primeiro sinal de saída; uma linha de atraso (330) configurada para receber o sinal de relógio para a geração de uma pluralidade de sinais de relógio de fase deslocada; e um primeiro circuito de seleção (370) para o recebimento da pluralidade de sinais de relógio de fase deslocada e para a seleção, uma de cada vez e sob o controle do controlador de ajuste e seleção de derivação, de uma primeira seqüência de sinais de relógio de fase deslocada para a geração do primeiro sinal de saída tendo substancialmente a segunda freqüência.
BRPI0510077-1A 2004-04-22 2005-03-14 laço de atraso travado de freqüência ajustável BRPI0510077A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/830,337 US7109766B2 (en) 2004-04-22 2004-04-22 Adjustable frequency delay-locked loop
PCT/US2005/008549 WO2005109647A2 (en) 2004-04-22 2005-03-14 Adjustable frequency delay-locked loop

Publications (1)

Publication Number Publication Date
BRPI0510077A true BRPI0510077A (pt) 2007-10-16

Family

ID=35135802

Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0510077-1A BRPI0510077A (pt) 2004-04-22 2005-03-14 laço de atraso travado de freqüência ajustável

Country Status (9)

Country Link
US (1) US7109766B2 (pt)
EP (1) EP1751867B1 (pt)
CN (1) CN101375506B (pt)
AU (1) AU2005241876B2 (pt)
BR (1) BRPI0510077A (pt)
CA (1) CA2562077C (pt)
RU (1) RU2337474C2 (pt)
TW (1) TWI287360B (pt)
WO (1) WO2005109647A2 (pt)

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US20060236148A1 (en) * 2005-01-21 2006-10-19 Glenn Wood One hot counter proxy
US7970092B2 (en) * 2005-11-22 2011-06-28 Panasonic Corporation Phase comparator and regulation circuit
US7315215B2 (en) 2006-03-08 2008-01-01 Motorola,, Inc. Direct digital synthesizer with variable reference for improved spurious performance
US7675332B1 (en) 2007-01-31 2010-03-09 Altera Corporation Fractional delay-locked loops
US20080315927A1 (en) * 2007-06-11 2008-12-25 Hynix Semiconductor Inc. Frequency adjusting apparatus and dll circuit including the same
KR100911191B1 (ko) 2007-09-05 2009-08-06 주식회사 하이닉스반도체 주파수 조정 장치 및 이를 포함하는 ｄｌｌ 회로
US7816960B2 (en) * 2007-08-09 2010-10-19 Qualcomm Incorporated Circuit device and method of measuring clock jitter
US7869769B2 (en) 2007-11-28 2011-01-11 Motorola, Inc. Method and apparatus for reconfigurable frequency generation
US8154329B2 (en) * 2009-12-31 2012-04-10 Motorola Solutions, Inc. Device and method for phase compensation
KR101138831B1 (ko) * 2010-05-27 2012-05-10 에스케이하이닉스 주식회사 오픈 루프 타입의 지연 고정 루프
RU2446592C1 (ru) * 2011-03-28 2012-03-27 Александр Иосифович Иванов Устройство автоматической подстройки скорости поступающих данных асинхронного информационного потока
CN102545887B (zh) * 2011-10-31 2013-11-13 中国电子科技集团公司第十三研究所 含有等效射频延迟线功能的电路
US9160461B2 (en) 2013-01-10 2015-10-13 Qualcomm Incorporated Systems and methods for minimizing spurs through duty cycle adjustment
US10698013B2 (en) * 2015-11-27 2020-06-30 Samsung Electronics Co., Ltd. Lock-in amplifier, integrated circuit and portable measurement device including the same
RU2638962C1 (ru) * 2016-09-07 2017-12-19 Левон Александрович Хачатуров Способ достижения необходимого значения стабильности частоты генератора периодического сигнала при использовании генераторов частоты периодического (в том числе синусоидального) сигнала с тем же значением номинальной частоты, но с меньшими значениями стабильности
US10721009B2 (en) * 2016-11-17 2020-07-21 Accedian Networks Inc. Virtualized clocks
CN108270441B (zh) * 2017-01-04 2021-12-28 京东方科技集团股份有限公司 频率可调的频率源和相关的系统、方法和电子设备
US10276223B2 (en) 2017-04-24 2019-04-30 Taiwan Semiconductor Manufacturing Company Limited Memory device for generating word line signals having varying pulse widths
JPWO2019131162A1 (ja) * 2017-12-27 2020-12-17 ソニーセミコンダクタソリューションズ株式会社 増幅器および信号処理回路
CN110581743B (zh) * 2018-06-11 2021-01-22 京东方科技集团股份有限公司 电子设备、时间同步系统及时间同步方法
RU2704728C1 (ru) * 2018-11-26 2019-10-30 Российская Федерация, от имени которой выступает Федеральное агентство по техническому регулированию и метрологии (Росстандарт) Электронная система стабилизации
TWI703827B (zh) * 2019-12-25 2020-09-01 新唐科技股份有限公司 時脈倍頻器

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Publication number Priority date Publication date Assignee Title
US4637018A (en) * 1984-08-29 1987-01-13 Burroughs Corporation Automatic signal delay adjustment method
JPS6266793A (ja) * 1985-09-18 1987-03-26 Toshiba Corp 自動位相制御回路
JP3499051B2 (ja) * 1995-06-22 2004-02-23 株式会社アドバンテスト タイミング信号発生回路
JP3695833B2 (ja) * 1996-04-05 2005-09-14 株式会社ルネサステクノロジ Ｐｌｌ回路
US5990714A (en) * 1996-12-26 1999-11-23 United Microelectronics Corporation Clock signal generating circuit using variable delay circuit
US6125157A (en) * 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
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TW429686B (en) * 1998-05-12 2001-04-11 Mitsubishi Electric Corp Circuit and method for generating clock
RU2166833C1 (ru) * 2000-02-09 2001-05-10 Марийский государственный технический университет Цифровой синтезатор частотно-модулированных сигналов
RU2170490C1 (ru) * 2000-02-28 2001-07-10 Пензенский технологический институт Генератор импульсов с цифровой перестройкой периода
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US6510191B2 (en) * 2001-02-09 2003-01-21 Motorola, Inc. Direct digital synthesizer based on delay line with sorted taps
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US6642800B2 (en) * 2002-04-04 2003-11-04 Ati Technologies, Inc. Spurious-free fractional-N frequency synthesizer with multi-phase network circuit
CN100420153C (zh) * 2002-08-23 2008-09-17 联发科技股份有限公司 锁相环路

Also Published As

Publication number Publication date
US20050237093A1 (en) 2005-10-27
RU2337474C2 (ru) 2008-10-27
US7109766B2 (en) 2006-09-19
WO2005109647A3 (en) 2008-09-12
TW200610273A (en) 2006-03-16
CA2562077C (en) 2011-02-15
CN101375506B (zh) 2012-01-04
WO2005109647A2 (en) 2005-11-17
AU2005241876A1 (en) 2005-11-17
CA2562077A1 (en) 2005-11-17
EP1751867A2 (en) 2007-02-14
EP1751867A4 (en) 2009-11-18
EP1751867B1 (en) 2018-07-04
RU2006141241A (ru) 2008-05-27
CN101375506A (zh) 2009-02-25
TWI287360B (en) 2007-09-21
AU2005241876B2 (en) 2008-01-24

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 7A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2158 DE 15/05/2012.