BR9913054A - Chip semicondutor co cobertura de superfìcie - Google Patents

Chip semicondutor co cobertura de superfìcie

Info

Publication number
BR9913054A
BR9913054A BR9913054-8A BR9913054A BR9913054A BR 9913054 A BR9913054 A BR 9913054A BR 9913054 A BR9913054 A BR 9913054A BR 9913054 A BR9913054 A BR 9913054A
Authority
BR
Brazil
Prior art keywords
protective
semiconductor chip
sensor
circuits
surface coverage
Prior art date
Application number
BR9913054-8A
Other languages
English (en)
Inventor
Michael Smola
Eric-Rodger Bruecklmeier
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of BR9913054A publication Critical patent/BR9913054A/pt

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/576—Protection from inspection, reverse engineering or tampering using active circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Patente de Invenção: <B>"CHIP SEMICONDUTOR COM COBERTURA DE SUPERFìCIE"<D>. Chip semicondutor com circuitos realizados em pelo menos uma camada de um substrato semicondutor e dispostos em pelo menos um grupo, e com pelo menos uma camada protetora (SL) condutora, disposta sobre pelo menos um desses grupos de circuito e ligada eletricamente com elo menos um dos circuitos (1, 2), sendo que o substrato apresenta pelo menos um sensor de proteção (SS) e o(s) sensor(es) de proteção (SS) acha(m)-se ligado(s), por sua(s) conexão(ões) de detecção, com a camada protetora condutora (SL) ou com pelo menos uma das camadas protetoras condutoras, e conexões de saída do(s) sensor(es) de proteção (SS) acham-se ligadas com pelo menos um dos circuitos (2), de um modo tal que não seja possível uma função adequada do(s) circuito(s) quando houver um nível não-temporário definido na saída do(s) sensor(es) de proteção.
BR9913054-8A 1998-08-18 1999-08-18 Chip semicondutor co cobertura de superfìcie BR9913054A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP98115550 1998-08-18
PCT/EP1999/006077 WO2000011719A1 (de) 1998-08-18 1999-08-18 Halbleiterchip mit oberflächenabdeckung

Publications (1)

Publication Number Publication Date
BR9913054A true BR9913054A (pt) 2001-05-08

Family

ID=8232478

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9913054-8A BR9913054A (pt) 1998-08-18 1999-08-18 Chip semicondutor co cobertura de superfìcie

Country Status (11)

Country Link
US (1) US6452283B2 (pt)
EP (1) EP1114460B1 (pt)
JP (1) JP2002523901A (pt)
KR (1) KR100396064B1 (pt)
CN (1) CN1158706C (pt)
AT (1) ATE376255T1 (pt)
BR (1) BR9913054A (pt)
DE (1) DE59914529D1 (pt)
RU (1) RU2213390C2 (pt)
UA (1) UA55555C2 (pt)
WO (1) WO2000011719A1 (pt)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10058078C1 (de) * 2000-11-23 2002-04-11 Infineon Technologies Ag Integrierte Schaltungsanordnung mit Analysierschutz und Verfahren zur Herstellung der Anordnung
DE10060652C1 (de) * 2000-12-06 2002-06-20 Infineon Technologies Ag Schaltungsanordnung für die Anzeige eines Angriffes auf ein elektronisches Bauelement bzw. eine elektronische Schaltung durch Unbefugte
DE10101281C1 (de) * 2001-01-12 2002-06-06 Infineon Technologies Ag Schutzschaltung gegen die Möglichkeit des Ausspionierens von Daten bzw. Informationen
DE10111027C1 (de) 2001-03-07 2002-08-08 Infineon Technologies Ag Schaltung für FIB-Sensor
US6459629B1 (en) * 2001-05-03 2002-10-01 Hrl Laboratories, Llc Memory with a bit line block and/or a word line block for preventing reverse engineering
KR20050084333A (ko) * 2002-12-18 2005-08-26 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 자기 메모리 셀의 어레이, 집적 회로 및 외부 자기장 노출여부 표시 방법
JP2006228910A (ja) * 2005-02-16 2006-08-31 Matsushita Electric Ind Co Ltd 半導体装置
FR2888975B1 (fr) * 2005-07-21 2007-09-07 Atmel Corp Procede de securisation pour la protection de donnees
US7923830B2 (en) * 2007-04-13 2011-04-12 Maxim Integrated Products, Inc. Package-on-package secure module having anti-tamper mesh in the substrate of the upper package
DE102007051788A1 (de) 2007-10-30 2009-05-14 Giesecke & Devrient Gmbh Halbleiterchip mit einer Schutzschicht und Verfahren zum Betrieb eines Halbleiterchip
US8036061B2 (en) * 2009-02-13 2011-10-11 Apple Inc. Integrated circuit with multiported memory supercell and data path switching circuitry
DE102012200168A1 (de) 2012-01-06 2013-07-11 Technische Universität Berlin Ladungsmesseinrichtung
CN105891651B (zh) * 2015-01-16 2019-12-10 恩智浦美国有限公司 低功率开路检测系统

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE47505T1 (de) * 1984-07-31 1989-11-15 Siemens Ag Monolithisch integrierte halbleiterschaltung.
US4593384A (en) * 1984-12-21 1986-06-03 Ncr Corporation Security device for the secure storage of sensitive data
FR2617979B1 (fr) * 1987-07-10 1989-11-10 Thomson Semiconducteurs Dispositif de detection de la depassivation d'un circuit integre
US4933898A (en) * 1989-01-12 1990-06-12 General Instrument Corporation Secure integrated circuit chip with conductive shield
DE4018688C2 (de) * 1990-06-11 1998-07-02 Siemens Ag Verfahren zum Schutz einer integrierten Schaltung gegen das Auslesen sensitiver Daten
US6782479B1 (en) * 1991-04-26 2004-08-24 Raytheon Company Apparatus and method for inhibiting analysis of a secure circuit
US5389738A (en) * 1992-05-04 1995-02-14 Motorola, Inc. Tamperproof arrangement for an integrated circuit device
GB2288048A (en) * 1994-03-29 1995-10-04 Winbond Electronics Corp Intergrated circuit
FR2740553B1 (fr) * 1995-10-26 1997-12-05 Sgs Thomson Microelectronics Procede de detection de presence de passivation dans un circuit integre
DE19639033C1 (de) * 1996-09-23 1997-08-07 Siemens Ag Analysierschutz für einen Halbleiterchip
KR100278661B1 (ko) * 1998-11-13 2001-02-01 윤종용 비휘발성 메모리소자 및 그 제조방법

Also Published As

Publication number Publication date
EP1114460B1 (de) 2007-10-17
WO2000011719A1 (de) 2000-03-02
US6452283B2 (en) 2002-09-17
CN1158706C (zh) 2004-07-21
RU2213390C2 (ru) 2003-09-27
EP1114460A1 (de) 2001-07-11
UA55555C2 (uk) 2003-04-15
KR100396064B1 (ko) 2003-08-27
JP2002523901A (ja) 2002-07-30
DE59914529D1 (de) 2007-11-29
CN1314005A (zh) 2001-09-19
KR20010072743A (ko) 2001-07-31
US20010028094A1 (en) 2001-10-11
ATE376255T1 (de) 2007-11-15

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 6A, 7A E 8A ANUIDADES

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 1911 DE 21/08/2007.