GB2288048A - Intergrated circuit - Google Patents

Intergrated circuit Download PDF

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Publication number
GB2288048A
GB2288048A GB9406263A GB9406263A GB2288048A GB 2288048 A GB2288048 A GB 2288048A GB 9406263 A GB9406263 A GB 9406263A GB 9406263 A GB9406263 A GB 9406263A GB 2288048 A GB2288048 A GB 2288048A
Authority
GB
United Kingdom
Prior art keywords
integrated circuit
terminal
recited
fuse
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9406263A
Other versions
GB9406263D0 (en
Inventor
Tsuei-Chi Yeh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Winbond Electronics Corp
Original Assignee
Winbond Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Winbond Electronics Corp filed Critical Winbond Electronics Corp
Priority to GB9406263A priority Critical patent/GB2288048A/en
Publication of GB9406263D0 publication Critical patent/GB9406263D0/en
Publication of GB2288048A publication Critical patent/GB2288048A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/10—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means together with a coded signal, e.g. in the form of personal identification information, like personal identification number [PIN] or biometric data
    • G07F7/1008—Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07372—Means for preventing undesired reading or writing from or onto record carriers by detecting tampering with the circuit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07372—Means for preventing undesired reading or writing from or onto record carriers by detecting tampering with the circuit
    • G06K19/07381—Means for preventing undesired reading or writing from or onto record carriers by detecting tampering with the circuit with deactivation or otherwise incapacitation of at least a part of the circuit upon detected tampering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/34—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
    • G06Q20/341—Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/0806—Details of the card
    • G07F7/0813—Specific details related to card security
    • G07F7/082—Features insuring the integrity of the data on or in the card
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/20—Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit (1) destroys itself by a voltage signal generated therein when a predetermined condition is met. The integrated circuit comprises a transistor (11) and a fuse-type switch device (13). The transistor (11) has a control terminal (110) coupled to a first reference voltage (V1) initially to enable the integrated circuit. The fuse-type switch device (13), in response to a voltage signal, couples the control terminal to a second reference (V2) thereby disabling the function of the integrated circuit permanently. <IMAGE>

Description

JwI(zAmD aRCUTF The invention relates to an integrated circuit..
Typically, an integrated circuit is designed and manufactured to meet the specification of the integrated circuit. In most design specifications, the life time of the integrated circuit or the number of times the integrated circuit is powered up is expected to be as long or large as possible, and has no upper limit. The specification of the conventional integrated circuit products all belong to the kind just recited However, in few special applications, the producer of the integrated circuit or the downstream system maker prefers to cease the life of the integrated circuit use a pcomdrd condition . occurs or limit the number of times the integrated circuit is powered up. For instance, in the area of integrated circuit relating to the computer game, it is occasionally expected the computer game cannot be played any more when a predetermined condition is occurred. The predetermined condition may include, among others, a predetermined number of times the integrated circuit is powered up, an execution of comparison of a particular address, or a predetermined accumulated time the computer game is run, etc. To name another, an electric key system may be also a good example of field of use of this special specification. When a holder of an electronic key, or IC card, does not respond to a security system correctly within a predetermined number of input occasions of the assigned password, the integrated circuit within the IC card will destroy itself in order to prevent further use of the card.
In order to meet the need of this special application, the present invention provides an integrated circuit which destroys the function of the integrated circuit when a predetermined condition is met.
In accordance with the present invention, an integrated circuit comprises a transistor having a control terminal coupled to a first reference voltage initially to enable said integrated circuit; and a fuse-type switch means for coupling said control terminal to a second reference voltage in response to a control signal in order to disable the function of said integrated circuit permanently.
The self-destructive integrated circuit provided in the invention comprises a transistor and a fuse-type switch device. The transistor has a control terminal coupled to a first reference voltage initially to enable the integrated circuit. The fuse-type switch device, in response to a control, e.g. voltage, signal, couples the control terminal to a second reference voltage in order to disable the function of the integrated circuit permanently.
The control signal is generated when a predetermined condition occurs.
The invention will be further understood by reference to the following detailed description of the invention, together with the appended drawings, in which: FIG. 1 discloses a first preferred embodiment of the invention; FIG. 2 discloses a second preferred embodiment of the invention; and, FIG. 3 discloses a preferred embodiment of the destructive qualifying device of the invention.
As shown in FIG. 1, the integrated circuit 1 of the invention includes a transistor 11 and a fuse-type switch device 13. The transistor 11 has a control terminal 110 coupled to a first reference voltage V1 initially to enable the integrated circuit 1. In other words, as the control terminal 110 is coupled to the first reference voltage V1, the integrated circuit 1 functions as designed.
The fuse-type switch device 13 couples the control terminal 110 to a second reference voltage V2 when a voltage signal 151 is asserted thereto from a destructionqualifying device 15. As a result, the integrated circuit 1 is disabled or malfunctioned permanently to the user of the integrated circuit 1.
The transistor 11 chosen may be any power switch or logic gate in the integrated circuit 1, as long as its disability will enforce the integrated circuit 1 to malfunction or not to function.
Depending on the detailed design of the integrated circuit 1, the transistor 11 may be a MOS field-effect transistor, a bipolar transistor or a Junction field-effect transistor.
Depending on the type of the transistor 11 selected in the integrated circuit 1, the control terminal 110 may be the gate, drain or source terminal of a MOS or Junction fieldeffect transistor, or may be the base, emitter or collector terminal of a bipolar transistor.
The fuse-type switch device 13 has a first terminal 131, a second terminal 133and a signal input terminal 135. The first terminal 131 is coupled to the control terminal 110 and the second terminal 133 is coupled to the second reference voltage V2. The first terminal 131 has relation of a first kind with the second terminal 133 initially. The signal input terminal 135 is adapted to receive the voltage signal 151 such that the first terminal 131 has relation of a second kind with the second terminal 133 as the voltage signal 151 is asserted. The relation of the first kind is opposite to the relation of the second kind. The first, or the second, kind relation includes electrically-connected relation and electrically-disconnected relation, all depending on the type of the transistor 11, the control terminal 110 , and the first and second reference voltage V1, V2 selected.
As the first reference voltage V1 is selected to be a reference high, the second reference voltage V2 should be selected to be a reference low. On the contrary, as the first reference voltage V1 is selected to be a reference low, the second reference voltage V2 should be selected to be a reference high.
The fuse-type switch device 13 may be embodied through the form of a silicon fuse, a non-volatile memory cell, a silicon anti-fuse, or a polysilicon-fuse. A one-timeprogrammable read only memory(OTPROM) cell, an electrical erasable programmable read only memory (EEPROM) cell, or a ferro-electric random access memory (FERAM) cell is a preferred selection among the different types of the non-volatile memory cell. An erasable programmable read only memory (EPROM) is a straightforward choice among different types of OTPROM.
The destructive qualifying device 15 generates the voltage signal 151, responsive to an event signal 150 which is generated by the circuits of a EystaXiwtiw ffe intpatEd circuit 1. The destructive qualifying device 15 may be a circuit inside or outside the integrated circuit 1.
A preferred embodiment of the destructive 'qualifying device 15 is a colmter/timer 3 shown in FIG. 3. The counter/timer 3 shown is a non-volatile presettable one, which has a preset terminal receiving a preset signal 152, count data terminal receiving a count data signal 153 and a clock terminal receiving the event signal 150. The event signal 150 may be a power-up signal, a particular address comparison signal or any other type of signal that can be used to count down the counter/timer 3. The predetermined count data 153 is fed to the count data terminal as the preset terminal is pulled active in order to preset the counter/timer 3 at the final stage of the manufacture of the integrated circuit 1.
As recited above, there are many different selections for the fuse-type switch device 13. However, for different types of fuse-type switch device 13, there corresponds to different minimum electrical voltage required to change the state of the fuse-type switch device 13.
Therefore, a second preferred embodiment of the invention, as shown in FIG. 2, may be recommended for some types of the fuse-type switch device 13.
All elements of FIG. 2, except a voltage charge pump 17, are the same as those disclosed in FIG. 1, therefore, the function and the operation thereof may be referred to the corresponding recitations above, and will not be further recited hereinafter.
As shown in FIG. 2, the voltage charge pump 17 is triggered by a qualification signal 151 from the destructive qualifying device 15 to generate a voltage signal 171 of a much higher voltage which is required to change the state of some types of the fuse-type switch device 13.
Same as the destructive qualifying device 15, the voltage charge pump 17 may be a circuit inside or outside the integrated circuit 1.

Claims (27)

1. A circuit comprising: a transistor having a control terminal coupled to a first reference voltage initially to enable said integrated circuit; and a fuse-type switch means for coupling said control terminal to a second reference voltage in response to a control signal in order to disable the function of said integrated circuit permanently.
2. The integrated circuit as recited in claim 1, wherein said transistor is a MOS field-effect transistor.
3. The integrated circuit as recited in claim 1, wherein said transistor is a bipolar transistor.
4. The integrated circuit as recited in claim 1, wherein said transistor is a junction field-effect transistor.
5. The integrated circuit as recited in claim 2, wherein said control terminal is a gate terminal of said MOS fieldeffect transistor.
6. The integrated circuit as recited in claim 3, wherein said control terminal is a base terminal of said bipolar transistor.
7. The integrated circuit as recited in claim 4, wherein said control terminal is a gate terminal of said junction field-effect transistor.
8. The integrated circuit as recited in any of the preceding claims, wherein the fuse-type switch means has a first terminal, a second terminal and a signal input terminal, said first terminal being coupled to said control terminal and said second terminal being coupled to said second reference voltage, the first terminal having a relation of a first kind with the second terminal initially, said signal input terminal being adapted to receive said control signal such that said first terminal has relation of a second kind with said second terminal as said control signal is asserted.
9. The integrated circuit according to any of the preceding claims, wherein said first reference voltage is a reference high and said second reference voltage is a reference low.
10. The integrated circuit according to any of claims 1 to 8, wherein said first reference voltage is a reference low and said second reference voltage is a reference high.
11. The integrated circuit according to any of the preceding claims, wherein said fuse-type switch means is in the form of a silicon-fuse.
12. The integrated circuit according to any of claims 1 to 10, wherein said fuse-type switch means is in the form of a non-volatile memory cell.
13. The integrated circuit according to any of claims 1 to 10, wherein said fuse-type switch means is in the form of an anti-fuse.
14. The integrated circuit according to any of claims 1 to 10, wherein said fuse-type switch means is in the form of a polysilicon-fuse.
15. The integrated circuit as recited in claim 12, wherein said non-volatile memory cell is a ferro-electric random access memory (FERAM) cell.
16. The integrated circuit as recited in claim 12, wherein said non-volatile memory cell is a one-time-programmable read only memory (OTPROM) cell.
17. The integrated circuit as recited in claim 16, wherein said OTPROM is an erasable programmable read only memory (EPROM) cell.
18. The integrated circuit as recited in claim 12, wherein said non-volatile memory cell is an electrical erasable programmable read only memory (EEPROM) cell.
19. The integrated circuit according to any of the preceding claims, further comprising: a destruction qualifying circuit for generating said control signal in response to an event signal.
20. The integrated circuit according to claim 19, further comprising: a voltage charge pump for generating said voltage signal in response to said qualification signal.
21. The integrated circuit as recited in claim 19 or claim 20, wherein said destructive qualifying circuit is a counter/timer having a clock input receiving said event signal.
22. The integrated circuit as recited in claim 21, wherein said event signal is a power-up signal.
23. The integrated circuit as recited in claim 21, wherein said event signal is an address comparison signal.
24. The integrated circuit according to at least claim 8, wherein the first kind of relation is an electricallyconnected relation and the second kind of relation is an electrically-disconnected relation.
25. The integrated circuit according to claim 8 or any of claims 9 to 23 when dependent on claim 8, wherein the first kind of relation is an electrically-disconnected relation and the second kind of relation is an electricallyconnected relation.
26. An integrated circuit according to any of the preceding claims, wherein the control signal is a voltage signal.
27. An integrated circuit substantially as hereinbefore described with reference to any of the examples shown in the accompanying drawings.
GB9406263A 1994-03-29 1994-03-29 Intergrated circuit Withdrawn GB2288048A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9406263A GB2288048A (en) 1994-03-29 1994-03-29 Intergrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9406263A GB2288048A (en) 1994-03-29 1994-03-29 Intergrated circuit

Publications (2)

Publication Number Publication Date
GB9406263D0 GB9406263D0 (en) 1994-05-18
GB2288048A true GB2288048A (en) 1995-10-04

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GB9406263A Withdrawn GB2288048A (en) 1994-03-29 1994-03-29 Intergrated circuit

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0779599A3 (en) * 1995-12-14 1998-11-04 Ncr International Inc. A card reader system
WO2000011719A1 (en) * 1998-08-18 2000-03-02 Infineon Technologies Ag Semiconductor chip with surface coating
WO2001013330A1 (en) * 1999-08-17 2001-02-22 Infineon Technologies Ag Integrated circuit and circuit arrangement for supplying an integrated circuit with electricity
WO2001016961A1 (en) * 1999-08-31 2001-03-08 Sony Computer Entertainment Inc. Electric/electronic circuit device
GB2357458A (en) * 1999-12-23 2001-06-27 Motorola Ltd Smart card destroyed on providing path to an excess potential by breaking frangible portion
DE10060912A1 (en) * 2000-12-07 2002-06-27 Infineon Technologies Ag Data carriers and methods for their cancellation
WO2004088581A1 (en) * 2003-03-31 2004-10-14 Canon Kabushiki Kaisha Unauthorized access prevention method
KR100652412B1 (en) 2005-06-01 2006-12-01 삼성전자주식회사 Circuit and method of countermeasure against access to protected device
DE102008060295A1 (en) * 2008-12-03 2010-06-10 Giesecke & Devrient Gmbh Data carrier with electrical destruction device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4105156A (en) * 1976-09-06 1978-08-08 Dethloff Juergen Identification system safeguarded against misuse
GB1543602A (en) * 1975-05-13 1979-04-04 Innovation Ste Int Systems for storing and transferring data
GB2205186A (en) * 1987-05-23 1988-11-30 Motorola Inc Memory cards
US4795893A (en) * 1986-07-11 1989-01-03 Bull, Cp8 Security device prohibiting the function of an electronic data processing unit after a first cutoff of its electrical power
GB2206431A (en) * 1987-06-30 1989-01-05 Motorola Inc Debit card circuits

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1543602A (en) * 1975-05-13 1979-04-04 Innovation Ste Int Systems for storing and transferring data
US4105156A (en) * 1976-09-06 1978-08-08 Dethloff Juergen Identification system safeguarded against misuse
US4795893A (en) * 1986-07-11 1989-01-03 Bull, Cp8 Security device prohibiting the function of an electronic data processing unit after a first cutoff of its electrical power
GB2205186A (en) * 1987-05-23 1988-11-30 Motorola Inc Memory cards
GB2206431A (en) * 1987-06-30 1989-01-05 Motorola Inc Debit card circuits

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0779599A3 (en) * 1995-12-14 1998-11-04 Ncr International Inc. A card reader system
US6452283B2 (en) 1998-08-18 2002-09-17 Infineon Technologies Ag Semiconductor chip with surface cover
WO2000011719A1 (en) * 1998-08-18 2000-03-02 Infineon Technologies Ag Semiconductor chip with surface coating
WO2001013330A1 (en) * 1999-08-17 2001-02-22 Infineon Technologies Ag Integrated circuit and circuit arrangement for supplying an integrated circuit with electricity
US6633501B2 (en) 1999-08-17 2003-10-14 Infineon Technologies Ag Integrated circuit and circuit configuration for supplying power to an integrated circuit
WO2001016961A1 (en) * 1999-08-31 2001-03-08 Sony Computer Entertainment Inc. Electric/electronic circuit device
US6518823B1 (en) 1999-08-31 2003-02-11 Sony Computer Entertainment Inc. One-time programmable logic device
KR100798286B1 (en) 1999-08-31 2008-01-28 소니 컴퓨터 엔터테인먼트 인코포레이티드 Circuit device
GB2357458A (en) * 1999-12-23 2001-06-27 Motorola Ltd Smart card destroyed on providing path to an excess potential by breaking frangible portion
GB2357458B (en) * 1999-12-23 2004-04-14 Motorola Ltd Smart card
DE10060912A1 (en) * 2000-12-07 2002-06-27 Infineon Technologies Ag Data carriers and methods for their cancellation
WO2004088581A1 (en) * 2003-03-31 2004-10-14 Canon Kabushiki Kaisha Unauthorized access prevention method
KR100652412B1 (en) 2005-06-01 2006-12-01 삼성전자주식회사 Circuit and method of countermeasure against access to protected device
DE102008060295A1 (en) * 2008-12-03 2010-06-10 Giesecke & Devrient Gmbh Data carrier with electrical destruction device

Also Published As

Publication number Publication date
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