BR112017007876A2 - aparelho de hardware de comutação de modo de smp/asmp rápida para um sistema de processador múltiplo de alta performance de potência baixa de custo baixo - Google Patents

aparelho de hardware de comutação de modo de smp/asmp rápida para um sistema de processador múltiplo de alta performance de potência baixa de custo baixo

Info

Publication number
BR112017007876A2
BR112017007876A2 BR112017007876A BR112017007876A BR112017007876A2 BR 112017007876 A2 BR112017007876 A2 BR 112017007876A2 BR 112017007876 A BR112017007876 A BR 112017007876A BR 112017007876 A BR112017007876 A BR 112017007876A BR 112017007876 A2 BR112017007876 A2 BR 112017007876A2
Authority
BR
Brazil
Prior art keywords
smp
processor
high performance
mode switching
asmp
Prior art date
Application number
BR112017007876A
Other languages
English (en)
Other versions
BR112017007876B1 (pt
Inventor
Wei Konggang
Yang Tongzeng
Chen Wei
Original Assignee
Huawei Tech Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/516,314 external-priority patent/US9952650B2/en
Priority claimed from US14/580,044 external-priority patent/US10928882B2/en
Application filed by Huawei Tech Co Ltd filed Critical Huawei Tech Co Ltd
Publication of BR112017007876A2 publication Critical patent/BR112017007876A2/pt
Publication of BR112017007876B1 publication Critical patent/BR112017007876B1/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3293—Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Power Sources (AREA)
  • Microcomputers (AREA)
  • Multi Processors (AREA)

Abstract

a presente invenção refere-se a um sistema de processamento que inclui múltiplos processadores em que um primeiro processador opera em uma primeira frequência de relógio e uma primeira tensão de suprimento em todos os momentos. pelo menos um processador é comutável dinamicamente para operar na primeira frequência de relógio e na primeira tensão de suprimento resultando nos primeiro e segundo processadores provendo um processamento múltiplo simétrico (smp) ou uma segunda frequência de relógio e uma segunda tensão de suprimento resultando nos primeiro e segundo processadores provendo um processamento múltiplo assimétrico (asmp). um controlador integrado (por exemplo, uma máquina de estado finita (fsm)) controla não apenas a mudança de tensão, mas também uma comutação de relógio. vários critérios podem ser usados para se determinar quando comutar pelo menos um processador comutável para melhoria do consumo de potência e/ou da performance. mediante o recebimento de um comando de comutação para comutação entre smp e asmp, uma série ou sequência de ações é executada para controle de um suprimento de tensão e um relógio de cpu/memória para o processador comutável e uma memória cache.
BR112017007876-7A 2014-10-16 2015-10-10 Sistema de processamento de processador múltiplo, aparelho, método de comutação de uma pluralidade de processadores entre um modo de processamento múltiplo simétrico (smp) e um modo de processamento múltiplo assimétrico (asmp), e método de processamento em um sistema de processador múltiplo que tem uma pluralidade de processadores BR112017007876B1 (pt)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US14/516,314 US9952650B2 (en) 2014-10-16 2014-10-16 Hardware apparatus and method for multiple processors dynamic asymmetric and symmetric mode switching
US14/516,314 2014-10-16
US14/580,044 2014-12-22
US14/580,044 US10928882B2 (en) 2014-10-16 2014-12-22 Low cost, low power high performance SMP/ASMP multiple-processor system
US14/704,240 2015-05-05
US14/704,240 US10248180B2 (en) 2014-10-16 2015-05-05 Fast SMP/ASMP mode-switching hardware apparatus for a low-cost low-power high performance multiple processor system
PCT/CN2015/091664 WO2016058500A1 (en) 2014-10-16 2015-10-10 Fast smp/asmp mode-switching hardware apparatus for low-cost low-power high performance multiple processor system

Publications (2)

Publication Number Publication Date
BR112017007876A2 true BR112017007876A2 (pt) 2018-01-23
BR112017007876B1 BR112017007876B1 (pt) 2023-01-10

Family

ID=55746129

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112017007876-7A BR112017007876B1 (pt) 2014-10-16 2015-10-10 Sistema de processamento de processador múltiplo, aparelho, método de comutação de uma pluralidade de processadores entre um modo de processamento múltiplo simétrico (smp) e um modo de processamento múltiplo assimétrico (asmp), e método de processamento em um sistema de processador múltiplo que tem uma pluralidade de processadores

Country Status (8)

Country Link
US (2) US10248180B2 (pt)
EP (1) EP3198465B1 (pt)
JP (1) JP6423090B2 (pt)
KR (1) KR101942883B1 (pt)
CN (1) CN106415521B (pt)
BR (1) BR112017007876B1 (pt)
ES (1) ES2799502T3 (pt)
WO (1) WO2016058500A1 (pt)

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Also Published As

Publication number Publication date
US10248180B2 (en) 2019-04-02
US10948969B2 (en) 2021-03-16
BR112017007876B1 (pt) 2023-01-10
JP2017537378A (ja) 2017-12-14
CN106415521B (zh) 2020-04-14
JP6423090B2 (ja) 2018-11-14
ES2799502T3 (es) 2020-12-18
EP3198465A4 (en) 2017-09-13
WO2016058500A1 (en) 2016-04-21
CN106415521A (zh) 2017-02-15
EP3198465A1 (en) 2017-08-02
KR101942883B1 (ko) 2019-01-28
US20160109923A1 (en) 2016-04-21
US20190227613A1 (en) 2019-07-25
EP3198465B1 (en) 2020-04-29
KR20170070160A (ko) 2017-06-21

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