BR112016001014A2 - Computing architecture with peripherals - Google Patents
Computing architecture with peripheralsInfo
- Publication number
- BR112016001014A2 BR112016001014A2 BR112016001014A BR112016001014A BR112016001014A2 BR 112016001014 A2 BR112016001014 A2 BR 112016001014A2 BR 112016001014 A BR112016001014 A BR 112016001014A BR 112016001014 A BR112016001014 A BR 112016001014A BR 112016001014 A2 BR112016001014 A2 BR 112016001014A2
- Authority
- BR
- Brazil
- Prior art keywords
- interconnect
- time
- peripherals
- memory transfer
- computing architecture
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0817—Cache consistency protocols using directory methods
- G06F12/082—Associative directories
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1663—Access to shared memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
- G06F13/372—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a time-dependent priority, e.g. individually loaded time counters or time slot
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/065—Replication mechanisms
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/067—Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/28—Using a specific disk cache architecture
- G06F2212/283—Plural cache memories
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/6032—Way prediction in set-associative cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/62—Details of cache specific to multiprocessor cache arrangements
- G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Computer Hardware Design (AREA)
- Computer Security & Cryptography (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Bus Control (AREA)
- Multi Processors (AREA)
- Memory System (AREA)
Abstract
ARQUITETURA DE COMPUTAÇÃO COM PERIFÉRICOS. Uma arquitetura computacional de memória compartilhada (300) tem M mestres-de-interconexão (350, 351, 352, 353, 354), um alvo-de-interconexão (370), e uma interconexão baseada em alocação de tempo(319). A interconexão (319) tem uma interconexão unidirectional baseada em alocação de tempo (320) para transportar requisições de transferência de memória com T intervalos de tempo e uma interconexão unidirectional baseada em alocação de tempo (340) para o transporte das respostas (às requisições) de transferência de memória com R intervalos de tempo. Para cada um dos R intervalos de tempo, aquele intervalo de tempo: corresponde a um intervalo de tempo para requisição de transferência de memória e inicia pelo menos L ciclos de relógico depois do instante de início daquele intervalo de tempo da requisição correspondente. O valor de L e >= 3 e < T. O alvo-de-interconexão (370) está conectada à interconexão (319). Cada mestre-de-interconexão (350, 351, 352, 353, 354) está conectado à interconexão (319).
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2013902678A AU2013902678A0 (en) | 2013-07-18 | Computing architecture with peripherals | |
AU2013904532A AU2013904532A0 (en) | 2013-11-25 | Computing architecture with peripherals | |
PCT/IB2014/063189 WO2015008251A2 (en) | 2013-07-18 | 2014-07-17 | Computing architecture with peripherals |
Publications (1)
Publication Number | Publication Date |
---|---|
BR112016001014A2 true BR112016001014A2 (pt) | 2017-08-22 |
Family
ID=51585139
Family Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112016001011A BR112016001011A2 (pt) | 2013-07-18 | 2014-07-17 | Computing architecture with peripherals |
BR112016001014A BR112016001014A2 (pt) | 2013-07-18 | 2014-07-17 | Computing architecture with peripherals |
BR112016000972A BR112016000972A2 (pt) | 2013-07-18 | 2014-07-17 | Computing architecture with peripherals |
BR112016001013A BR112016001013A2 (pt) | 2013-07-18 | 2014-07-17 | Computing architecture with peripherals |
BR112016001015A BR112016001015A2 (pt) | 2013-07-18 | 2014-07-17 | Computing architecture with peripherals |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112016001011A BR112016001011A2 (pt) | 2013-07-18 | 2014-07-17 | Computing architecture with peripherals |
Family Applications After (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112016000972A BR112016000972A2 (pt) | 2013-07-18 | 2014-07-17 | Computing architecture with peripherals |
BR112016001013A BR112016001013A2 (pt) | 2013-07-18 | 2014-07-17 | Computing architecture with peripherals |
BR112016001015A BR112016001015A2 (pt) | 2013-07-18 | 2014-07-17 | Computing architecture with peripherals |
Country Status (8)
Country | Link |
---|---|
US (5) | US10210117B2 (pt) |
EP (1) | EP3022655A2 (pt) |
AU (1) | AU2014291635B2 (pt) |
BR (5) | BR112016001011A2 (pt) |
CA (1) | CA2924881A1 (pt) |
IL (2) | IL243619A0 (pt) |
SG (1) | SG11201600354TA (pt) |
WO (1) | WO2015008251A2 (pt) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3003054B1 (fr) * | 2013-03-06 | 2016-08-19 | Sagem Defense Securite | Procede et dispositif de filtrage de transactions pour systeme sur puce |
EP3022655A2 (en) * | 2013-07-18 | 2016-05-25 | Synaptic Laboratories Limited | Computing architecture with peripherals |
US9578054B1 (en) * | 2015-08-31 | 2017-02-21 | Newman H-R Computer Design, LLC | Hacking-resistant computer design |
JP6575260B2 (ja) * | 2015-09-18 | 2019-09-18 | 富士通株式会社 | 帯域管理装置、帯域管理方法および帯域管理プログラム |
EP3188025A1 (en) * | 2015-12-29 | 2017-07-05 | Teknologian Tutkimuskeskus VTT Oy | Memory node with cache for emulated shared memory computers |
US9997232B2 (en) * | 2016-03-10 | 2018-06-12 | Micron Technology, Inc. | Processing in memory (PIM) capable memory device having sensing circuitry performing logic operations |
US10282321B1 (en) * | 2017-01-19 | 2019-05-07 | Marvell Israel (M.I.S.L) Ltd. | Systems and methods for serial input and selective output mechanism for exchanging data at a network device |
JP6979777B2 (ja) * | 2017-03-22 | 2021-12-15 | キヤノン株式会社 | インターフェース装置およびその制御方法 |
US10592424B2 (en) * | 2017-07-14 | 2020-03-17 | Arm Limited | Range-based memory system |
US10613979B2 (en) | 2017-11-30 | 2020-04-07 | International Business Machines Corporation | Accelerator memory coherency with single state machine |
US10437750B2 (en) * | 2017-12-21 | 2019-10-08 | Arm Limited | Relative data width indication for read responses routed by an interconnect |
US11880314B1 (en) * | 2018-07-27 | 2024-01-23 | Dialog Semiconductor B.V. | Microcontroller for driving an external device |
US11409643B2 (en) | 2019-11-06 | 2022-08-09 | Honeywell International Inc | Systems and methods for simulating worst-case contention to determine worst-case execution time of applications executed on a processor |
CN115794727A (zh) * | 2022-11-03 | 2023-03-14 | 格兰菲智能科技有限公司 | 缓存系统构造方法和装置 |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4488287A (en) * | 1982-11-30 | 1984-12-11 | International Telephone And Telegraph Corporation | Combining and splitting of voice and data from multiple terminal sources and electronic PABX for same |
US4578789A (en) * | 1982-11-30 | 1986-03-25 | Itt Corporation | Simultaneous voice and data communication and data base access in a switching system using a tone bus or broadcast mode |
US4589107A (en) * | 1982-11-30 | 1986-05-13 | Itt Corporation | Simultaneous voice and data communication and data base access in a switching system using a combined voice conference and data base processing module |
US4584680A (en) * | 1982-11-30 | 1986-04-22 | Itt Corporation | Use of a tone bus to provide polling and data distribution apparatus for communication system terminal groups |
US4912633A (en) * | 1988-10-24 | 1990-03-27 | Ncr Corporation | Hierarchical multiple bus computer architecture |
US5963746A (en) * | 1990-11-13 | 1999-10-05 | International Business Machines Corporation | Fully distributed processing memory element |
US5590345A (en) * | 1990-11-13 | 1996-12-31 | International Business Machines Corporation | Advanced parallel array processor(APAP) |
US5748921A (en) * | 1995-12-11 | 1998-05-05 | Advanced Micro Devices, Inc. | Computer system including a plurality of multimedia devices each having a high-speed memory data channel for accessing system memory |
US6567426B1 (en) * | 1998-03-05 | 2003-05-20 | Silicon Graphics, Inc. | Preemptive timer multiplexed shared memory access |
JP3959914B2 (ja) * | 1999-12-24 | 2007-08-15 | 株式会社日立製作所 | 主記憶共有型並列計算機及びそれに用いるノード制御装置 |
US7124376B2 (en) * | 2000-05-02 | 2006-10-17 | Palmchip Corporation | Design tool for systems-on-a-chip |
AU2001278328A1 (en) * | 2000-07-26 | 2002-02-05 | David Dickenson | Distributive access controller |
US20040010652A1 (en) * | 2001-06-26 | 2004-01-15 | Palmchip Corporation | System-on-chip (SOC) architecture with arbitrary pipeline depth |
US7085866B1 (en) * | 2002-02-19 | 2006-08-01 | Hobson Richard F | Hierarchical bus structure and memory access protocol for multiprocessor systems |
US20050172091A1 (en) * | 2004-01-29 | 2005-08-04 | Rotithor Hemant G. | Method and an apparatus for interleaving read data return in a packetized interconnect to memory |
US9513695B2 (en) * | 2008-06-24 | 2016-12-06 | Virident Systems, Inc. | Methods of managing power in network computer systems |
US8417873B1 (en) * | 2008-06-24 | 2013-04-09 | Virident Systems, Inc. | Random read and read/write block accessible memory |
US8880970B2 (en) * | 2008-12-23 | 2014-11-04 | Conversant Intellectual Property Management Inc. | Error detection method and a system including one or more memory devices |
JP5420648B2 (ja) * | 2009-05-22 | 2014-02-19 | 株式会社日立製作所 | 半導体装置 |
GB2474446A (en) * | 2009-10-13 | 2011-04-20 | Advanced Risc Mach Ltd | Barrier requests to maintain transaction order in an interconnect with multiple paths |
US20110153982A1 (en) * | 2009-12-21 | 2011-06-23 | Bbn Technologies Corp. | Systems and methods for collecting data from multiple core processors |
US9825883B2 (en) * | 2010-05-27 | 2017-11-21 | Ciena Corporation | Extensible time space switch systems and methods |
US8438327B2 (en) * | 2010-06-30 | 2013-05-07 | Freescale Semiconductor, Inc. | Recovery scheme for an emulated memory system |
US8627021B2 (en) * | 2011-08-31 | 2014-01-07 | Qualcomm Incorporated | Method and apparatus for load-based prefetch access |
US9875108B2 (en) * | 2013-03-16 | 2018-01-23 | Intel Corporation | Shared memory interleavings for instruction atomicity violations |
EP3022655A2 (en) * | 2013-07-18 | 2016-05-25 | Synaptic Laboratories Limited | Computing architecture with peripherals |
US9454378B2 (en) * | 2013-09-30 | 2016-09-27 | Apple Inc. | Global configuration broadcast |
-
2014
- 2014-07-17 EP EP14771622.9A patent/EP3022655A2/en not_active Withdrawn
- 2014-07-17 US US14/905,011 patent/US10210117B2/en active Active
- 2014-07-17 BR BR112016001011A patent/BR112016001011A2/pt not_active IP Right Cessation
- 2014-07-17 SG SG11201600354TA patent/SG11201600354TA/en unknown
- 2014-07-17 WO PCT/IB2014/063189 patent/WO2015008251A2/en active Application Filing
- 2014-07-17 BR BR112016001014A patent/BR112016001014A2/pt not_active IP Right Cessation
- 2014-07-17 BR BR112016000972A patent/BR112016000972A2/pt not_active IP Right Cessation
- 2014-07-17 BR BR112016001013A patent/BR112016001013A2/pt not_active IP Right Cessation
- 2014-07-17 BR BR112016001015A patent/BR112016001015A2/pt not_active IP Right Cessation
- 2014-07-17 CA CA2924881A patent/CA2924881A1/en not_active Abandoned
- 2014-07-17 AU AU2014291635A patent/AU2014291635B2/en active Active
-
2016
- 2016-01-15 IL IL243619A patent/IL243619A0/en unknown
- 2016-01-16 US US14/997,494 patent/US20160299857A1/en not_active Abandoned
- 2016-01-16 US US14/997,487 patent/US20160275015A1/en not_active Abandoned
- 2016-01-16 US US14/997,498 patent/US20160321205A1/en not_active Abandoned
- 2016-01-16 US US14/997,501 patent/US20160299714A1/en not_active Abandoned
- 2016-01-18 IL IL243652A patent/IL243652A0/en unknown
Also Published As
Publication number | Publication date |
---|---|
BR112016001011A2 (pt) | 2017-08-22 |
SG11201600354TA (en) | 2016-03-30 |
US20160299714A1 (en) | 2016-10-13 |
US20160154753A1 (en) | 2016-06-02 |
WO2015008251A3 (en) | 2015-05-28 |
AU2014291635A1 (en) | 2016-03-10 |
US10210117B2 (en) | 2019-02-19 |
US20160299857A1 (en) | 2016-10-13 |
NZ716954A (en) | 2021-02-26 |
CA2924881A1 (en) | 2015-01-22 |
US20160275015A1 (en) | 2016-09-22 |
BR112016001013A2 (pt) | 2017-08-22 |
EP3022655A2 (en) | 2016-05-25 |
US20160321205A1 (en) | 2016-11-03 |
BR112016001015A2 (pt) | 2017-08-22 |
BR112016000972A2 (pt) | 2017-08-22 |
WO2015008251A2 (en) | 2015-01-22 |
IL243652A0 (en) | 2016-02-29 |
IL243619A0 (en) | 2016-02-29 |
AU2014291635B2 (en) | 2019-11-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
BR112016000972A2 (pt) | Computing architecture with peripherals | |
BR112015003406A2 (pt) | acesso a nível de bloco para armazenamento paralelo | |
BR112016012904A2 (pt) | Indicação de disponibilidade de usuário para comunicação | |
MX350915B (es) | Terminacion de comando de averiguacion en memorias flash. | |
BR112016010291A8 (pt) | sistema de computação para atender solicitações de uma pluralidade de clientes e método | |
BR112015029848A8 (pt) | dispositivos de recepção e de transmissão, métodos para recepção de um dispositivo de recepção e para transmissão de um dispositivo de transmissão, e, meio de armazenamento legível por computador | |
BR102013031320A8 (pt) | sistema e meio legível por computador não-transitório | |
BR112018004896A2 (pt) | ?dispositivo proxy para representar múltiplas credenciais | |
BR112016013584A8 (pt) | sistema de computação, método executado por processador, meio de armazenamento legível por computador e dispositivo de armazenamento para construção de consultas para execução através de estruturas de dados multidimensionais | |
BR112013006392A2 (pt) | métodos de processamento de solicitações para conteúdo e de iniciar uma interligação para o conteúdo | |
BR112015026753A2 (pt) | método e dispositivo para a gestão de memória de dispositivo de usuário | |
BR112015031583A2 (pt) | rede local e método para atualizar um dispositivo em uma rede local | |
BR112017004100A2 (pt) | apresentação de ambiente de computação em múltiplos dispositivos | |
BR112015024948A2 (pt) | compartilhamento de firmware entre agentes em um nó de computação | |
BR112016002181A2 (pt) | controle de um modo de acesso atual de um dispositivo de computação com base em um estado de um mecanismo de fixação | |
BR112015018922A8 (pt) | dispositivo, método e um ou mais meios de armazenamento não transitórios legíveis por computador para estimação de rotina | |
BR112017001869A2 (pt) | sistema de bloco de construção e unidades de bloco de construção do mesmo | |
BR112015027171A2 (pt) | manutenção de resultado de pesquisa com etiquetas | |
BR112014032795A2 (pt) | método, dispositivo, servidor e terminal para visitar página da rede | |
BR112015030435A2 (pt) | temporizadores por processador virtuais para sistemas de processador múltiplo | |
BR112017026655A2 (pt) | dispositivo de comunicação e rede que usam protocolo tdma de radiocomunicação | |
IN2013CH04449A (pt) | ||
IN2013CH05264A (pt) | ||
BR112015030741A2 (pt) | teste de toque independente para manipulações de tela de toque e zoom de toque duplo | |
BR112015016012A2 (pt) | método e dispositivo para transferência de recursos |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
B08F | Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette] | ||
B08K | Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette] |