IN2013CH04449A - - Google Patents

Info

Publication number
IN2013CH04449A
IN2013CH04449A IN4449CH2013A IN2013CH04449A IN 2013CH04449 A IN2013CH04449 A IN 2013CH04449A IN 4449CH2013 A IN4449CH2013 A IN 4449CH2013A IN 2013CH04449 A IN2013CH04449 A IN 2013CH04449A
Authority
IN
India
Prior art keywords
data block
core
stored
ready state
stored data
Prior art date
Application number
Other languages
English (en)
Inventor
Vajapeyam Sriram
Original Assignee
Empire Technology Dev Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Empire Technology Dev Llc filed Critical Empire Technology Dev Llc
Priority to IN4449CH2013 priority Critical patent/IN2013CH04449A/en
Priority to US14/383,895 priority patent/US9864709B2/en
Publication of IN2013CH04449A publication Critical patent/IN2013CH04449A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G06F2212/622—State-only directory, i.e. not recording identity of sharing or owning nodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
IN4449CH2013 2013-09-30 2013-09-30 IN2013CH04449A (pt)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IN4449CH2013 IN2013CH04449A (pt) 2013-09-30 2013-09-30
US14/383,895 US9864709B2 (en) 2013-09-30 2013-11-21 Data transfer in a multi-core processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IN4449CH2013 IN2013CH04449A (pt) 2013-09-30 2013-09-30

Publications (1)

Publication Number Publication Date
IN2013CH04449A true IN2013CH04449A (pt) 2015-04-03

Family

ID=54209872

Family Applications (1)

Application Number Title Priority Date Filing Date
IN4449CH2013 IN2013CH04449A (pt) 2013-09-30 2013-09-30

Country Status (2)

Country Link
US (1) US9864709B2 (pt)
IN (1) IN2013CH04449A (pt)

Cited By (1)

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JP5949977B1 (ja) * 2015-02-19 2016-07-13 日本電気株式会社 情報処理装置、情報処理方法、メインプロセッサコア、プログラム、情報処理方法、サブプロセッサコア
CN105427368B (zh) * 2015-11-17 2018-03-20 上海兆芯集成电路有限公司 数据单元的关联性检查方法以及使用该方法的装置
CN108986015B (zh) * 2015-11-17 2022-12-06 格兰菲智能科技有限公司 数据单元的关联性检查方法以及使用该方法的装置
CN105243685B (zh) * 2015-11-17 2018-01-02 上海兆芯集成电路有限公司 数据单元的关联性检查方法以及使用该方法的装置
CN110413210B (zh) * 2018-04-28 2023-05-30 伊姆西Ip控股有限责任公司 用于处理数据的方法、设备和计算机程序产品
US11269799B2 (en) * 2019-05-03 2022-03-08 Arm Limited Cluster of processing elements having split mode and lock mode
CN112732628A (zh) * 2019-10-29 2021-04-30 Oppo广东移动通信有限公司 核间数据处理方法、系统、片上系统以及电子设备
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CN116594758B (zh) * 2023-07-18 2023-09-26 山东三未信安信息科技有限公司 一种密码模块调用优化系统及优化方法

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115114192A (zh) * 2021-03-23 2022-09-27 北京灵汐科技有限公司 存储器接口、功能核、众核系统和存储数据访问方法

Also Published As

Publication number Publication date
US9864709B2 (en) 2018-01-09
US20150286597A1 (en) 2015-10-08

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