BR112015029848A8 - dispositivos de recepção e de transmissão, métodos para recepção de um dispositivo de recepção e para transmissão de um dispositivo de transmissão, e, meio de armazenamento legível por computador - Google Patents

dispositivos de recepção e de transmissão, métodos para recepção de um dispositivo de recepção e para transmissão de um dispositivo de transmissão, e, meio de armazenamento legível por computador Download PDF

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Publication number
BR112015029848A8
BR112015029848A8 BR112015029848A BR112015029848A BR112015029848A8 BR 112015029848 A8 BR112015029848 A8 BR 112015029848A8 BR 112015029848 A BR112015029848 A BR 112015029848A BR 112015029848 A BR112015029848 A BR 112015029848A BR 112015029848 A8 BR112015029848 A8 BR 112015029848A8
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BR
Brazil
Prior art keywords
receiving
transmitting
memory
devices
computer
Prior art date
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BR112015029848A
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English (en)
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BR112015029848B1 (pt
BR112015029848A2 (pt
Inventor
K Ramanujan Raj
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Intel Corp
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Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR112015029848A2 publication Critical patent/BR112015029848A2/pt
Publication of BR112015029848A8 publication Critical patent/BR112015029848A8/pt
Publication of BR112015029848B1 publication Critical patent/BR112015029848B1/pt

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0851—Cache with interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/31—Providing disk cache in a specific location of a storage system
    • G06F2212/311—In host system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • Memory System (AREA)
  • Dram (AREA)

Abstract

resumo patente de invenção para: "dispositivo de memória híbrido". trata-se de dispositivos de memória, controladores e dispositivos eletrônicos que compreendem dispositivos de memória. em uma modalidade, um dispositivo de memória compreende uma memória volátil, uma memória não volátil e um controlador que compreende um armazenamento temporário de memória e uma lógica para transferir dados entre a memória não volátil e a memória volátil por meio do armazenamento temporário de memória em resposta a solicitações de um aplicativo, em que os dados no armazenamento temporário de memória são acessíveis ao aplicativo. além disso, outras modalidades são reveladas e reivindicadas.
BR112015029848-6A 2013-06-27 2014-06-23 Sistema compreendendo um dispositivo de memória e um driver de sistema operacional para gerenciar operações de acesso a memória entre pelo menos um aplicativo e o dispositivo de memória BR112015029848B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/928,694 2013-06-27
US13/928,694 US9129674B2 (en) 2013-06-27 2013-06-27 Hybrid memory device
PCT/US2014/043678 WO2014209891A1 (en) 2013-06-27 2014-06-23 Hybrid memory device

Publications (3)

Publication Number Publication Date
BR112015029848A2 BR112015029848A2 (pt) 2017-07-25
BR112015029848A8 true BR112015029848A8 (pt) 2019-12-24
BR112015029848B1 BR112015029848B1 (pt) 2022-12-13

Family

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BR112015029848-6A BR112015029848B1 (pt) 2013-06-27 2014-06-23 Sistema compreendendo um dispositivo de memória e um driver de sistema operacional para gerenciar operações de acesso a memória entre pelo menos um aplicativo e o dispositivo de memória

Country Status (9)

Country Link
US (1) US9129674B2 (pt)
EP (1) EP3014623B1 (pt)
JP (1) JP6112594B2 (pt)
KR (1) KR101719092B1 (pt)
CN (1) CN105247617B (pt)
BR (1) BR112015029848B1 (pt)
RU (1) RU2627100C2 (pt)
TW (1) TWI537725B (pt)
WO (1) WO2014209891A1 (pt)

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Also Published As

Publication number Publication date
RU2015151127A (ru) 2017-05-31
JP2016523411A (ja) 2016-08-08
TWI537725B (zh) 2016-06-11
US20150003175A1 (en) 2015-01-01
RU2627100C2 (ru) 2017-08-03
BR112015029848B1 (pt) 2022-12-13
EP3014623B1 (en) 2019-03-13
CN105247617A (zh) 2016-01-13
EP3014623A1 (en) 2016-05-04
KR20150140361A (ko) 2015-12-15
BR112015029848A2 (pt) 2017-07-25
TW201508483A (zh) 2015-03-01
JP6112594B2 (ja) 2017-04-12
EP3014623A4 (en) 2017-03-01
US9129674B2 (en) 2015-09-08
CN105247617B (zh) 2020-06-12
WO2014209891A1 (en) 2014-12-31
KR101719092B1 (ko) 2017-04-04

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B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B350 Update of information on the portal [chapter 15.35 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

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