SG11201600354TA - Computing architecture with peripherals - Google Patents

Computing architecture with peripherals

Info

Publication number
SG11201600354TA
SG11201600354TA SG11201600354TA SG11201600354TA SG11201600354TA SG 11201600354T A SG11201600354T A SG 11201600354TA SG 11201600354T A SG11201600354T A SG 11201600354TA SG 11201600354T A SG11201600354T A SG 11201600354TA SG 11201600354T A SG11201600354T A SG 11201600354TA
Authority
SG
Singapore
Prior art keywords
peripherals
computing architecture
architecture
computing
Prior art date
Application number
SG11201600354TA
Other languages
English (en)
Inventor
Benjamin Gittins
Original Assignee
Benjamin Aaron Gittins
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from AU2013902678A external-priority patent/AU2013902678A0/en
Application filed by Benjamin Aaron Gittins filed Critical Benjamin Aaron Gittins
Publication of SG11201600354TA publication Critical patent/SG11201600354TA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/082—Associative directories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/372—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a time-dependent priority, e.g. individually loaded time counters or time slot
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/065—Replication mechanisms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/067—Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28—Using a specific disk cache architecture
    • G06F2212/283—Plural cache memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6032—Way prediction in set-associative cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
SG11201600354TA 2013-07-18 2014-07-17 Computing architecture with peripherals SG11201600354TA (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
AU2013902678A AU2013902678A0 (en) 2013-07-18 Computing architecture with peripherals
AU2013904532A AU2013904532A0 (en) 2013-11-25 Computing architecture with peripherals
PCT/IB2014/063189 WO2015008251A2 (en) 2013-07-18 2014-07-17 Computing architecture with peripherals

Publications (1)

Publication Number Publication Date
SG11201600354TA true SG11201600354TA (en) 2016-03-30

Family

ID=51585139

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201600354TA SG11201600354TA (en) 2013-07-18 2014-07-17 Computing architecture with peripherals

Country Status (8)

Country Link
US (5) US10210117B2 (pt)
EP (1) EP3022655A2 (pt)
AU (1) AU2014291635B2 (pt)
BR (5) BR112016001014A2 (pt)
CA (1) CA2924881A1 (pt)
IL (2) IL243619A0 (pt)
SG (1) SG11201600354TA (pt)
WO (1) WO2015008251A2 (pt)

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* Cited by examiner, † Cited by third party
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FR3003054B1 (fr) * 2013-03-06 2016-08-19 Sagem Defense Securite Procede et dispositif de filtrage de transactions pour systeme sur puce
BR112016001014A2 (pt) * 2013-07-18 2017-08-22 Benjamin A Gittins Computing architecture with peripherals
US9578054B1 (en) * 2015-08-31 2017-02-21 Newman H-R Computer Design, LLC Hacking-resistant computer design
JP6575260B2 (ja) * 2015-09-18 2019-09-18 富士通株式会社 帯域管理装置、帯域管理方法および帯域管理プログラム
EP3188025A1 (en) * 2015-12-29 2017-07-05 Teknologian Tutkimuskeskus VTT Oy Memory node with cache for emulated shared memory computers
US9997232B2 (en) 2016-03-10 2018-06-12 Micron Technology, Inc. Processing in memory (PIM) capable memory device having sensing circuitry performing logic operations
US10282321B1 (en) * 2017-01-19 2019-05-07 Marvell Israel (M.I.S.L) Ltd. Systems and methods for serial input and selective output mechanism for exchanging data at a network device
JP6979777B2 (ja) * 2017-03-22 2021-12-15 キヤノン株式会社 インターフェース装置およびその制御方法
US10592424B2 (en) * 2017-07-14 2020-03-17 Arm Limited Range-based memory system
US10613979B2 (en) 2017-11-30 2020-04-07 International Business Machines Corporation Accelerator memory coherency with single state machine
US10437750B2 (en) * 2017-12-21 2019-10-08 Arm Limited Relative data width indication for read responses routed by an interconnect
US11880314B1 (en) * 2018-07-27 2024-01-23 Dialog Semiconductor B.V. Microcontroller for driving an external device
US11409643B2 (en) * 2019-11-06 2022-08-09 Honeywell International Inc Systems and methods for simulating worst-case contention to determine worst-case execution time of applications executed on a processor
CN115794727A (zh) * 2022-11-03 2023-03-14 格兰菲智能科技有限公司 缓存系统构造方法和装置

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Also Published As

Publication number Publication date
EP3022655A2 (en) 2016-05-25
BR112016001013A2 (pt) 2017-08-22
AU2014291635A1 (en) 2016-03-10
BR112016001015A2 (pt) 2017-08-22
US20160321205A1 (en) 2016-11-03
NZ716954A (en) 2021-02-26
AU2014291635B2 (en) 2019-11-07
BR112016001014A2 (pt) 2017-08-22
US20160154753A1 (en) 2016-06-02
CA2924881A1 (en) 2015-01-22
US20160299857A1 (en) 2016-10-13
WO2015008251A2 (en) 2015-01-22
IL243619A0 (en) 2016-02-29
US20160275015A1 (en) 2016-09-22
US10210117B2 (en) 2019-02-19
BR112016001011A2 (pt) 2017-08-22
US20160299714A1 (en) 2016-10-13
WO2015008251A3 (en) 2015-05-28
IL243652A0 (en) 2016-02-29
BR112016000972A2 (pt) 2017-08-22

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