BR112015019459A2 - sistema de memória - Google Patents
sistema de memóriaInfo
- Publication number
- BR112015019459A2 BR112015019459A2 BR112015019459A BR112015019459A BR112015019459A2 BR 112015019459 A2 BR112015019459 A2 BR 112015019459A2 BR 112015019459 A BR112015019459 A BR 112015019459A BR 112015019459 A BR112015019459 A BR 112015019459A BR 112015019459 A2 BR112015019459 A2 BR 112015019459A2
- Authority
- BR
- Brazil
- Prior art keywords
- pulse width
- request signal
- host memory
- memory controller
- memory system
- Prior art date
Links
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0766—Error or fault reporting or storing
- G06F11/0772—Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/079—Root cause analysis, i.e. error or fault diagnosis
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1663—Access to shared memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1678—Details of memory controller using bus width
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1694—Configuration of memory controller to different memory types
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40618—Refresh operations over multiple banks or interleaving
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1003—Interface circuits for daisy chain or ring bus memory arrangements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
- H04L9/0869—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving random numbers or seeds
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1041—Resource optimization
- G06F2212/1044—Space efficiency improvement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/25—Using a specific main memory architecture
- G06F2212/253—Centralized memory
- G06F2212/2532—Centralized memory comprising a plurality of modules
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Quality & Reliability (AREA)
- Mathematical Physics (AREA)
- Health & Medical Sciences (AREA)
- Biomedical Technology (AREA)
- Computer Hardware Design (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Security & Cryptography (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Memory System (AREA)
- Dram (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
resumo "sistema de memória" trata-se de um dispositivo para uso em um módulo de memória acoplado a um controlador de memória do host através de um barramento, que compreende lógica de controle de módulo de memória para gerar um sinal de solicitação para um controlador de memória do host que tem uma largura de pulso maior que ou igual a uma largura de pulso mínima, em que a largura de pulso mínima compreende um número de ciclos de relógio necessário para garantir que o controlador de memória do host detecte o sinal de solicitação, e em que a largura de pulso do sinal de solicitação indica pelo menos uma função em adição ao sinal de solicitação para o controlador de memória do host 25632886v1 25632886v1
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2013/032633 WO2014143056A1 (en) | 2013-03-15 | 2013-03-15 | A memory system |
Publications (2)
Publication Number | Publication Date |
---|---|
BR112015019459A2 true BR112015019459A2 (pt) | 2017-07-18 |
BR112015019459B1 BR112015019459B1 (pt) | 2021-10-19 |
Family
ID=51537392
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR122016006764-5A BR122016006764B1 (pt) | 2013-03-15 | 2013-03-15 | Aparelhos e métodos de memória |
BR122016007765-9A BR122016007765B1 (pt) | 2013-03-15 | 2013-03-15 | Aparelho em comunicação com controlador de memória de host, aparelho acoplado a um módulo de memória e métodos para formar conjuntos eletrônicos |
BR122016006765-3A BR122016006765B1 (pt) | 2013-03-15 | 2013-03-15 | Aparelho acoplado ao módulo de memória, sistema de memória e método |
BR112015019459-1A BR112015019459B1 (pt) | 2013-03-15 | 2013-03-15 | Dispositivo para uso em um módulo de memória e método realizado em um módulo de memória |
Family Applications Before (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR122016006764-5A BR122016006764B1 (pt) | 2013-03-15 | 2013-03-15 | Aparelhos e métodos de memória |
BR122016007765-9A BR122016007765B1 (pt) | 2013-03-15 | 2013-03-15 | Aparelho em comunicação com controlador de memória de host, aparelho acoplado a um módulo de memória e métodos para formar conjuntos eletrônicos |
BR122016006765-3A BR122016006765B1 (pt) | 2013-03-15 | 2013-03-15 | Aparelho acoplado ao módulo de memória, sistema de memória e método |
Country Status (8)
Country | Link |
---|---|
US (11) | US9990246B2 (pt) |
EP (1) | EP2973571B1 (pt) |
JP (1) | JP6139010B2 (pt) |
KR (2) | KR101670917B1 (pt) |
CN (1) | CN104981872B (pt) |
BR (4) | BR122016006764B1 (pt) |
RU (1) | RU2628124C2 (pt) |
WO (1) | WO2014143056A1 (pt) |
Families Citing this family (76)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6139010B2 (ja) | 2013-03-15 | 2017-05-31 | インテル・コーポレーション | デバイス |
US10001948B2 (en) * | 2013-05-13 | 2018-06-19 | Rambus Inc. | Buffer circuit with data bit inversion |
US9740423B2 (en) * | 2013-07-26 | 2017-08-22 | Hitachi, Ltd. | Computer system |
IN2013CH04449A (pt) * | 2013-09-30 | 2015-04-03 | Empire Technology Dev Llc | |
US9484070B2 (en) * | 2014-04-30 | 2016-11-01 | Micron Technology, Inc. | Apparatuses supporting multiple interface types and methods of operating the same |
WO2016081192A1 (en) * | 2014-11-20 | 2016-05-26 | Rambus Inc. | Memory systems and methods for improved power management |
US10528410B2 (en) * | 2014-12-16 | 2020-01-07 | Intel Corporation | Apparatus, method and system to exchange error information in a unified protocol communication |
US9524249B2 (en) * | 2014-12-23 | 2016-12-20 | Intel Corporation | Memory encryption engine integration |
CN107112043B (zh) | 2015-01-28 | 2021-01-29 | 惠普发展公司有限责任合伙企业 | 支持不同类型的存储器装置 |
US9594689B2 (en) * | 2015-02-09 | 2017-03-14 | International Business Machines Corporation | Designated cache data backup during system operation |
US10387259B2 (en) | 2015-06-26 | 2019-08-20 | Intel Corporation | Instant restart in non volatile system memory computing systems with embedded programmable data checking |
JP2017045311A (ja) * | 2015-08-27 | 2017-03-02 | 株式会社東芝 | メモリシステム |
US10031677B1 (en) | 2015-10-14 | 2018-07-24 | Rambus Inc. | High-throughput low-latency hybrid memory module |
CN106611608B (zh) * | 2015-10-23 | 2019-01-15 | 群联电子股份有限公司 | 存储器控制电路单元、存储器储存装置与数据传输方法 |
US9792224B2 (en) | 2015-10-23 | 2017-10-17 | Intel Corporation | Reducing latency by persisting data relationships in relation to corresponding data in persistent memory |
JP2017097825A (ja) * | 2015-11-16 | 2017-06-01 | 株式会社東芝 | ホスト機器および拡張デバイス |
US10503686B2 (en) * | 2015-12-09 | 2019-12-10 | Microchip Technology Incorporated | SPI interface with automatic slave select generation |
US10163508B2 (en) | 2016-02-26 | 2018-12-25 | Intel Corporation | Supporting multiple memory types in a memory slot |
US9785359B2 (en) * | 2016-02-26 | 2017-10-10 | Intel Corporation | Sending packets using optimized PIO write sequences without sfences and out of order credit returns |
US10621119B2 (en) | 2016-03-03 | 2020-04-14 | Samsung Electronics Co., Ltd. | Asynchronous communication protocol compatible with synchronous DDR protocol |
US10592114B2 (en) * | 2016-03-03 | 2020-03-17 | Samsung Electronics Co., Ltd. | Coordinated in-module RAS features for synchronous DDR compatible memory |
US10310547B2 (en) * | 2016-03-05 | 2019-06-04 | Intel Corporation | Techniques to mirror a command/address or interpret command/address logic at a memory device |
US10152237B2 (en) * | 2016-05-05 | 2018-12-11 | Micron Technology, Inc. | Non-deterministic memory protocol |
KR102525229B1 (ko) | 2016-05-13 | 2023-04-25 | 에스케이하이닉스 주식회사 | 메모리 모듈 및 이를 포함하는 시스템 |
US10163485B2 (en) * | 2016-05-25 | 2018-12-25 | Mediatek Inc. | Memory module, memory controller and associated control method for read training technique |
US10198204B2 (en) | 2016-06-01 | 2019-02-05 | Advanced Micro Devices, Inc. | Self refresh state machine MOP array |
US10459855B2 (en) | 2016-07-01 | 2019-10-29 | Intel Corporation | Load reduced nonvolatile memory interface |
KR102679057B1 (ko) * | 2016-08-18 | 2024-07-02 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 메모리 시스템의 동작방법 |
US20180059933A1 (en) * | 2016-08-26 | 2018-03-01 | Sandisk Technologies Llc | Electrically-Buffered NV-DIMM and Method for Use Therewith |
US10359933B2 (en) * | 2016-09-19 | 2019-07-23 | Micron Technology, Inc. | Memory devices and electronic systems having a hybrid cache including static and dynamic caches with single and multiple bits per cell, and related methods |
CN107885671B (zh) | 2016-09-30 | 2021-09-14 | 华为技术有限公司 | 一种非易失性内存的持久化方法和计算设备 |
US10521351B2 (en) * | 2017-01-12 | 2019-12-31 | International Business Machines Corporation | Temporarily suppressing processing of a restrained storage operand request |
US10180793B2 (en) * | 2017-01-31 | 2019-01-15 | Hewlett Packard Enterprise Development Lp | Performance attributes for memory |
US10846018B2 (en) * | 2017-04-05 | 2020-11-24 | Mediatek Inc. | Memory device, memory controller and associated memory system operated according to selected clock signals |
EP3605541A4 (en) | 2017-04-14 | 2020-04-01 | Huawei Technologies Co., Ltd. | MEMORY REFRESHING TECHNOLOGY AND COMPUTER SYSTEM |
CN107291421A (zh) * | 2017-06-09 | 2017-10-24 | 中国电子科技集团公司第四十研究所 | 一种可编程图形序列发生系统及方法 |
US10162406B1 (en) * | 2017-08-31 | 2018-12-25 | Micron Technology, Inc. | Systems and methods for frequency mode detection and implementation |
JP2019046051A (ja) * | 2017-08-31 | 2019-03-22 | 東芝メモリ株式会社 | メモリ装置およびデータ処理装置 |
US10908820B2 (en) | 2017-09-14 | 2021-02-02 | Samsung Electronics Co., Ltd. | Host-based and client-based command scheduling in large bandwidth memory systems |
US10996888B2 (en) * | 2017-10-31 | 2021-05-04 | Qualcomm Incorporated | Write credits management for non-volatile memory |
US10769074B2 (en) | 2017-11-09 | 2020-09-08 | Microsoft Technology Licensing, Llc | Computer memory content movement |
DE102018124375A1 (de) * | 2017-11-21 | 2019-05-23 | Samsung Electronics Co., Ltd. | Betriebsverfahren eines signalempfängers, pulsbreitensteuerungund elektronische vorrichtung mit denselben |
KR102370278B1 (ko) * | 2017-11-30 | 2022-03-07 | 에스케이하이닉스 주식회사 | 메모리 컨트롤러, 이를 포함하는 메모리 시스템, 및 그의 동작방법 |
KR102493964B1 (ko) | 2017-12-18 | 2023-02-01 | 삼성전자주식회사 | 스토리지 컨트롤러, 그것을 포함하는 스토리지 장치, 및 스토리지 컨트롤러의 동작 방법 |
US11226768B2 (en) * | 2018-01-04 | 2022-01-18 | Montage Technology Co., Ltd. | Memory controller and method for accessing memory module |
US10929029B2 (en) | 2018-01-04 | 2021-02-23 | Montage Technology Co., Ltd. | Memory controller and method for accessing memory modules and processing sub-modules |
CN110008147B (zh) * | 2018-01-04 | 2021-11-19 | 澜起科技股份有限公司 | 存储器控制器以及用于对存储模块进行访问的方法 |
US11048645B2 (en) | 2018-02-01 | 2021-06-29 | Samsung Electronics Co., Ltd. | Memory module, operation method therof, and operation method of host |
US11099995B2 (en) | 2018-03-28 | 2021-08-24 | Intel Corporation | Techniques for prefetching data to a first level of memory of a hierarchical arrangement of memory |
US10714159B2 (en) * | 2018-05-09 | 2020-07-14 | Micron Technology, Inc. | Indication in memory system or sub-system of latency associated with performing an access command |
US10963404B2 (en) | 2018-06-25 | 2021-03-30 | Intel Corporation | High bandwidth DIMM |
US10884958B2 (en) | 2018-06-25 | 2021-01-05 | Intel Corporation | DIMM for a high bandwidth memory channel |
KR102029035B1 (ko) * | 2018-07-26 | 2019-10-07 | 주식회사 우리비전 | 메인 보드 리버스 인터커넥션을 통한 메모리 모듈의 실장 테스트에 사용되는 메모리 모듈을 수납하는 메인 보드 |
US10782916B2 (en) | 2018-08-08 | 2020-09-22 | Micron Technology, Inc. | Proactive return of write credits in a memory system |
US11074007B2 (en) * | 2018-08-08 | 2021-07-27 | Micron Technology, Inc. | Optimize information requests to a memory system |
US10969994B2 (en) | 2018-08-08 | 2021-04-06 | Micron Technology, Inc. | Throttle response signals from a memory system |
US11409436B2 (en) | 2018-08-08 | 2022-08-09 | Micron Technology, Inc. | Buffer management in memory systems for read and write requests |
US11061751B2 (en) * | 2018-09-06 | 2021-07-13 | Micron Technology, Inc. | Providing bandwidth expansion for a memory sub-system including a sequencer separate from a controller |
US11080210B2 (en) * | 2018-09-06 | 2021-08-03 | Micron Technology, Inc. | Memory sub-system including an in package sequencer separate from a controller |
US10740031B2 (en) | 2018-09-25 | 2020-08-11 | International Business Machines Corporation | Interface scheduler for a distributed memory system |
KR20200040183A (ko) | 2018-10-08 | 2020-04-17 | 박흥균 | 라인 형태의 전자빔 방출 장치 |
US11650943B2 (en) | 2018-10-16 | 2023-05-16 | Micron Technology, Inc. | Flexible bus management |
US10901657B2 (en) | 2018-11-29 | 2021-01-26 | International Business Machines Corporation | Dynamic write credit buffer management of non-volatile dual inline memory module |
US11403035B2 (en) * | 2018-12-19 | 2022-08-02 | Micron Technology, Inc. | Memory module including a controller and interfaces for communicating with a host and another memory module |
US10606794B1 (en) * | 2019-05-14 | 2020-03-31 | Infineon Technologies Ag | Clock signal monitor for slave device on a master-slave bus |
KR20200142219A (ko) * | 2019-06-12 | 2020-12-22 | 삼성전자주식회사 | 전자 장치 및 그의 저장 공간 이용 방법 |
US11249539B2 (en) | 2019-06-28 | 2022-02-15 | Integrated Device Technology, Inc. | DDR5 client PMIC power up sequence and state transitions |
US11699471B2 (en) | 2019-09-25 | 2023-07-11 | Intel Corporation | Synchronous dynamic random access memory (SDRAM) dual in-line memory module (DIMM) having increased per data pin bandwidth |
JP7419010B2 (ja) * | 2019-10-04 | 2024-01-22 | キヤノン株式会社 | データ処理システムおよびデータ処理システムの制御方法 |
US11656673B2 (en) * | 2019-12-30 | 2023-05-23 | Micron Technology, Inc. | Managing reduced power memory operations |
US11182312B2 (en) | 2020-04-02 | 2021-11-23 | Micron Technology, Inc. | Memory sub-system manufacturing mode |
US11372544B2 (en) * | 2020-09-24 | 2022-06-28 | Netapp, Inc. | Write type based crediting for block level write throttling to control impact to read input/output operations |
US11709538B2 (en) * | 2020-11-19 | 2023-07-25 | Micron Technology, Inc. | Minimizing power loss and reset time with media controller suspend |
US11609868B1 (en) * | 2020-12-31 | 2023-03-21 | Waymo Llc | Control calibration timing to avoid memory write blackout period |
US11842056B2 (en) * | 2021-10-25 | 2023-12-12 | EMC IP Holding Company, LLC | System and method for allocating storage system resources during write throttling |
KR20230155145A (ko) * | 2022-05-03 | 2023-11-10 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 그것의 동작 방법 |
Family Cites Families (98)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4148099A (en) | 1978-04-11 | 1979-04-03 | Ncr Corporation | Memory device having a minimum number of pins |
US5448706A (en) * | 1992-05-13 | 1995-09-05 | Sharp Microelectronics Technology, Inc. | Address generator for multi-channel circular-buffer style processing |
JP3369227B2 (ja) | 1992-11-09 | 2003-01-20 | 株式会社東芝 | プロセッサ |
US5555250A (en) | 1994-10-14 | 1996-09-10 | Compaq Computer Corporation | Data error detection and correction system |
US5784390A (en) | 1995-06-19 | 1998-07-21 | Seagate Technology, Inc. | Fast AtA-compatible drive interface with error detection and/or error correction |
US5805905A (en) | 1995-09-06 | 1998-09-08 | Opti Inc. | Method and apparatus for arbitrating requests at two or more levels of priority using a single request line |
US5610745A (en) * | 1995-10-26 | 1997-03-11 | Hewlett-Packard Co. | Method and apparatus for tracking buffer availability |
JPH1078934A (ja) | 1996-07-01 | 1998-03-24 | Sun Microsyst Inc | パケット切替えコンピュータ・システムのマルチサイズ・バス結合システム |
US6260101B1 (en) | 1997-03-07 | 2001-07-10 | Advanced Micro Devices, Inc. | Microcontroller having dedicated hardware for memory address space expansion supporting both static and dynamic memory devices |
AU1798999A (en) | 1997-12-05 | 1999-06-28 | Intel Corporation | Memory system including a memory module having a memory module controller |
US6088762A (en) | 1998-06-19 | 2000-07-11 | Intel Corporation | Power failure mode for a memory controller |
US6260127B1 (en) | 1998-07-13 | 2001-07-10 | Compaq Computer Corporation | Method and apparatus for supporting heterogeneous memory in computer systems |
US6457081B1 (en) | 1998-11-23 | 2002-09-24 | Advanced Micro Devices, Inc. | Packet protocol for reading an indeterminate number of data bytes across a computer interconnection bus |
US7356639B2 (en) * | 2000-01-05 | 2008-04-08 | Rambus Inc. | Configurable width buffered module having a bypass circuit |
US7363422B2 (en) * | 2000-01-05 | 2008-04-22 | Rambus Inc. | Configurable width buffered module |
US6683884B1 (en) | 2000-03-31 | 2004-01-27 | Intel Corporation | Shared credit round robin queuing |
US7100028B2 (en) | 2000-08-09 | 2006-08-29 | Advanced Micro Devices, Inc. | Multiple entry points for system call instructions |
US6625685B1 (en) | 2000-09-20 | 2003-09-23 | Broadcom Corporation | Memory controller with programmable configuration |
US6931128B2 (en) | 2001-01-16 | 2005-08-16 | Microsoft Corporation | Methods and systems for generating encryption keys using random bit generators |
US6658523B2 (en) | 2001-03-13 | 2003-12-02 | Micron Technology, Inc. | System latency levelization for read data |
US6615217B2 (en) * | 2001-06-29 | 2003-09-02 | Bull Hn Information Systems Inc. | Method and data processing system providing bulk record memory transfers across multiple heterogeneous computer systems |
JP3912091B2 (ja) * | 2001-12-04 | 2007-05-09 | ソニー株式会社 | データ通信システム、データ送信装置、データ受信装置、および方法、並びにコンピュータ・プログラム |
KR100408419B1 (ko) * | 2001-12-19 | 2003-12-06 | 삼성전자주식회사 | 반도체 메모리 장치의 동작 타이밍 제어회로 및 동작타이밍 제어 방법 |
US7076678B2 (en) * | 2002-02-11 | 2006-07-11 | Micron Technology, Inc. | Method and apparatus for data transfer |
US6781911B2 (en) | 2002-04-09 | 2004-08-24 | Intel Corporation | Early power-down digital memory device and method |
US7469420B2 (en) | 2002-05-21 | 2008-12-23 | Thomson Licensing | Key transport tamper protection |
JP4222803B2 (ja) * | 2002-09-11 | 2009-02-12 | Necエレクトロニクス株式会社 | データ処理装置およびデータ処理回路 |
KR100524952B1 (ko) | 2003-03-07 | 2005-11-01 | 삼성전자주식회사 | 기록 매체의 데이터 보호 방법 및 이를 이용한 디스크드라이브 |
US7234099B2 (en) | 2003-04-14 | 2007-06-19 | International Business Machines Corporation | High reliability memory module with a fault tolerant address and command bus |
KR100475125B1 (ko) | 2003-06-21 | 2005-03-14 | 삼성전자주식회사 | 데이터 버스 폭 변경이 자유로운 이동형 저장 장치 및이에 대한 데이터 버스 폭 설정 방법 |
JP2005025903A (ja) | 2003-07-01 | 2005-01-27 | Nec Micro Systems Ltd | 半導体記憶装置 |
CA2538308C (en) | 2003-09-10 | 2013-05-14 | Qualcomm Incorporated | High data rate interface |
US7177989B1 (en) | 2003-12-31 | 2007-02-13 | Intel Corporation | Retry of a device read transaction |
KR100840441B1 (ko) | 2004-03-31 | 2008-06-20 | 마이크론 테크놀로지, 인크. | 집적 회로들에서의 신호 타이밍의 재구성 |
US8200879B1 (en) * | 2004-06-29 | 2012-06-12 | National Semiconductor Corporation | Memory interface including an efficient variable-width bus |
US8032674B2 (en) | 2004-07-19 | 2011-10-04 | Marvell International Ltd. | System and method for controlling buffer memory overflow and underflow conditions in storage controllers |
US7660938B1 (en) | 2004-10-01 | 2010-02-09 | Super Talent Electronics, Inc. | Flash card reader and data exchanger utilizing low power extended USB protocol without polling |
US7525986B2 (en) | 2004-10-28 | 2009-04-28 | Intel Corporation | Starvation prevention scheme for a fixed priority PCI-Express arbiter with grant counters using arbitration pools |
US7571296B2 (en) * | 2004-11-11 | 2009-08-04 | Nvidia Corporation | Memory controller-adaptive 1T/2T timing control |
US7966439B1 (en) * | 2004-11-24 | 2011-06-21 | Nvidia Corporation | Apparatus, system, and method for a fast data return memory controller |
US20060117160A1 (en) * | 2004-12-01 | 2006-06-01 | Intel Corporation | Method to consolidate memory usage to reduce power consumption |
US9384818B2 (en) * | 2005-04-21 | 2016-07-05 | Violin Memory | Memory power management |
US7319612B2 (en) * | 2005-05-18 | 2008-01-15 | Intel Corporation | Performing multiple read operations via a single read command |
US8335894B1 (en) * | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
US8327104B2 (en) * | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
JP2007004522A (ja) | 2005-06-24 | 2007-01-11 | Renesas Technology Corp | 記憶装置 |
US8055833B2 (en) * | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
DE102005035207A1 (de) | 2005-07-27 | 2007-02-01 | Siemens Ag | Verfahren und Vorrichtung zur Datenübertragung zwischen zwei relativ zueinander bewegten Komponenten |
US7426607B2 (en) | 2005-08-05 | 2008-09-16 | Infineon Technologies Ag | Memory system and method of operating memory system |
US20110022850A1 (en) | 2006-07-26 | 2011-01-27 | Hondar Lee | Access control for secure portable storage device |
US8272781B2 (en) | 2006-08-01 | 2012-09-25 | Intel Corporation | Dynamic power control of a memory device thermal sensor |
US7900079B2 (en) | 2006-08-11 | 2011-03-01 | International Business Machines Corporation | Data capture window synchronizing method for generating data bit sequences and adjusting capture window on parallel data paths |
US7761725B2 (en) | 2006-08-30 | 2010-07-20 | Ati Technologies Ulc | Clock generation for synchronous circuits with slow settling control signals |
JP5056762B2 (ja) | 2006-10-24 | 2012-10-24 | 富士通株式会社 | データパケット送受信システム、データパケット送受信方法およびデータパケット送受信プログラム |
US8122202B2 (en) | 2007-02-16 | 2012-02-21 | Peter Gillingham | Reduced pin count interface |
US7624225B2 (en) | 2007-03-22 | 2009-11-24 | International Business Machines Corporation | System and method for providing synchronous dynamic random access memory (SDRAM) mode register shadowing in a memory system |
US8874831B2 (en) | 2007-06-01 | 2014-10-28 | Netlist, Inc. | Flash-DRAM hybrid memory module |
US7624211B2 (en) | 2007-06-27 | 2009-11-24 | Micron Technology, Inc. | Method for bus width negotiation of data storage devices |
US7787375B2 (en) | 2007-08-06 | 2010-08-31 | International Business Machines Corporation | Performing a recovery action in response to a credit depletion notification |
US7882324B2 (en) | 2007-10-30 | 2011-02-01 | Qimonda Ag | Method and apparatus for synchronizing memory enabled systems with master-slave architecture |
US7971081B2 (en) * | 2007-12-28 | 2011-06-28 | Intel Corporation | System and method for fast platform hibernate and resume |
US8045416B2 (en) | 2008-03-05 | 2011-10-25 | Micron Technology, Inc. | Method and memory device providing reduced quantity of interconnections |
US8255783B2 (en) | 2008-04-23 | 2012-08-28 | International Business Machines Corporation | Apparatus, system and method for providing error protection for data-masking bits |
US8154918B2 (en) | 2008-06-30 | 2012-04-10 | Sandisk Il Ltd. | Method for page- and block based scrambling in non-volatile memory |
TWI370361B (en) * | 2008-08-21 | 2012-08-11 | Ili Technology Corp | Memory access controlling apparatus and control method thereof |
US8639874B2 (en) | 2008-12-22 | 2014-01-28 | International Business Machines Corporation | Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device |
WO2010101835A1 (en) | 2009-03-02 | 2010-09-10 | The Board Of Trustees Of The University Of Illinois | Decoupled memory modules: building high-bandwidth memory systems from low-speed dynamic random access memory devices |
TWI416523B (zh) | 2009-06-10 | 2013-11-21 | Silicon Motion Inc | 非揮發性記憶體之寫入錯誤管理方法、非揮發性記憶體、記憶卡、以及非揮發性記憶體之控制器 |
KR101585213B1 (ko) | 2009-08-18 | 2016-01-13 | 삼성전자주식회사 | 라이트 레벨링 동작을 수행하기 위한 메모리 장치의 제어 방법, 메모리 장치의 라이트 레벨링 방법, 및 라이트 레벨링 동작을 수행하는 메모리 컨트롤러, 메모리 장치, 및 메모리 시스템 |
US8447908B2 (en) | 2009-09-07 | 2013-05-21 | Bitmicro Networks, Inc. | Multilevel memory bus system for solid-state mass storage |
US8862966B2 (en) * | 2009-09-09 | 2014-10-14 | Advanced Micro Devices, Inc. | Adjustment of write timing based on error detection techniques |
US8996785B2 (en) | 2009-09-21 | 2015-03-31 | Aplus Flash Technology, Inc. | NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface |
KR101620348B1 (ko) | 2009-10-16 | 2016-05-12 | 삼성전자주식회사 | 내부전원 발생장치, 이를 구비한 멀티채널 메모리 장치 및 이를 채용한 프로세싱 시스템 |
US8862973B2 (en) * | 2009-12-09 | 2014-10-14 | Intel Corporation | Method and system for error management in a memory device |
JP5421152B2 (ja) | 2010-03-08 | 2014-02-19 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
JP5139465B2 (ja) | 2010-03-31 | 2013-02-06 | 株式会社東芝 | メモリチップ、情報記憶システム、読み出し装置 |
US8339891B2 (en) | 2010-05-25 | 2012-12-25 | Lsi Corporation | Power savings and/or dynamic power management in a memory |
US8898511B2 (en) | 2010-06-24 | 2014-11-25 | International Business Machines Corporation | Homogeneous recovery in a redundant memory system |
US8972723B2 (en) | 2010-07-14 | 2015-03-03 | Sandisk Technologies Inc. | Storage device and method for providing a partially-encrypted content file to a host device |
BR112013006329B1 (pt) * | 2010-09-16 | 2020-12-01 | Apple Inc. | controlador de memória compreendendo uma pluralidade de portas, circuito integrado e método |
US8615638B2 (en) | 2010-10-08 | 2013-12-24 | Qualcomm Incorporated | Memory controllers, systems and methods for applying page management policies based on stream transaction information |
JP5032647B2 (ja) | 2010-11-26 | 2012-09-26 | 株式会社東芝 | データ記憶装置、コントロール装置及び暗号化方法 |
US8410819B2 (en) * | 2010-12-29 | 2013-04-02 | Stmicroelectronics, Inc. | Programmable pulse width discriminator |
US8321649B2 (en) | 2011-03-18 | 2012-11-27 | Freescale Semiconductor, Inc. | Memory controller address and data pin multiplexing |
US8665665B2 (en) * | 2011-03-30 | 2014-03-04 | Mediatek Inc. | Apparatus and method to adjust clock duty cycle of memory |
US8930647B1 (en) | 2011-04-06 | 2015-01-06 | P4tents1, LLC | Multiple class memory systems |
US9069703B2 (en) | 2011-04-29 | 2015-06-30 | Seagate Technology Llc | Encrypted-transport solid-state disk controller |
JP5720470B2 (ja) | 2011-07-27 | 2015-05-20 | 富士通株式会社 | 処理装置,試験信号生成装置及び試験信号生成方法 |
US9025409B2 (en) * | 2011-08-05 | 2015-05-05 | Rambus Inc. | Memory buffers and modules supporting dynamic point-to-point connections |
US9047418B2 (en) * | 2011-11-22 | 2015-06-02 | Icron Technologies Corporation | Methods and devices for extending USB 3.0-compliant communication |
US9330031B2 (en) | 2011-12-09 | 2016-05-03 | Nvidia Corporation | System and method for calibration of serial links using a serial-to-parallel loopback |
US9417998B2 (en) * | 2012-01-26 | 2016-08-16 | Memory Technologies Llc | Apparatus and method to provide cache move with non-volatile mass memory system |
US8638153B2 (en) * | 2012-03-29 | 2014-01-28 | Qualcomm Incorporated | Pulse clock generation logic with built-in level shifter and programmable rising edge and pulse width |
US8667205B2 (en) | 2012-04-30 | 2014-03-04 | International Business Machines Corporation | Deadlock resolution in end-to-end credit protocol |
JP5836903B2 (ja) * | 2012-09-04 | 2015-12-24 | 株式会社東芝 | 情報処理装置 |
US8730750B1 (en) * | 2012-10-28 | 2014-05-20 | Lsi Corporation | Memory device with control circuitry for generating a reset signal in read and write modes of operation |
US20140122777A1 (en) | 2012-10-31 | 2014-05-01 | Mosaid Technologies Incorporated | Flash memory controller having multi mode pin-out |
JP6139010B2 (ja) | 2013-03-15 | 2017-05-31 | インテル・コーポレーション | デバイス |
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2013
- 2013-03-15 JP JP2016500074A patent/JP6139010B2/ja not_active Expired - Fee Related
- 2013-03-15 BR BR122016006764-5A patent/BR122016006764B1/pt active IP Right Grant
- 2013-03-15 RU RU2015134146A patent/RU2628124C2/ru active
- 2013-03-15 EP EP13877923.6A patent/EP2973571B1/en active Active
- 2013-03-15 US US13/977,653 patent/US9990246B2/en active Active
- 2013-03-15 BR BR122016007765-9A patent/BR122016007765B1/pt active IP Right Grant
- 2013-03-15 CN CN201380073070.3A patent/CN104981872B/zh active Active
- 2013-03-15 KR KR1020157022074A patent/KR101670917B1/ko active IP Right Grant
- 2013-03-15 WO PCT/US2013/032633 patent/WO2014143056A1/en active Application Filing
- 2013-03-15 KR KR1020167029790A patent/KR20160127168A/ko not_active Application Discontinuation
- 2013-03-15 BR BR122016006765-3A patent/BR122016006765B1/pt active IP Right Grant
- 2013-03-15 BR BR112015019459-1A patent/BR112015019459B1/pt active IP Right Grant
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2015
- 2015-12-11 US US14/967,230 patent/US10198306B2/en active Active
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2016
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