US7426607B2 - Memory system and method of operating memory system - Google Patents
Memory system and method of operating memory system Download PDFInfo
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- US7426607B2 US7426607B2 US11/198,246 US19824605A US7426607B2 US 7426607 B2 US7426607 B2 US 7426607B2 US 19824605 A US19824605 A US 19824605A US 7426607 B2 US7426607 B2 US 7426607B2
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- memory
- random access
- address
- memory component
- data bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1694—Configuration of memory controller to different memory types
Definitions
- the present invention relates to a semiconductor memory system, and in particular, to a memory system including a shared interface for semiconductor memories.
- flash memory and random access memory are utilized within the same system.
- many mobile applications such as cellular phones, used NAND flash memory to store code and use low-power RAM to allow execution at faster speeds.
- low-power single data rate (LP-SDR) or low-power double data rate (LP-DDR) can be provided to allow fast speed execution, while a NAND or NOR flash memory may be provided to store code.
- L-SDR low-power single data rate
- LP-DDR low-power double data rate
- NOR flash memory may be provided to store code.
- this combination of NAND flash and LP-DDR or LP-SDR memories have become quite common.
- One aspect of the present invention provides a random access memory system with a memory controller, a first memory device, a second memory device, and a memory bus.
- the memory controller is configured to control access to a plurality of memory devices.
- the memory bus is configured to alternatively couple the memory controller to the first memory device and to couple the memory controller to the second memory.
- FIG. 1A illustrates a block diagram of a system having a flash memory and a RAM.
- FIG. 1B illustrates a block diagram of a system having a flash memory and a RAM.
- FIG. 2 illustrates a system having a RAM and a flash memory with a shared interface in accordance with one embodiment of the present invention.
- FIG. 3 illustrates a portion of a pin interface of a memory subsystem in accordance with one embodiment of the present invention.
- FIG. 4 illustrates an exemplary timing diagram of a memory subsystem in accordance with one embodiment of the present invention.
- FIG. 5 illustrates an exemplary timing diagram of a memory subsystem in accordance with one embodiment of the present invention.
- FIG. 1A illustrates memory subsystem 10 .
- Memory subsystem 10 includes host memory controller 12 , flash memory 14 , and random access memory (RAM) 16 .
- Flash memory 14 is coupled to host memory device 12 via an external memory bus. Flash memory 14 is further coupled to RAM 16 via an external memory bus.
- flash memory 14 is a NOR flash device and RAM 16 is an SRAM. In another case, flash memory 14 is a NAND flash device and/or RAM 16 a PSRAM.
- memory subsystem 10 may be suitable for application in a low to mid-range cellular phone segment.
- application software is resident on flash memory 14 in the form of execute-in-place (XIP) code. Since flash memory tends to be relatively slower, the XIP code in flash memory 14 then utilizes RAM 16 as working memory when more speed is needed.
- XIP execute-in-place
- FIG. 1B illustrates memory subsystem 20 .
- Memory subsystem 20 includes host memory controller 22 , flash memory 24 and random access memory (RAM) 26 .
- Host memory controller 22 is coupled to both flash memory 24 and RAM 26 via an external memory bus, which in one case provides parallel connection of both memory devices to memory controller 22 .
- RAM 26 is a low-power single data rate (LP-SDR) RAM and flash memory 24 is a NAND flash device.
- L-DDR low-power double data rate
- flash memory 24 is a NOR flash device.
- memory subsystem 20 is suitable for application in mid to high-range cellular phones segments.
- memory system 20 utilizes flash memory 24 to store application code and data, and then uses a faster RAM 26 for execution and work with the data.
- the connection between host memory controller 22 and flash memory 24 is slow relative to the connection between host controller 22 and RAM 26 .
- a system configured as memory subsystem 20 may utilize a shadowing technique where code resident in flash memory 24 is mainly working with a low-power SDR or DDR such as RAM 26 .
- FIG. 2 illustrates memory subsystem 30 in accordance with one embodiment of the present invention.
- Memory subsystem 30 includes host memory controller 32 , random access memory (RAM) 34 and flash memory 36 .
- Host controller 32 and RAM 34 are coupled via an external memory bus.
- flash memory 36 and RAM 34 are coupled to host memory controller 32 via the same external memory bus and are multiplexed with host memory controller 32 .
- RAM 34 is a low-power single data rate (LP-SDR) RAM and flash memory 36 is a NAND flash device.
- L-DDR low-power double data rate
- flash memory 36 is a NOR flash device.
- memory subsystem 30 is suitable for application in middle to high-end cellular phone segments.
- application software and data are stored mainly in flash memory 36 .
- Host memory controller 32 then accesses this code, and any data in flash memory 36 , via the external memory bus.
- host controller 32 can also access RAM 34 via the same external memory bus, and utilize this low-power high-speed RAM to perform operations there.
- host controller 32 again via multiplexing, can access flash memory 36 for these purposes.
- FIG. 3 illustrates further detail of a memory subsystem 50 in accordance with one embodiment of the present invention. Specific pin interface of memory subsystem 50 is illustrated.
- Memory subsystem 50 includes memory controller 52 , RAM interface 54 , and flash interface 56 . Further, multiplexed address and data lines (MUX A/D) 58 in accordance with one embodiment of the invention, is illustrated between RAM interface 54 and flash interface 56 .
- MUX A/D multiplexed address and data lines
- RAM interface 54 includes conventional RAM interface pins.
- RAM interface 54 is an interface for a low-power DDR or a low-power SDR type RAM device.
- RAM interface 54 includes open pins 1 , 2 , and 3 .
- nWE write enable
- nCAS column address strobe
- nRAS row address strobe
- RAM interface 54 also includes a chip select signal (nCS) pin, a clock (CLK) pin, a complimentary clock (nCLK) pin, and a clock enable (CKE) pin.
- nCS chip select signal
- CLK clock
- nCLK complimentary clock
- CKE clock enable
- RAM interface 54 also includes write mask or data mask (DM) pins, and DQ pins and DQS pins for the echo clock of DQs.
- DM write mask or data mask
- the DQS pins provide a right data strobe on time edge-aligned for read and center-aligned for write.
- the DQ is 16 bits, and in another it is 32 bits.
- Flash interface 56 also includes conventional flash interface pins.
- Flash interface 56 is an interface for a NAND flash device or a NOR flash device. Illustrated on the flash interface 56 are a read enable (nRE) pin, a ready (RDY) pin, a chip enable (bCE) pin, a write enable (nWE) pin, a address latch enable (ALE) pin and a command latch enable (CLE) pin.
- the read enable (nRE) pin, the ready (RDY) pin, and the chip enable (bCE) pin on the flash interface 56 are respectively coupled to pins 1 , 2 and 3 (which can be used to provide additional functionality where needed) on RAM interface 54 .
- the write enable (nWE) pins on RAM interface 54 and flash interface 56 are coupled together, and the address latch enable (ALE) pin and the command latch enable (CLE) pins on the flash interface 56 are respectively coupled to the column address strobe (nCAS) pin and the row address strobe (nRAS) pin on RAM interface 54 .
- ALE address latch enable
- CLE command latch enable
- address and data (A/D) pins between memory controller 52 and RAM interface 54 and between memory controller 52 and flash interface 56 are multiplexed via MUX A/D 58 .
- 16 A/D pins (A 15 -A 0 and I/O 15 -I/O 0 ) are multiplexed.
- 8 pins A/D pins (for example, A 7 -A 0 and I/O 7 -I/O 0 ) are used in 8 byte applications.
- MUX A/D 58 allows shared pin connections with memory controller 52 by both RAM interface 54 and flash interface 56 , no additional pins are needed to couple flash interface 56 to memory controller 52 than are already used to couple RAM interface 54 to memory controller 52 . This saves space on the PCB, and in one case, saves over 20 pins on memory controller 52 .
- FIG. 4 illustrates an exemplary timing diagram of a memory subsystem, such as memory subsystem 50 , in accordance with one embodiment of the present invention. Signals are temporally illustrated horizontally across the figure, and each is labeled with the corresponding pin or pins from memory subsystem 50 of FIG. 3 .
- memory controller 52 In operation of memory subsystem 50 , memory controller 52 alternatively accesses RAM interface 54 and flash interface 56 as needed, via MUX A/D 58 .
- a clock signal (CLK) is illustrated at the top of the figure.
- a read command for the RAM interface 54 is applied at pins nRAS, nCAS and mWE and a corresponding address command comes in from memory controller 52 via the A/D pins, as indicated by ADR in the figure.
- memory controller 52 sets the address where the RAM is to be accessed. After some latency, data is then accessed from the specified address location as indicated by the DQ bus pins labeled Q 0 , Q 1 , Q 2 , Q 3 , Q 4 -Qn.
- the address bus is idle such that there is no transaction relative to the RAM. In this way, memory system 50 exploits this idle time of the address bus to access commands for the flash memory.
- the shaded area labeled “Bus taken by NAND,” illustrates how, in one embodiment, the data and address bus executes commands in the flash memory via A/D pins I/O 7 -I/O 0 .
- Corresponding read commands are indicated (“Read NAND) on the command CLE, ALE, nWE pins.
- memory controller 52 controls access to RAM and flash memory via chip select (nCS) and chip enable (bCE), respectively.
- nCS chip select
- bCE chip enable
- control of the A/D bus in taken by the flash memory when control of the A/D bus in taken by the flash memory, it is asynchronous such that the flash memory does not have to track the main clock.
- the clock to the RAM such as a low power DDR, is relatively fast, such as 100 MHz or higher. Since flash memory maintains a relatively slower access, such as a 20-25 nanosecond cycle, memory controller 52 does not have to synchronize this command with the main clock.
- FIG. 5 illustrates another exemplary timing diagram of a memory subsystem, such as memory subsystem 50 , in accordance with one embodiment of the present invention. Signals are temporally illustrated horizontally across the figure, and each is labeled with the corresponding pin or pins from memory subsystem 50 of FIG. 3 .
- FIG. 5 an additional example of accessing of the flash memory by memory controller 52 via multiplexing is illustrated.
- the flash memory is being accessed.
- the chip select (nCS) is high and the chip enable (nCE) is low such that the command and address signals are applied for the flash memory.
- Control of the A/D bus is illustrated by the shaded area labeled “NAND serial output.”
- data such as Q a , Q a +1, etc. is read out serially.
- controller 52 then has need to access the RAM. In this way, controller 52 brings the read enable (nRE) high. Then with read enable high, the flash memory releases the address bus. Further, when the chip enable (nCE) transitions high and the chip select (nCS) transitions low, the RAM takes control of the A/D bus and the command and address signals are applied for the RAM. The appropriate read command and address are then placed so the RAM is accessed.
- the chip enable (nCE) transitions low and the chip select (nCS) transitions high so that the flash memory can continue serially reading data, Q a +2, Q a +3, Q a +4, etc., out of the flash memory during latency when data Q 0 , Q 1 , Q 2 , and Q 3 are read from the RAM in response to the asserted read command.
- the RAM has priority and is master over the flash memory relative to the multiplexing controlled by memory controller 52 . Since in one case the RAM is clocked at a relatively fast rate, for example at 100 MHz, whereas the flash memory is clocking more on the order of 5 microseconds, there is plenty of time to do much of the RAM operation and data control while the controller is otherwise waiting for the NAND data and commands.
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Abstract
Description
Claims (12)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/198,246 US7426607B2 (en) | 2005-08-05 | 2005-08-05 | Memory system and method of operating memory system |
DE102006035870A DE102006035870A1 (en) | 2005-08-05 | 2006-08-01 | Semiconductor memory with shared interface |
CNA2006101515570A CN1924847A (en) | 2005-08-05 | 2006-08-04 | Shared interface semiconductor memories |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US11/198,246 US7426607B2 (en) | 2005-08-05 | 2005-08-05 | Memory system and method of operating memory system |
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US20070033336A1 US20070033336A1 (en) | 2007-02-08 |
US7426607B2 true US7426607B2 (en) | 2008-09-16 |
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US11/198,246 Active 2026-05-03 US7426607B2 (en) | 2005-08-05 | 2005-08-05 | Memory system and method of operating memory system |
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US (1) | US7426607B2 (en) |
CN (1) | CN1924847A (en) |
DE (1) | DE102006035870A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090177909A1 (en) * | 2006-12-13 | 2009-07-09 | Texas Instruments Incorporated | Memory bus shared system |
Families Citing this family (13)
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US7451263B2 (en) * | 2006-02-08 | 2008-11-11 | Infineon Technologies Ag | Shared interface for components in an embedded system |
US7752373B2 (en) * | 2007-02-09 | 2010-07-06 | Sigmatel, Inc. | System and method for controlling memory operations |
US8767450B2 (en) * | 2007-08-21 | 2014-07-01 | Samsung Electronics Co., Ltd. | Memory controllers to refresh memory sectors in response to writing signals and memory systems including the same |
KR20100134375A (en) * | 2009-06-15 | 2010-12-23 | 삼성전자주식회사 | Memory system conducting refresh operation |
WO2009055150A1 (en) * | 2007-10-19 | 2009-04-30 | Rambus Inc. | Reconfigurable point-to-point memory interface |
US8700830B2 (en) | 2007-11-20 | 2014-04-15 | Spansion Llc | Memory buffering system that improves read/write performance and provides low latency for mobile systems |
WO2009111175A1 (en) * | 2008-03-06 | 2009-09-11 | Rambus Inc. | Error detection and offset cancellation during multi-wire communication |
WO2010011534A1 (en) * | 2008-07-23 | 2010-01-28 | Rambus Inc. | Reconfigurable memory controller |
US20110022769A1 (en) * | 2009-07-26 | 2011-01-27 | Cpo Technologies Corporation | Translation USB Intermediate Device and Data Rate Apportionment USB Intermediate Device |
KR101626084B1 (en) * | 2009-11-25 | 2016-06-01 | 삼성전자주식회사 | Multi-chip memory system and data transfer method thereof |
US20130073790A1 (en) * | 2011-09-16 | 2013-03-21 | Avalanche Technology, Inc. | Magnetic random access memory with burst access |
US8990594B2 (en) * | 2012-08-28 | 2015-03-24 | Energy Pass Incorporation | Apparatus for measuring a remaining power of a battery includes a first memory for storing a routine code and a second memory for storing an exception code |
US9990246B2 (en) | 2013-03-15 | 2018-06-05 | Intel Corporation | Memory system |
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- 2005-08-05 US US11/198,246 patent/US7426607B2/en active Active
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- 2006-08-04 CN CNA2006101515570A patent/CN1924847A/en active Pending
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Also Published As
Publication number | Publication date |
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CN1924847A (en) | 2007-03-07 |
DE102006035870A1 (en) | 2007-03-22 |
US20070033336A1 (en) | 2007-02-08 |
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