BR0008704A - Célula de sram com tensões de limiar duplas comcontrole de dispersão de linhas de bits - Google Patents

Célula de sram com tensões de limiar duplas comcontrole de dispersão de linhas de bits

Info

Publication number
BR0008704A
BR0008704A BR0008704-1A BR0008704A BR0008704A BR 0008704 A BR0008704 A BR 0008704A BR 0008704 A BR0008704 A BR 0008704A BR 0008704 A BR0008704 A BR 0008704A
Authority
BR
Brazil
Prior art keywords
word
bit line
line
transistors
lines
Prior art date
Application number
BR0008704-1A
Other languages
English (en)
Portuguese (pt)
Inventor
Ali Keshavarzi
Kevin Zhang
Yibin Ye
Vivek De
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR0008704A publication Critical patent/BR0008704A/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
BR0008704-1A 1999-03-03 2000-02-17 Célula de sram com tensões de limiar duplas comcontrole de dispersão de linhas de bits BR0008704A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/261,915 US6181608B1 (en) 1999-03-03 1999-03-03 Dual Vt SRAM cell with bitline leakage control
PCT/US2000/004239 WO2000052702A1 (en) 1999-03-03 2000-02-17 Dual threshold voltage sram cell with bit line leakage control

Publications (1)

Publication Number Publication Date
BR0008704A true BR0008704A (pt) 2001-12-26

Family

ID=22995437

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0008704-1A BR0008704A (pt) 1999-03-03 2000-02-17 Célula de sram com tensões de limiar duplas comcontrole de dispersão de linhas de bits

Country Status (10)

Country Link
US (1) US6181608B1 (https=)
EP (1) EP1155413B1 (https=)
JP (1) JP2002538615A (https=)
KR (1) KR100479670B1 (https=)
CN (1) CN1253897C (https=)
AU (1) AU3001700A (https=)
BR (1) BR0008704A (https=)
DE (1) DE60029757T2 (https=)
TW (1) TW463169B (https=)
WO (1) WO2000052702A1 (https=)

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KR100993517B1 (ko) * 2002-03-27 2010-11-10 더 리전트 오브 더 유니버시티 오브 캘리포니아 집적 회로, 집적 회로 구동 회로, 및 관련방법
US6683804B1 (en) * 2002-07-16 2004-01-27 Analog Devices, Inc. Read/write memory arrays and methods with predetermined and retrievable latent-state patterns
DE10255102B3 (de) * 2002-11-26 2004-04-29 Infineon Technologies Ag SRAM-Speicherzelle mit Mitteln zur Erzielung eines vom Speicherzustand unabhängigen Leckstroms
US6724649B1 (en) * 2002-12-19 2004-04-20 Intel Corporation Memory cell leakage reduction
US7200050B2 (en) * 2003-05-26 2007-04-03 Semiconductor Energy Laboratory Co., Ltd. Memory unit and semiconductor device
CA2529667A1 (en) * 2003-07-01 2005-01-20 Zmos Technology, Inc Sram cell structure and circuits
US6920061B2 (en) * 2003-08-27 2005-07-19 International Business Machines Corporation Loadless NMOS four transistor dynamic dual Vt SRAM cell
JP2005142289A (ja) * 2003-11-05 2005-06-02 Toshiba Corp 半導体記憶装置
US7123500B2 (en) * 2003-12-30 2006-10-17 Intel Corporation 1P1N 2T gain cell
JP4342350B2 (ja) * 2004-03-11 2009-10-14 株式会社東芝 半導体メモリ装置
US7061794B1 (en) * 2004-03-30 2006-06-13 Virage Logic Corp. Wordline-based source-biasing scheme for reducing memory cell leakage
US7469465B2 (en) * 2004-06-30 2008-12-30 Hitachi Global Storage Technologies Netherlands B.V. Method of providing a low-stress sensor configuration for a lithography-defined read sensor
US7079426B2 (en) * 2004-09-27 2006-07-18 Intel Corporation Dynamic multi-Vcc scheme for SRAM cell stability control
US7110278B2 (en) * 2004-09-29 2006-09-19 Intel Corporation Crosspoint memory array utilizing one time programmable antifuse cells
US7321502B2 (en) * 2004-09-30 2008-01-22 Intel Corporation Non volatile data storage through dielectric breakdown
US7321504B2 (en) * 2005-04-21 2008-01-22 Micron Technology, Inc Static random access memory cell
KR100699857B1 (ko) * 2005-07-30 2007-03-27 삼성전자주식회사 무부하 에스램, 그 동작 방법 및 그 제조 방법
US7230842B2 (en) * 2005-09-13 2007-06-12 Intel Corporation Memory cell having p-type pass device
JP2007122814A (ja) * 2005-10-28 2007-05-17 Oki Electric Ind Co Ltd 半導体集積回路及びリーク電流低減方法
US20070153610A1 (en) * 2005-12-29 2007-07-05 Intel Corporation Dynamic body bias with bias boost
US8006164B2 (en) 2006-09-29 2011-08-23 Intel Corporation Memory cell supply voltage control based on error detection
US7558097B2 (en) * 2006-12-28 2009-07-07 Intel Corporation Memory having bit line with resistor(s) between memory cells
US8009461B2 (en) * 2008-01-07 2011-08-30 International Business Machines Corporation SRAM device, and SRAM device design structure, with adaptable access transistors
JP2009295229A (ja) * 2008-06-05 2009-12-17 Toshiba Corp 半導体記憶装置
US20110149667A1 (en) * 2009-12-23 2011-06-23 Fatih Hamzaoglu Reduced area memory array by using sense amplifier as write driver
US9858986B2 (en) * 2010-08-02 2018-01-02 Texas Instruments Incorporated Integrated circuit with low power SRAM
US9111638B2 (en) * 2012-07-13 2015-08-18 Freescale Semiconductor, Inc. SRAM bit cell with reduced bit line pre-charge voltage
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
WO2015009331A1 (en) * 2013-07-15 2015-01-22 Everspin Technologies, Inc. Memory device with page emulation mode
CN109859791B (zh) * 2019-01-31 2020-08-28 西安微电子技术研究所 一种全隔离结构9管sram存储单元及其读写操作方法
CN110277120B (zh) * 2019-06-27 2021-05-14 电子科技大学 一种在低压下提升读写稳定性的单端8管sram存储单元电路
CN111755048B (zh) * 2020-06-22 2024-11-29 上海华力微电子有限公司 下字线驱动读辅助电路和版图设计
US12580008B2 (en) 2024-02-08 2026-03-17 Arm Limited Power gating circuit with memory precharge support
US12525284B2 (en) 2024-02-08 2026-01-13 Arm Limited Column select topology supporting increased throughput for writes to memory
US20250259671A1 (en) * 2024-02-08 2025-08-14 Arm Limited Increased throughput for reads in static random access memory

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Also Published As

Publication number Publication date
JP2002538615A (ja) 2002-11-12
AU3001700A (en) 2000-09-21
DE60029757D1 (en) 2006-09-14
CN1253897C (zh) 2006-04-26
CN1357145A (zh) 2002-07-03
WO2000052702A1 (en) 2000-09-08
EP1155413B1 (en) 2006-08-02
US6181608B1 (en) 2001-01-30
HK1037778A1 (en) 2002-02-15
TW463169B (en) 2001-11-11
EP1155413A1 (en) 2001-11-21
KR20010102476A (ko) 2001-11-15
DE60029757T2 (de) 2007-10-31
KR100479670B1 (ko) 2005-03-30

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 7A, 8A E 9A ANUIDADES

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 NA RPI2003 DE 26/05/2009.