TW463169B - Dual VT SRAM cell with bitline leakage control - Google Patents
Dual VT SRAM cell with bitline leakage control Download PDFInfo
- Publication number
- TW463169B TW463169B TW089103802A TW89103802A TW463169B TW 463169 B TW463169 B TW 463169B TW 089103802 A TW089103802 A TW 089103802A TW 89103802 A TW89103802 A TW 89103802A TW 463169 B TW463169 B TW 463169B
- Authority
- TW
- Taiwan
- Prior art keywords
- line
- word line
- integrated circuit
- signal
- millivolts
- Prior art date
Links
- 230000009977 dual effect Effects 0.000 title 1
- 239000013078 crystal Substances 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 15
- 238000009825 accumulation Methods 0.000 claims 1
- 239000003990 capacitor Substances 0.000 claims 1
- 229910052715 tantalum Inorganic materials 0.000 claims 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims 1
- 230000007423 decrease Effects 0.000 description 9
- 239000000872 buffer Substances 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 230000006698 induction Effects 0.000 description 4
- 230000001939 inductive effect Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/418—Address circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/261,915 US6181608B1 (en) | 1999-03-03 | 1999-03-03 | Dual Vt SRAM cell with bitline leakage control |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW463169B true TW463169B (en) | 2001-11-11 |
Family
ID=22995437
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW089103802A TW463169B (en) | 1999-03-03 | 2000-03-10 | Dual VT SRAM cell with bitline leakage control |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US6181608B1 (https=) |
| EP (1) | EP1155413B1 (https=) |
| JP (1) | JP2002538615A (https=) |
| KR (1) | KR100479670B1 (https=) |
| CN (1) | CN1253897C (https=) |
| AU (1) | AU3001700A (https=) |
| BR (1) | BR0008704A (https=) |
| DE (1) | DE60029757T2 (https=) |
| TW (1) | TW463169B (https=) |
| WO (1) | WO2000052702A1 (https=) |
Families Citing this family (40)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002056681A (ja) * | 2000-08-09 | 2002-02-22 | Toshiba Corp | メモリ装置 |
| US6519176B1 (en) * | 2000-09-29 | 2003-02-11 | Intel Corporation | Dual threshold SRAM cell for single-ended sensing |
| TWI242085B (en) * | 2001-03-29 | 2005-10-21 | Sanyo Electric Co | Display device |
| US6946901B2 (en) * | 2001-05-22 | 2005-09-20 | The Regents Of The University Of California | Low-power high-performance integrated circuit and related methods |
| US6628557B2 (en) | 2001-09-28 | 2003-09-30 | Intel Corporation | Leakage-tolerant memory arrangements |
| KR100993517B1 (ko) * | 2002-03-27 | 2010-11-10 | 더 리전트 오브 더 유니버시티 오브 캘리포니아 | 집적 회로, 집적 회로 구동 회로, 및 관련방법 |
| US6683804B1 (en) * | 2002-07-16 | 2004-01-27 | Analog Devices, Inc. | Read/write memory arrays and methods with predetermined and retrievable latent-state patterns |
| DE10255102B3 (de) * | 2002-11-26 | 2004-04-29 | Infineon Technologies Ag | SRAM-Speicherzelle mit Mitteln zur Erzielung eines vom Speicherzustand unabhängigen Leckstroms |
| US6724649B1 (en) * | 2002-12-19 | 2004-04-20 | Intel Corporation | Memory cell leakage reduction |
| US7200050B2 (en) * | 2003-05-26 | 2007-04-03 | Semiconductor Energy Laboratory Co., Ltd. | Memory unit and semiconductor device |
| CA2529667A1 (en) * | 2003-07-01 | 2005-01-20 | Zmos Technology, Inc | Sram cell structure and circuits |
| US6920061B2 (en) * | 2003-08-27 | 2005-07-19 | International Business Machines Corporation | Loadless NMOS four transistor dynamic dual Vt SRAM cell |
| JP2005142289A (ja) * | 2003-11-05 | 2005-06-02 | Toshiba Corp | 半導体記憶装置 |
| US7123500B2 (en) * | 2003-12-30 | 2006-10-17 | Intel Corporation | 1P1N 2T gain cell |
| JP4342350B2 (ja) * | 2004-03-11 | 2009-10-14 | 株式会社東芝 | 半導体メモリ装置 |
| US7061794B1 (en) * | 2004-03-30 | 2006-06-13 | Virage Logic Corp. | Wordline-based source-biasing scheme for reducing memory cell leakage |
| US7469465B2 (en) * | 2004-06-30 | 2008-12-30 | Hitachi Global Storage Technologies Netherlands B.V. | Method of providing a low-stress sensor configuration for a lithography-defined read sensor |
| US7079426B2 (en) * | 2004-09-27 | 2006-07-18 | Intel Corporation | Dynamic multi-Vcc scheme for SRAM cell stability control |
| US7110278B2 (en) * | 2004-09-29 | 2006-09-19 | Intel Corporation | Crosspoint memory array utilizing one time programmable antifuse cells |
| US7321502B2 (en) * | 2004-09-30 | 2008-01-22 | Intel Corporation | Non volatile data storage through dielectric breakdown |
| US7321504B2 (en) * | 2005-04-21 | 2008-01-22 | Micron Technology, Inc | Static random access memory cell |
| KR100699857B1 (ko) * | 2005-07-30 | 2007-03-27 | 삼성전자주식회사 | 무부하 에스램, 그 동작 방법 및 그 제조 방법 |
| US7230842B2 (en) * | 2005-09-13 | 2007-06-12 | Intel Corporation | Memory cell having p-type pass device |
| JP2007122814A (ja) * | 2005-10-28 | 2007-05-17 | Oki Electric Ind Co Ltd | 半導体集積回路及びリーク電流低減方法 |
| US20070153610A1 (en) * | 2005-12-29 | 2007-07-05 | Intel Corporation | Dynamic body bias with bias boost |
| US8006164B2 (en) | 2006-09-29 | 2011-08-23 | Intel Corporation | Memory cell supply voltage control based on error detection |
| US7558097B2 (en) * | 2006-12-28 | 2009-07-07 | Intel Corporation | Memory having bit line with resistor(s) between memory cells |
| US8009461B2 (en) * | 2008-01-07 | 2011-08-30 | International Business Machines Corporation | SRAM device, and SRAM device design structure, with adaptable access transistors |
| JP2009295229A (ja) * | 2008-06-05 | 2009-12-17 | Toshiba Corp | 半導体記憶装置 |
| US20110149667A1 (en) * | 2009-12-23 | 2011-06-23 | Fatih Hamzaoglu | Reduced area memory array by using sense amplifier as write driver |
| US9858986B2 (en) * | 2010-08-02 | 2018-01-02 | Texas Instruments Incorporated | Integrated circuit with low power SRAM |
| US9111638B2 (en) * | 2012-07-13 | 2015-08-18 | Freescale Semiconductor, Inc. | SRAM bit cell with reduced bit line pre-charge voltage |
| US9070477B1 (en) | 2012-12-12 | 2015-06-30 | Mie Fujitsu Semiconductor Limited | Bit interleaved low voltage static random access memory (SRAM) and related methods |
| WO2015009331A1 (en) * | 2013-07-15 | 2015-01-22 | Everspin Technologies, Inc. | Memory device with page emulation mode |
| CN109859791B (zh) * | 2019-01-31 | 2020-08-28 | 西安微电子技术研究所 | 一种全隔离结构9管sram存储单元及其读写操作方法 |
| CN110277120B (zh) * | 2019-06-27 | 2021-05-14 | 电子科技大学 | 一种在低压下提升读写稳定性的单端8管sram存储单元电路 |
| CN111755048B (zh) * | 2020-06-22 | 2024-11-29 | 上海华力微电子有限公司 | 下字线驱动读辅助电路和版图设计 |
| US12580008B2 (en) | 2024-02-08 | 2026-03-17 | Arm Limited | Power gating circuit with memory precharge support |
| US12525284B2 (en) | 2024-02-08 | 2026-01-13 | Arm Limited | Column select topology supporting increased throughput for writes to memory |
| US20250259671A1 (en) * | 2024-02-08 | 2025-08-14 | Arm Limited | Increased throughput for reads in static random access memory |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5153852A (en) * | 1988-07-01 | 1992-10-06 | Vitesse Semiconductor Corporation | Static RAM cell with high speed and improved cell stability |
| JPH0340294A (ja) | 1989-07-05 | 1991-02-21 | Mitsubishi Electric Corp | スタティック型半導体記憶装置 |
| JP3076351B2 (ja) * | 1990-04-09 | 2000-08-14 | 株式会社リコー | バッテリバックアップ付半導体記憶装置 |
| US5222039A (en) * | 1990-11-28 | 1993-06-22 | Thunderbird Technologies, Inc. | Static random access memory (SRAM) including Fermi-threshold field effect transistors |
| US5732015A (en) * | 1991-04-23 | 1998-03-24 | Waferscale Integration, Inc. | SRAM with a programmable reference voltage |
| US5461713A (en) * | 1991-05-10 | 1995-10-24 | Sgs-Thomson Microelectronics S.R.L. | Current offset sense amplifier of a modulated current or current unbalance type for programmable memories |
| US5452246A (en) | 1993-06-02 | 1995-09-19 | Fujitsu Limited | Static semiconductor memory device adapted for stabilization of low-voltage operation and reduction in cell size |
| US5393689A (en) * | 1994-02-28 | 1995-02-28 | Motorola, Inc. | Process for forming a static-random-access memory cell |
| US5471421A (en) | 1994-12-16 | 1995-11-28 | Sun Microsystems, Inc. | Storage cell using low powered/low threshold CMOS pass transistors having reduced charge leakage |
| DE69615421T2 (de) * | 1995-01-12 | 2002-06-06 | Intergraph Corp., Huntsville | Registerspeicher mit Umleitungsmöglichkeit |
| US5703392A (en) * | 1995-06-02 | 1997-12-30 | Utron Technology Inc | Minimum size integrated circuit static memory cell |
| JP4198201B2 (ja) * | 1995-06-02 | 2008-12-17 | 株式会社ルネサステクノロジ | 半導体装置 |
| KR0182960B1 (ko) * | 1995-08-31 | 1999-04-15 | 김광호 | 반도체 메모리의 칩 면적을 줄일수 있는 비트라인 로드회로 |
| JPH09270494A (ja) * | 1996-01-31 | 1997-10-14 | Hitachi Ltd | 半導体集積回路装置 |
| US5790452A (en) * | 1996-05-02 | 1998-08-04 | Integrated Device Technology, Inc. | Memory cell having asymmetrical source/drain pass transistors and method for operating same |
| US5828597A (en) * | 1997-04-02 | 1998-10-27 | Texas Instruments Incorporated | Low voltage, low power static random access memory cell |
| US5939762A (en) | 1997-06-26 | 1999-08-17 | Integrated Device Technology, Inc. | SRAM cell using thin gate oxide pulldown transistors |
-
1999
- 1999-03-03 US US09/261,915 patent/US6181608B1/en not_active Expired - Lifetime
-
2000
- 2000-02-17 WO PCT/US2000/004239 patent/WO2000052702A1/en not_active Ceased
- 2000-02-17 DE DE60029757T patent/DE60029757T2/de not_active Expired - Lifetime
- 2000-02-17 EP EP00908724A patent/EP1155413B1/en not_active Expired - Lifetime
- 2000-02-17 BR BR0008704-1A patent/BR0008704A/pt not_active IP Right Cessation
- 2000-02-17 CN CNB008071195A patent/CN1253897C/zh not_active Expired - Fee Related
- 2000-02-17 KR KR10-2001-7011169A patent/KR100479670B1/ko not_active Expired - Fee Related
- 2000-02-17 JP JP2000603043A patent/JP2002538615A/ja active Pending
- 2000-02-17 AU AU30017/00A patent/AU3001700A/en not_active Abandoned
- 2000-03-10 TW TW089103802A patent/TW463169B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| JP2002538615A (ja) | 2002-11-12 |
| AU3001700A (en) | 2000-09-21 |
| DE60029757D1 (en) | 2006-09-14 |
| CN1253897C (zh) | 2006-04-26 |
| BR0008704A (pt) | 2001-12-26 |
| CN1357145A (zh) | 2002-07-03 |
| WO2000052702A1 (en) | 2000-09-08 |
| EP1155413B1 (en) | 2006-08-02 |
| US6181608B1 (en) | 2001-01-30 |
| HK1037778A1 (en) | 2002-02-15 |
| EP1155413A1 (en) | 2001-11-21 |
| KR20010102476A (ko) | 2001-11-15 |
| DE60029757T2 (de) | 2007-10-31 |
| KR100479670B1 (ko) | 2005-03-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |