ATE540561T1 - Leiterplatte und herstellungsverfahren dafür - Google Patents

Leiterplatte und herstellungsverfahren dafür

Info

Publication number
ATE540561T1
ATE540561T1 AT09250033T AT09250033T ATE540561T1 AT E540561 T1 ATE540561 T1 AT E540561T1 AT 09250033 T AT09250033 T AT 09250033T AT 09250033 T AT09250033 T AT 09250033T AT E540561 T1 ATE540561 T1 AT E540561T1
Authority
AT
Austria
Prior art keywords
mounting region
circuit board
production process
conductive trace
insulating layer
Prior art date
Application number
AT09250033T
Other languages
English (en)
Inventor
Yasuto Ishimaru
Hirofumi Ebe
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Application granted granted Critical
Publication of ATE540561T1 publication Critical patent/ATE540561T1/de

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0209—External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H10W70/687—Shapes or dispositions thereof comprising multiple insulating layers characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of flexible or folded printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09318—Core having one signal plane and one power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09663—Divided layout, i.e. conductors divided in two or more parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0969—Apertured conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49162—Manufacturing circuit on or in base by using wire as conductive path

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
AT09250033T 2008-01-31 2009-01-07 Leiterplatte und herstellungsverfahren dafür ATE540561T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008021272A JP5184115B2 (ja) 2008-01-31 2008-01-31 配線回路基板およびその製造方法

Publications (1)

Publication Number Publication Date
ATE540561T1 true ATE540561T1 (de) 2012-01-15

Family

ID=40637858

Family Applications (1)

Application Number Title Priority Date Filing Date
AT09250033T ATE540561T1 (de) 2008-01-31 2009-01-07 Leiterplatte und herstellungsverfahren dafür

Country Status (7)

Country Link
US (1) US8097814B2 (de)
EP (1) EP2086297B1 (de)
JP (1) JP5184115B2 (de)
KR (1) KR101486591B1 (de)
CN (1) CN101499452B (de)
AT (1) ATE540561T1 (de)
TW (1) TWI433612B (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5095460B2 (ja) * 2008-01-17 2012-12-12 シャープ株式会社 半導体装置および表示装置
JP4981744B2 (ja) 2008-05-09 2012-07-25 日東電工株式会社 配線回路基板およびその製造方法
JP6094044B2 (ja) 2011-03-23 2017-03-15 大日本印刷株式会社 放熱基板およびそれを用いた素子
JP2016035969A (ja) * 2014-08-01 2016-03-17 味の素株式会社 回路基板及びその製造方法
WO2016149269A1 (en) * 2015-03-19 2016-09-22 Fci Asia Pte. Ltd Comprehensive layout strategy for flip chipping integrated circuits
KR102059478B1 (ko) * 2017-09-15 2019-12-26 스템코 주식회사 회로 기판 및 그 제조 방법
KR102430750B1 (ko) * 2019-08-22 2022-08-08 스템코 주식회사 회로 기판 및 그 제조 방법
KR102876911B1 (ko) 2020-07-13 2025-10-27 삼성전자주식회사 반도체 패키지

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JP2844085B2 (ja) * 1989-07-20 1999-01-06 セイコーインスツルメンツ株式会社 回路基板及び半導体素子の実装方法
JP2808952B2 (ja) 1991-11-27 1998-10-08 日立電線株式会社 半導体素子搭載用基板
US6714625B1 (en) * 1992-04-08 2004-03-30 Elm Technology Corporation Lithography device for semiconductor circuit pattern generation
US5801432A (en) * 1992-06-04 1998-09-01 Lsi Logic Corporation Electronic system using multi-layer tab tape semiconductor device having distinct signal, power and ground planes
JPH0653277A (ja) * 1992-06-04 1994-02-25 Lsi Logic Corp 半導体装置アセンブリおよびその組立方法
US5854085A (en) * 1992-06-04 1998-12-29 Lsi Logic Corporation Multi-layer tab tape having distinct signal, power and ground planes, semiconductor device assembly employing same, apparatus for and method of assembling same
US5717252A (en) * 1994-07-25 1998-02-10 Mitsui High-Tec, Inc. Solder-ball connected semiconductor device with a recessed chip mounting area
KR19980020726A (ko) * 1996-09-11 1998-06-25 김광호 칩 스케일의 볼 그리드 어레이 패키지 및 그의 제조 방법
JP2001102406A (ja) * 1999-09-28 2001-04-13 Toshiba Corp エリアアレイパッケージ及び半導体装置
JP2001209918A (ja) * 1999-11-19 2001-08-03 Nitto Denko Corp 回路付サスペンション基板
JP3734481B2 (ja) * 2003-05-08 2006-01-11 日東電工株式会社 Ｔａｂ用テープキャリアの製造方法
JP2005333028A (ja) * 2004-05-20 2005-12-02 Nitto Denko Corp 配線回路基板
TWI288885B (en) * 2004-06-24 2007-10-21 Checkpoint Systems Inc Die attach area cut-on-fly method and apparatus
JP4014591B2 (ja) 2004-10-05 2007-11-28 シャープ株式会社 半導体装置および電子機器
KR100593935B1 (ko) * 2005-03-24 2006-06-30 삼성전기주식회사 발광 다이오드 패키지 및 그 제조 방법
KR20060126070A (ko) * 2005-06-03 2006-12-07 삼성전자주식회사 구동 집적 회로칩 패키지 및 이를 구비한 표시 장치
JP4619214B2 (ja) * 2005-07-04 2011-01-26 日東電工株式会社 配線回路基板
KR100652519B1 (ko) * 2005-07-18 2006-12-01 삼성전자주식회사 듀얼 금속층을 갖는 테이프 배선기판 및 그를 이용한 칩 온필름 패키지
JP2007035869A (ja) * 2005-07-26 2007-02-08 Nitto Denko Corp Ｔａｂ用テープキャリア
JP2007134658A (ja) 2005-11-14 2007-05-31 Nitto Denko Corp 配線回路基板および配線回路基板を製造し電子部品を実装する方法
JP4762734B2 (ja) * 2006-01-25 2011-08-31 日東電工株式会社 配線回路基板集合体シートおよびその製造方法
JP4919727B2 (ja) * 2006-08-04 2012-04-18 日東電工株式会社 配線回路基板
US7736936B2 (en) * 2006-08-29 2010-06-15 Semiconductor Energy Laboratory Co., Ltd. Method of forming display device that includes removing mask to form opening in insulating film
JP4919738B2 (ja) * 2006-08-31 2012-04-18 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2009094361A (ja) * 2007-10-10 2009-04-30 Nitto Denko Corp Ｃｏｆ基板
JP4981744B2 (ja) * 2008-05-09 2012-07-25 日東電工株式会社 配線回路基板およびその製造方法

Also Published As

Publication number Publication date
CN101499452B (zh) 2012-05-16
CN101499452A (zh) 2009-08-05
KR20090084711A (ko) 2009-08-05
US20090195997A1 (en) 2009-08-06
US8097814B2 (en) 2012-01-17
EP2086297B1 (de) 2012-01-04
EP2086297A2 (de) 2009-08-05
KR101486591B1 (ko) 2015-01-26
EP2086297A3 (de) 2010-05-26
TW200945958A (en) 2009-11-01
JP5184115B2 (ja) 2013-04-17
JP2009182227A (ja) 2009-08-13
TWI433612B (zh) 2014-04-01

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