WO2009037145A3 - Verfahren zur herstellung einer elektronischen baugruppe sowie elektronische baugruppe - Google Patents

Verfahren zur herstellung einer elektronischen baugruppe sowie elektronische baugruppe Download PDF

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Publication number
WO2009037145A3
WO2009037145A3 PCT/EP2008/061897 EP2008061897W WO2009037145A3 WO 2009037145 A3 WO2009037145 A3 WO 2009037145A3 EP 2008061897 W EP2008061897 W EP 2008061897W WO 2009037145 A3 WO2009037145 A3 WO 2009037145A3
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Prior art keywords
electronic assembly
electronic component
production
electronic
conductive foil
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PCT/EP2008/061897
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English (en)
French (fr)
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WO2009037145A2 (de
Inventor
Andreas Kugler
Gerhard Liebing
Dirk Freundt
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Bosch Gmbh Robert
Andreas Kugler
Gerhard Liebing
Dirk Freundt
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Application filed by Bosch Gmbh Robert, Andreas Kugler, Gerhard Liebing, Dirk Freundt filed Critical Bosch Gmbh Robert
Priority to EP08803865A priority Critical patent/EP2193697A2/de
Publication of WO2009037145A2 publication Critical patent/WO2009037145A2/de
Publication of WO2009037145A3 publication Critical patent/WO2009037145A3/de

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
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    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Abstract

Die Erfindung betrifft ein Verfahren zur Herstellung einer elektronischen Baugruppe (21), insbesondere für Hochfrequenzanwendungen, umfassend mindestens ein elektronisches Bauelement (9), das auf einer Leiterplatte (45) befestigt ist, sowie mindestens eine Leiterbahnstruktur (15, 25), mit der das mindestens eine elektronische Bauelement (9) kontaktiert wird. Hierzu wird das mindestens eine elektronische Bauelement (9) auf eine isolierende Schicht (5) einer leitfähigen Folie (1) befestigt. Die leitfähige Folie (1) mit dem mindestens einen daran befestigten elektronischen Bauelement (9) wird auf einen Leiterplattenträger (13) auflaminiert. Durch Strukturieren der leitfähigen Folie (1) und Ankontaktieren des mindestens einen elektronischen Bauelements (9) wird eine Leiterbahnstruktur (15) ausgebildet. An Durchkontaktierungen (33), die in der elektronischen Baugruppe (21) ausgebildet sind und die zur Unterseite der elektronischen Baugruppe (21) führen und mit der Leiterbahnstruktur (15, 25) verbunden sind, werden Lötpunkte (35) angebracht.
PCT/EP2008/061897 2007-09-19 2008-09-09 Verfahren zur herstellung einer elektronischen baugruppe sowie elektronische baugruppe WO2009037145A2 (de)

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