ATE518241T1 - Herstellungsverfahren für wafer aus silizium auf isolator und entsprechender wafer - Google Patents

Herstellungsverfahren für wafer aus silizium auf isolator und entsprechender wafer

Info

Publication number
ATE518241T1
ATE518241T1 AT07290094T AT07290094T ATE518241T1 AT E518241 T1 ATE518241 T1 AT E518241T1 AT 07290094 T AT07290094 T AT 07290094T AT 07290094 T AT07290094 T AT 07290094T AT E518241 T1 ATE518241 T1 AT E518241T1
Authority
AT
Austria
Prior art keywords
donor substrate
silicon
insulator
wafer
initial donor
Prior art date
Application number
AT07290094T
Other languages
German (de)
English (en)
Inventor
Patrick Reynaud
Oleg Kononchuk
Michael Stinco
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE518241T1 publication Critical patent/ATE518241T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10P90/16—
    • H10P14/6309—
    • H10P14/6322—
    • H10P90/1916—
    • H10W10/181—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/8305—Miscellaneous [e.g., treated surfaces, etc.]

Landscapes

  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
AT07290094T 2007-01-24 2007-01-24 Herstellungsverfahren für wafer aus silizium auf isolator und entsprechender wafer ATE518241T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP20070290094 EP1950803B1 (en) 2007-01-24 2007-01-24 Method for manufacturing silicon on Insulator wafers and corresponding wafer

Publications (1)

Publication Number Publication Date
ATE518241T1 true ATE518241T1 (de) 2011-08-15

Family

ID=38157805

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07290094T ATE518241T1 (de) 2007-01-24 2007-01-24 Herstellungsverfahren für wafer aus silizium auf isolator und entsprechender wafer

Country Status (7)

Country Link
US (1) US7736994B2 (enExample)
EP (2) EP1950803B1 (enExample)
JP (1) JP4817342B2 (enExample)
KR (1) KR101302426B1 (enExample)
CN (1) CN101558487B (enExample)
AT (1) ATE518241T1 (enExample)
WO (1) WO2008090439A1 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5438986B2 (ja) * 2008-02-19 2014-03-12 株式会社半導体エネルギー研究所 光電変換装置の製造方法
CN102782869B (zh) 2009-12-09 2013-12-25 速力斯公司 背结背触点三维薄太阳能电池及其制造方法
WO2013055307A2 (en) 2010-08-05 2013-04-18 Solexel, Inc. Backplane reinforcement and interconnects for solar cells
FR2987166B1 (fr) 2012-02-16 2017-05-12 Soitec Silicon On Insulator Procede de transfert d'une couche
EP2817819A4 (en) 2012-02-26 2015-09-02 Solexel Inc SYSTEMS AND METHOD FOR LASER DISTRIBUTION AND DEVICE LAYER TRANSMISSION
FR2999801B1 (fr) 2012-12-14 2014-12-26 Soitec Silicon On Insulator Procede de fabrication d'une structure
US8946054B2 (en) 2013-04-19 2015-02-03 International Business Machines Corporation Crack control for substrate separation
FR3076070B1 (fr) * 2017-12-22 2019-12-27 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de transfert d'une couche utile
FR3076069B1 (fr) * 2017-12-22 2021-11-26 Commissariat Energie Atomique Procede de transfert d'une couche utile
DE102018221582A1 (de) 2018-12-13 2020-06-18 Siltronic Ag Verfahren zur Herstellung einer Halbleiterscheibe und Halbleiterscheibe
US11257902B2 (en) * 2020-05-28 2022-02-22 Taiwan Semiconductor Manufacturing Company Limited SOI device structure for robust isolation

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10114176A (ja) 1996-10-11 1998-05-06 Kunio Kuramochi 図示式野球スコアブック
KR100232886B1 (ko) * 1996-11-23 1999-12-01 김영환 Soi 웨이퍼 제조방법
JP3932369B2 (ja) 1998-04-09 2007-06-20 信越半導体株式会社 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ
JPH11307747A (ja) 1998-04-17 1999-11-05 Nec Corp Ｓｏｉ基板およびその製造方法
JP3500063B2 (ja) 1998-04-23 2004-02-23 信越半導体株式会社 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ
JP3358550B2 (ja) * 1998-07-07 2002-12-24 信越半導体株式会社 Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
JP4476390B2 (ja) 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6544656B1 (en) * 1999-03-16 2003-04-08 Shin-Etsu Handotai Co., Ltd. Production method for silicon wafer and silicon wafer
FR2817394B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
US6448152B1 (en) 2001-02-20 2002-09-10 Silicon Genesis Corporation Method and system for generating a plurality of donor wafers and handle wafers prior to an order being placed by a customer
US6737337B1 (en) * 2001-04-27 2004-05-18 Advanced Micro Devices, Inc. Method of preventing dopant depletion in surface semiconductor layer of semiconductor-on-insulator (SOI) device
US20030029957A1 (en) 2001-08-13 2003-02-13 Smith Ronald D. System and method for manufacturing an ignition coil
JP2003068744A (ja) * 2001-08-30 2003-03-07 Shin Etsu Handotai Co Ltd シリコンウエーハの製造方法及びシリコンウエーハ並びにｓｏｉウエーハ
US7153757B2 (en) 2002-08-29 2006-12-26 Analog Devices, Inc. Method for direct bonding two silicon wafers for minimising interfacial oxide and stresses at the bond interface, and an SOI structure
JP2004247610A (ja) * 2003-02-14 2004-09-02 Canon Inc 基板の製造方法
KR100766393B1 (ko) * 2003-02-14 2007-10-11 주식회사 사무코 규소 웨이퍼의 제조방법
FR2855909B1 (fr) 2003-06-06 2005-08-26 Soitec Silicon On Insulator Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substrat
US7052978B2 (en) 2003-08-28 2006-05-30 Intel Corporation Arrangements incorporating laser-induced cleaving
US7625808B2 (en) * 2003-09-01 2009-12-01 Sumco Corporation Method for manufacturing bonded wafer
DE602004013163T2 (de) 2004-11-19 2009-05-14 S.O.I. Tec Silicon On Insulator Technologies S.A. Verfahren zur Herstellung eines Germanium-On-Insulator-Wafers (GeOI)
FR2881573B1 (fr) 2005-01-31 2008-07-11 Soitec Silicon On Insulator Procede de transfert d'une couche mince formee dans un substrat presentant des amas de lacunes
US20070117350A1 (en) * 2005-08-03 2007-05-24 Memc Electronic Materials, Inc. Strained silicon on insulator (ssoi) with layer transfer from oxidized donor

Also Published As

Publication number Publication date
KR101302426B1 (ko) 2013-09-10
US7736994B2 (en) 2010-06-15
EP1950803B1 (en) 2011-07-27
US20080176380A1 (en) 2008-07-24
EP2264755A3 (en) 2011-11-23
JP2010517286A (ja) 2010-05-20
EP2264755A2 (en) 2010-12-22
WO2008090439A1 (en) 2008-07-31
JP4817342B2 (ja) 2011-11-16
CN101558487B (zh) 2012-05-30
CN101558487A (zh) 2009-10-14
KR20090108689A (ko) 2009-10-16
EP1950803A1 (en) 2008-07-30

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