CN101558487B - 制造复合材料晶片的方法 - Google Patents

制造复合材料晶片的方法 Download PDF

Info

Publication number
CN101558487B
CN101558487B CN2008800011140A CN200880001114A CN101558487B CN 101558487 B CN101558487 B CN 101558487B CN 2008800011140 A CN2008800011140 A CN 2008800011140A CN 200880001114 A CN200880001114 A CN 200880001114A CN 101558487 B CN101558487 B CN 101558487B
Authority
CN
China
Prior art keywords
donor substrate
silicon
manufacturing
layer
wafer according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2008800011140A
Other languages
English (en)
Chinese (zh)
Other versions
CN101558487A (zh
Inventor
帕特里克·雷诺
奥列格·科农丘克
米夏埃尔·司廷科
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of CN101558487A publication Critical patent/CN101558487A/zh
Application granted granted Critical
Publication of CN101558487B publication Critical patent/CN101558487B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/8305—Miscellaneous [e.g., treated surfaces, etc.]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
CN2008800011140A 2007-01-24 2008-01-16 制造复合材料晶片的方法 Active CN101558487B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP07290094.7 2007-01-24
EP20070290094 EP1950803B1 (en) 2007-01-24 2007-01-24 Method for manufacturing silicon on Insulator wafers and corresponding wafer
PCT/IB2008/000131 WO2008090439A1 (en) 2007-01-24 2008-01-16 Method for manufacturing compound material wafers and corresponding compound material wafer

Publications (2)

Publication Number Publication Date
CN101558487A CN101558487A (zh) 2009-10-14
CN101558487B true CN101558487B (zh) 2012-05-30

Family

ID=38157805

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008800011140A Active CN101558487B (zh) 2007-01-24 2008-01-16 制造复合材料晶片的方法

Country Status (7)

Country Link
US (1) US7736994B2 (enExample)
EP (2) EP2264755A3 (enExample)
JP (1) JP4817342B2 (enExample)
KR (1) KR101302426B1 (enExample)
CN (1) CN101558487B (enExample)
AT (1) ATE518241T1 (enExample)
WO (1) WO2008090439A1 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8017429B2 (en) * 2008-02-19 2011-09-13 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing photoelectric conversion device
EP2510552A4 (en) 2009-12-09 2014-11-05 Solexel Inc HIGHLY EFFICIENT PHOTOVOLTAIC BACK CONTACT STRUCTURES FOR SOLAR CELLS AND METHOD OF MANUFACTURING THEM BY USING SEMICONDUCTOR WAFERS
KR20140015247A (ko) 2010-08-05 2014-02-06 솔렉셀, 인크. 태양전지용 백플레인 보강 및 상호연결부
FR2987166B1 (fr) 2012-02-16 2017-05-12 Soitec Silicon On Insulator Procede de transfert d'une couche
EP2817819A4 (en) 2012-02-26 2015-09-02 Solexel Inc SYSTEMS AND METHOD FOR LASER DISTRIBUTION AND DEVICE LAYER TRANSMISSION
FR2999801B1 (fr) 2012-12-14 2014-12-26 Soitec Silicon On Insulator Procede de fabrication d'une structure
US8946054B2 (en) 2013-04-19 2015-02-03 International Business Machines Corporation Crack control for substrate separation
FR3076069B1 (fr) * 2017-12-22 2021-11-26 Commissariat Energie Atomique Procede de transfert d'une couche utile
FR3076070B1 (fr) * 2017-12-22 2019-12-27 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de transfert d'une couche utile
DE102018221582A1 (de) 2018-12-13 2020-06-18 Siltronic Ag Verfahren zur Herstellung einer Halbleiterscheibe und Halbleiterscheibe
US11257902B2 (en) * 2020-05-28 2022-02-22 Taiwan Semiconductor Manufacturing Company Limited SOI device structure for robust isolation

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5953622A (en) * 1996-11-23 1999-09-14 Hyundai Electronics Industries Co., Ltd. Method for fabricating semiconductor wafers
CN1692482A (zh) * 2003-02-14 2005-11-02 三菱住友硅晶株式会社 硅片的制造方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10114176A (ja) 1996-10-11 1998-05-06 Kunio Kuramochi 図示式野球スコアブック
JP3932369B2 (ja) 1998-04-09 2007-06-20 信越半導体株式会社 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ
JPH11307747A (ja) 1998-04-17 1999-11-05 Nec Corp Ｓｏｉ基板およびその製造方法
JP3500063B2 (ja) 1998-04-23 2004-02-23 信越半導体株式会社 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ
JP3358550B2 (ja) * 1998-07-07 2002-12-24 信越半導体株式会社 Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
JP4476390B2 (ja) 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
EP2037009B1 (en) * 1999-03-16 2013-07-31 Shin-Etsu Handotai Co., Ltd. Method for producing a bonded SOI wafer
FR2817394B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
US6448152B1 (en) 2001-02-20 2002-09-10 Silicon Genesis Corporation Method and system for generating a plurality of donor wafers and handle wafers prior to an order being placed by a customer
US6737337B1 (en) * 2001-04-27 2004-05-18 Advanced Micro Devices, Inc. Method of preventing dopant depletion in surface semiconductor layer of semiconductor-on-insulator (SOI) device
US20030029957A1 (en) 2001-08-13 2003-02-13 Smith Ronald D. System and method for manufacturing an ignition coil
JP2003068744A (ja) * 2001-08-30 2003-03-07 Shin Etsu Handotai Co Ltd シリコンウエーハの製造方法及びシリコンウエーハ並びにｓｏｉウエーハ
US7153757B2 (en) 2002-08-29 2006-12-26 Analog Devices, Inc. Method for direct bonding two silicon wafers for minimising interfacial oxide and stresses at the bond interface, and an SOI structure
JP2004247610A (ja) * 2003-02-14 2004-09-02 Canon Inc 基板の製造方法
FR2855909B1 (fr) 2003-06-06 2005-08-26 Soitec Silicon On Insulator Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substrat
US7052978B2 (en) 2003-08-28 2006-05-30 Intel Corporation Arrangements incorporating laser-induced cleaving
EP1662549B1 (en) * 2003-09-01 2015-07-29 SUMCO Corporation Method for manufacturing bonded wafer
EP1659623B1 (en) * 2004-11-19 2008-04-16 S.O.I. Tec Silicon on Insulator Technologies S.A. Method for fabricating a germanium on insulator (GeOI) type wafer
FR2881573B1 (fr) 2005-01-31 2008-07-11 Soitec Silicon On Insulator Procede de transfert d'une couche mince formee dans un substrat presentant des amas de lacunes
US20070117350A1 (en) * 2005-08-03 2007-05-24 Memc Electronic Materials, Inc. Strained silicon on insulator (ssoi) with layer transfer from oxidized donor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5953622A (en) * 1996-11-23 1999-09-14 Hyundai Electronics Industries Co., Ltd. Method for fabricating semiconductor wafers
CN1692482A (zh) * 2003-02-14 2005-11-02 三菱住友硅晶株式会社 硅片的制造方法

Also Published As

Publication number Publication date
EP2264755A3 (en) 2011-11-23
EP1950803B1 (en) 2011-07-27
CN101558487A (zh) 2009-10-14
JP4817342B2 (ja) 2011-11-16
JP2010517286A (ja) 2010-05-20
KR20090108689A (ko) 2009-10-16
KR101302426B1 (ko) 2013-09-10
EP2264755A2 (en) 2010-12-22
EP1950803A1 (en) 2008-07-30
US20080176380A1 (en) 2008-07-24
US7736994B2 (en) 2010-06-15
WO2008090439A1 (en) 2008-07-31
ATE518241T1 (de) 2011-08-15

Similar Documents

Publication Publication Date Title
CN101558487B (zh) 制造复合材料晶片的方法
US6593173B1 (en) Low defect density, thin-layer, SOI substrates
US6946317B2 (en) Method of fabricating heteroepitaxial microstructures
KR100886620B1 (ko) 복합물 웨이퍼 제조방법 및 사용한 도우너 기판의리싸이클링 방법
US8361888B2 (en) Method for manufacturing SOI wafer
US6375738B1 (en) Process of producing semiconductor article
JPH05102445A (ja) 半導体基材の作製方法
KR20130029110A (ko) 절연체 기판상의 실리콘 마감을 위한 방법
WO2018006883A1 (zh) 利用薄膜转移技术制备薄膜体声波器件的方法
KR20090101119A (ko) Ｓｏｉ 웨이퍼의 제조 방법
US8216917B2 (en) Method for fabricating a semiconductor on insulator type substrate
JP7408893B2 (ja) ダイヤモンド又はイリジウム材料の単結晶層を製造するための方法、及びダイヤモンド又はイリジウム材料の単結晶層をエピタキシャル成長させるための基板
CN100433259C (zh) 半导体基材及其制造方法
JP6827442B2 (ja) 貼り合わせｓｏｉウェーハの製造方法及び貼り合わせｓｏｉウェーハ
JP2010525598A (ja) 複合材料ウェハの製造方法および対応する複合材料ウェハ
KR20160013037A (ko) 접합 웨이퍼의 제조방법
JP7355289B2 (ja) Ｌｎｏ材料の単結晶層を生成するための方法、及びｌｎｏ材料の単結晶層をエピタキシャル成長させるための基板
US11976380B2 (en) Method for manufacturing a monocrystalline layer of GaAs material and substrate for epitaxial growth of a monocrystalline layer of GaAs material
KR100704146B1 (ko) Ｓｏｉ 기판의 제조방법
KR100609367B1 (ko) Ｓｏｉ 기판의 제조방법
US20230215760A1 (en) Method for manufacturing a semiconductor-on-insulator substrate for radiofrequency applications
TW202036657A (zh) 一種在基板上製作薄膜方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C56 Change in the name or address of the patentee

Owner name: SAWTEK INC.

Free format text: FORMER NAME: SOITEC SILICON ON INSULATOR

CP03 Change of name, title or address

Address after: French Boerning

Patentee after: Soitec Silicon On Insulator

Address before: French Berneni

Patentee before: Silicon on Insulator Technologies S. A.