ATE484847T1 - Verfahren zur herstellung einer dünnen schicht, einschliesslich eines schrittes des korrigierens der dicke durch hilfsoxidation und zugehörige vorrichtung - Google Patents

Verfahren zur herstellung einer dünnen schicht, einschliesslich eines schrittes des korrigierens der dicke durch hilfsoxidation und zugehörige vorrichtung

Info

Publication number
ATE484847T1
ATE484847T1 AT03784416T AT03784416T ATE484847T1 AT E484847 T1 ATE484847 T1 AT E484847T1 AT 03784416 T AT03784416 T AT 03784416T AT 03784416 T AT03784416 T AT 03784416T AT E484847 T1 ATE484847 T1 AT E484847T1
Authority
AT
Austria
Prior art keywords
thickness
layer
correcting
thin layer
producing
Prior art date
Application number
AT03784416T
Other languages
English (en)
Inventor
Bruno Ghyselen
Cecile Aulnette
Benedite Osternaud
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0210208A external-priority patent/FR2843486B1/fr
Priority claimed from FR0210209A external-priority patent/FR2843487B1/fr
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE484847T1 publication Critical patent/ATE484847T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Length Measuring Devices By Optical Means (AREA)
  • Formation Of Insulating Films (AREA)
  • Length Measuring Devices With Unspecified Measuring Means (AREA)
  • Physical Vapour Deposition (AREA)
AT03784416T 2002-08-12 2003-08-11 Verfahren zur herstellung einer dünnen schicht, einschliesslich eines schrittes des korrigierens der dicke durch hilfsoxidation und zugehörige vorrichtung ATE484847T1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR0210208A FR2843486B1 (fr) 2002-08-12 2002-08-12 Procede d'elaboration de couches minces de semi-conducteur comprenant une etape de finition
FR0210209A FR2843487B1 (fr) 2002-08-12 2002-08-12 Procede d'elaboration de couche mince comprenant une etape de correction d'epaisseur par oxydation sacrificielle, et machine associee
US46724103P 2003-04-30 2003-04-30
PCT/IB2003/003640 WO2004015759A2 (en) 2002-08-12 2003-08-11 A method of preparing a thin layer, the method including a step of correcting thickness by sacrificial oxidation, and an associated machine

Publications (1)

Publication Number Publication Date
ATE484847T1 true ATE484847T1 (de) 2010-10-15

Family

ID=31721058

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03784416T ATE484847T1 (de) 2002-08-12 2003-08-11 Verfahren zur herstellung einer dünnen schicht, einschliesslich eines schrittes des korrigierens der dicke durch hilfsoxidation und zugehörige vorrichtung

Country Status (7)

Country Link
EP (2) EP2190010A2 (de)
JP (1) JP4684650B2 (de)
AT (1) ATE484847T1 (de)
AU (1) AU2003263391A1 (de)
DE (1) DE60334555D1 (de)
TW (1) TWI298919B (de)
WO (1) WO2004015759A2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2991099B1 (fr) 2012-05-25 2014-05-23 Soitec Silicon On Insulator Procede de traitement d'une structure semi-conducteur sur isolant en vue d'uniformiser l'epaisseur de la couche semi-conductrice
JP6747386B2 (ja) * 2017-06-23 2020-08-26 信越半導体株式会社 Ｓｏｉウェーハの製造方法
US20220205105A1 (en) * 2019-02-15 2022-06-30 Lam Research Corporation Trim and deposition profile control with multi-zone heated substrate support for multi-patterning processes
FR3099291A1 (fr) 2019-07-23 2021-01-29 Soitec procédé de préparation d’une couche mince, incluant une séquence d’étapes pour ameliorer l’uniformité d’epaisseur de ladite couche mince
FR3104810B1 (fr) 2019-12-17 2023-03-31 Soitec Silicon On Insulator Procede de gravure de substrats comportant une couche mince superficielle, pour ameliorer l’uniformite d’epaisseur de ladite couche
CN114894132A (zh) * 2022-05-08 2022-08-12 三河建华高科有限责任公司 一种半导体晶圆厚度检测控制系统

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3154100B2 (ja) * 1991-08-02 2001-04-09 キヤノン株式会社 液晶画像表示装置の製造方法
JP3272815B2 (ja) * 1993-05-20 2002-04-08 株式会社東芝 レジスト感度調整装置および方法
JP3612836B2 (ja) * 1996-01-26 2005-01-19 三菱化学株式会社 薄膜製造方法
JP3660469B2 (ja) * 1996-07-05 2005-06-15 日本電信電話株式会社 Ｓｏｉ基板の製造方法
TW346649B (en) * 1996-09-24 1998-12-01 Tokyo Electron Co Ltd Method for wet etching a film
JP2002118242A (ja) * 1996-11-15 2002-04-19 Canon Inc 半導体部材の製造方法
US6111634A (en) * 1997-05-28 2000-08-29 Lam Research Corporation Method and apparatus for in-situ monitoring of thickness using a multi-wavelength spectrometer during chemical-mechanical polishing
FR2777115B1 (fr) 1998-04-07 2001-07-13 Commissariat Energie Atomique Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
TW455973B (en) * 1999-04-05 2001-09-21 Applied Materials Inc Endpoint detection in the fabrication of electronic devices
FR2797714B1 (fr) * 1999-08-20 2001-10-26 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
FR2797713B1 (fr) 1999-08-20 2002-08-02 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
JP2001118832A (ja) * 1999-10-21 2001-04-27 Toshiba Corp エッチング溝深さ、膜厚および段差の測定方法、およびその装置
JP2003532349A (ja) 2000-05-02 2003-10-28 エピオン コーポレイション Ｇｃｉｂ処理によるデバイス特性の調整システム及び方法
US6829559B2 (en) * 2000-09-20 2004-12-07 K.L.A.-Tencor Technologies Methods and systems for determining a presence of macro and micro defects on a specimen
JP2002134466A (ja) * 2000-10-25 2002-05-10 Sony Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
WO2004015759A2 (en) 2004-02-19
JP4684650B2 (ja) 2011-05-18
WO2004015759A3 (en) 2004-06-03
EP2190010A2 (de) 2010-05-26
TWI298919B (en) 2008-07-11
TW200414392A (en) 2004-08-01
DE60334555D1 (de) 2010-11-25
AU2003263391A1 (en) 2004-02-25
EP1547143A2 (de) 2005-06-29
JP2005536043A (ja) 2005-11-24
EP1547143B1 (de) 2010-10-13

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