DE60334555D1 - Verfahren zur herstellung einer dünnen schicht, einschliesslich eines schrittes des korrigierens der dicke durch hilfsoxidation und zugehörige vorrichtung - Google Patents

Verfahren zur herstellung einer dünnen schicht, einschliesslich eines schrittes des korrigierens der dicke durch hilfsoxidation und zugehörige vorrichtung

Info

Publication number
DE60334555D1
DE60334555D1 DE60334555T DE60334555T DE60334555D1 DE 60334555 D1 DE60334555 D1 DE 60334555D1 DE 60334555 T DE60334555 T DE 60334555T DE 60334555 T DE60334555 T DE 60334555T DE 60334555 D1 DE60334555 D1 DE 60334555D1
Authority
DE
Germany
Prior art keywords
thickness
layer
correcting
thin layer
producing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60334555T
Other languages
English (en)
Inventor
Bruno Ghyselen
Cecile Aulnette
Benedite Osternaud
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0210209A external-priority patent/FR2843487B1/fr
Priority claimed from FR0210208A external-priority patent/FR2843486B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Application granted granted Critical
Publication of DE60334555D1 publication Critical patent/DE60334555D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
DE60334555T 2002-08-12 2003-08-11 Verfahren zur herstellung einer dünnen schicht, einschliesslich eines schrittes des korrigierens der dicke durch hilfsoxidation und zugehörige vorrichtung Expired - Lifetime DE60334555D1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR0210209A FR2843487B1 (fr) 2002-08-12 2002-08-12 Procede d'elaboration de couche mince comprenant une etape de correction d'epaisseur par oxydation sacrificielle, et machine associee
FR0210208A FR2843486B1 (fr) 2002-08-12 2002-08-12 Procede d'elaboration de couches minces de semi-conducteur comprenant une etape de finition
US46724103P 2003-04-30 2003-04-30
PCT/IB2003/003640 WO2004015759A2 (en) 2002-08-12 2003-08-11 A method of preparing a thin layer, the method including a step of correcting thickness by sacrificial oxidation, and an associated machine

Publications (1)

Publication Number Publication Date
DE60334555D1 true DE60334555D1 (de) 2010-11-25

Family

ID=31721058

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60334555T Expired - Lifetime DE60334555D1 (de) 2002-08-12 2003-08-11 Verfahren zur herstellung einer dünnen schicht, einschliesslich eines schrittes des korrigierens der dicke durch hilfsoxidation und zugehörige vorrichtung

Country Status (7)

Country Link
EP (2) EP2190010A2 (de)
JP (1) JP4684650B2 (de)
AT (1) ATE484847T1 (de)
AU (1) AU2003263391A1 (de)
DE (1) DE60334555D1 (de)
TW (1) TWI298919B (de)
WO (1) WO2004015759A2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2991099B1 (fr) 2012-05-25 2014-05-23 Soitec Silicon On Insulator Procede de traitement d'une structure semi-conducteur sur isolant en vue d'uniformiser l'epaisseur de la couche semi-conductrice
JP6747386B2 (ja) * 2017-06-23 2020-08-26 信越半導体株式会社 Ｓｏｉウェーハの製造方法
CN113678237A (zh) * 2019-02-15 2021-11-19 朗姆研究公司 针对多重图案化工艺使用多区加热衬底支撑件的修整与沉积轮廓控制
FR3099291A1 (fr) 2019-07-23 2021-01-29 Soitec procédé de préparation d’une couche mince, incluant une séquence d’étapes pour ameliorer l’uniformité d’epaisseur de ladite couche mince
FR3104810B1 (fr) 2019-12-17 2023-03-31 Soitec Silicon On Insulator Procede de gravure de substrats comportant une couche mince superficielle, pour ameliorer l’uniformite d’epaisseur de ladite couche
CN114894132A (zh) * 2022-05-08 2022-08-12 三河建华高科有限责任公司 一种半导体晶圆厚度检测控制系统

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3154100B2 (ja) * 1991-08-02 2001-04-09 キヤノン株式会社 液晶画像表示装置の製造方法
JP3272815B2 (ja) * 1993-05-20 2002-04-08 株式会社東芝 レジスト感度調整装置および方法
JP3612836B2 (ja) * 1996-01-26 2005-01-19 三菱化学株式会社 薄膜製造方法
JP3660469B2 (ja) * 1996-07-05 2005-06-15 日本電信電話株式会社 Ｓｏｉ基板の製造方法
TW346649B (en) * 1996-09-24 1998-12-01 Tokyo Electron Co Ltd Method for wet etching a film
JP2002118242A (ja) * 1996-11-15 2002-04-19 Canon Inc 半導体部材の製造方法
US6111634A (en) * 1997-05-28 2000-08-29 Lam Research Corporation Method and apparatus for in-situ monitoring of thickness using a multi-wavelength spectrometer during chemical-mechanical polishing
FR2777115B1 (fr) 1998-04-07 2001-07-13 Commissariat Energie Atomique Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
TW455973B (en) * 1999-04-05 2001-09-21 Applied Materials Inc Endpoint detection in the fabrication of electronic devices
FR2797714B1 (fr) * 1999-08-20 2001-10-26 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
FR2797713B1 (fr) 1999-08-20 2002-08-02 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
JP2001118832A (ja) * 1999-10-21 2001-04-27 Toshiba Corp エッチング溝深さ、膜厚および段差の測定方法、およびその装置
US6750460B2 (en) 2000-05-02 2004-06-15 Epion Corporation System and method for adjusting the properties of a device by GCIB processing
US7196782B2 (en) 2000-09-20 2007-03-27 Kla-Tencor Technologies Corp. Methods and systems for determining a thin film characteristic and an electrical property of a specimen
JP2002134466A (ja) * 2000-10-25 2002-05-10 Sony Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
AU2003263391A1 (en) 2004-02-25
EP1547143B1 (de) 2010-10-13
EP2190010A2 (de) 2010-05-26
EP1547143A2 (de) 2005-06-29
TWI298919B (en) 2008-07-11
WO2004015759A2 (en) 2004-02-19
JP4684650B2 (ja) 2011-05-18
ATE484847T1 (de) 2010-10-15
TW200414392A (en) 2004-08-01
WO2004015759A3 (en) 2004-06-03
JP2005536043A (ja) 2005-11-24

Similar Documents

Publication Publication Date Title
DE60333559D1 (de) Substrat zum züchten von galliumnitrid, verfahren zur herstellung des substrats zum züchten von galliumnitrid und verfahren zur herstellung eines galliumnitridsubstrats
DE69902860D1 (de) Verfahren zur Herstellung eines integrierten Halbleiterbauelements
ATE383656T1 (de) Verfahren zur herstellung eines verbundmaterials und verfahren zur auswahl eines wafers
ATE345749T1 (de) Verfahren und vorrichtung zur herstellung eines intravaskulären stents
DE69912376D1 (de) Verfahren zur herstellung eines halbleiterbauelements
DE60038423D1 (de) Verfahren zur Herstellung eines Halbleiterbauelements
DE60009771D1 (de) Verfahren zur Oberflächenbehandlung, Verfahren zur Herstellung eines Tintenstrahl-Aufzeichnungsmaterials sowie durch dieses Verfahren hergestelltes Material
DE60327721D1 (de) Verfahren zur Herstellung eines Halbleiterbauelements
DE60022857D1 (de) Verfahren zur Herstellung eines Halbleiterbauelements
ATE418956T1 (de) Verfahren und vorrichtung zur herstellung eines mehrkernigen geformten artikels
ATE480650T1 (de) Tiegel zur behandlung von schmelzflüssigem silicium und verfahren zu seiner herstellung
DE602006011362D1 (de) Verfahren zur herstellung eines (110) silizium-wafers
DE60204502D1 (de) Polysiloxanharz und Verfahren zur Herstellung einer Zwischenschicht daraus für Wafer
DE602004026875D1 (de) Härtbare selbstklebefolie zum zertrennen bzw. chip-bonden und verfahren zur herstellung eines halbleiterbauelements
DE69923567D1 (de) Verfahren zur herstellung eines siliciumcarbidsinterkörpers
ATE396180T1 (de) Verfahren zur herstellung von 2,6-diamino-4,5,6,7-tetrahydrobenzothiazol
TW200505617A (en) Method and apparatus for removing an edge region of a layer applied to a substrate and for coating a substrate and a substrate
DE69900481T2 (de) Verfahren zur Herstellung eines einkristallinen Siliciumwafers und durch das Verfahren hergestellte einkristalline Siliciumwafer
DE59900247D1 (de) Verfahren zum Rauhätzen einer Halbleiter-Oberfläche
DE69922617D1 (de) Verfahren zur Herstellung eines Halbleiterbauelementes
DE60334555D1 (de) Verfahren zur herstellung einer dünnen schicht, einschliesslich eines schrittes des korrigierens der dicke durch hilfsoxidation und zugehörige vorrichtung
DE10292173D2 (de) Verfahren und Vorrichtung zur Herstellung von Furnieren und von furnierten Teilen sowie Furniere und furnierte Teile
DE60227022D1 (de) Verfahren zur Herstellung einer Elektrode für Siliziumkarbidhalbleiter
DE60230982D1 (de) Verfahren zur herstellung eines halbleiterbauelements
DE60209835D1 (de) Verfahren zur Herstellung eines Halbleiterbauelements

Legal Events

Date Code Title Description
R082 Change of representative

Ref document number: 1547143

Country of ref document: EP

Representative=s name: SAMSON & PARTNER, PATENTANWAELTE, DE

R081 Change of applicant/patentee

Ref document number: 1547143

Country of ref document: EP

Owner name: SOITEC, FR

Free format text: FORMER OWNER: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, BERNIN, FR

Effective date: 20120905

R082 Change of representative

Ref document number: 1547143

Country of ref document: EP

Representative=s name: SAMSON & PARTNER, PATENTANWAELTE, DE

Effective date: 20120905