ATE370448T1 - Fifo schaltungen mit niedriger verzögerung für gemischte synchrone und asynchrone systeme - Google Patents
Fifo schaltungen mit niedriger verzögerung für gemischte synchrone und asynchrone systemeInfo
- Publication number
- ATE370448T1 ATE370448T1 AT01944392T AT01944392T ATE370448T1 AT E370448 T1 ATE370448 T1 AT E370448T1 AT 01944392 T AT01944392 T AT 01944392T AT 01944392 T AT01944392 T AT 01944392T AT E370448 T1 ATE370448 T1 AT E370448T1
- Authority
- AT
- Austria
- Prior art keywords
- sender
- receiver
- subsystem
- time domain
- circuit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
- G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
- G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Communication Control (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Information Transfer Systems (AREA)
- Time-Division Multiplex Systems (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US21064200P | 2000-06-09 | 2000-06-09 |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE370448T1 true ATE370448T1 (de) | 2007-09-15 |
Family
ID=22783678
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT01944392T ATE370448T1 (de) | 2000-06-09 | 2001-06-08 | Fifo schaltungen mit niedriger verzögerung für gemischte synchrone und asynchrone systeme |
Country Status (9)
Country | Link |
---|---|
EP (1) | EP1374032B1 (de) |
JP (2) | JP4849763B2 (de) |
KR (1) | KR100761430B1 (de) |
CN (1) | CN100429616C (de) |
AT (1) | ATE370448T1 (de) |
AU (1) | AU2001266808A1 (de) |
CA (1) | CA2412438A1 (de) |
DE (1) | DE60130039T2 (de) |
WO (1) | WO2001095089A2 (de) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100729319B1 (ko) | 2000-04-25 | 2007-06-15 | 더 트러스티스 오브 컬럼비아 유니버시티 인 더 시티 오브 뉴욕 | 고용량 비동기 파이프라인 처리를 위한 회로 및 방법 |
AU2001257403A1 (en) | 2000-04-26 | 2001-11-07 | The Trustees Of Columbia University In The City Of New York | A low latency fifo circuit for mixed clock systems |
AU2001292980A1 (en) | 2000-10-23 | 2002-05-06 | The Trustees Of Columbia University In The City Of New York | Asynchronous pipeline with latch controllers |
KR20020094129A (ko) * | 2001-06-11 | 2002-12-18 | 이문기 | 데이터 전송을 위한 토큰링 방식의 데이터 전송 시스템 |
WO2004066142A2 (en) | 2003-01-24 | 2004-08-05 | Koninklijke Philips Electronics N.V. | Pipeline synchronisation device and method |
CN100463443C (zh) * | 2005-07-01 | 2009-02-18 | 中兴通讯股份有限公司 | 一种异步fifo实现系统及实现方法 |
FR2890766B1 (fr) * | 2005-09-12 | 2007-11-30 | Arteris Sa | Systeme et procede de communication asynchrone sur circuit, entre des sous-circuits synchrones |
FR2899413B1 (fr) | 2006-03-31 | 2008-08-08 | Arteris Sa | Systeme de commutation de message |
FR2900017B1 (fr) | 2006-04-12 | 2008-10-31 | Arteris Sa | Systeme d'interconnexions de blocs fonctionnels externes sur puce muni d'un unique protocole parametrable de communication |
FR2902957B1 (fr) | 2006-06-23 | 2008-09-12 | Arteris Sa | Systeme et procede de gestions de messages transmis dans un reseau d'interconnexions |
US7913007B2 (en) | 2007-09-27 | 2011-03-22 | The University Of North Carolina | Systems, methods, and computer readable media for preemption in asynchronous systems using anti-tokens |
WO2010039312A2 (en) | 2008-06-27 | 2010-04-08 | The University Of North Carolina At Chapel Hill | Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits |
CN102053815B (zh) * | 2009-11-05 | 2012-10-31 | 上海华虹集成电路有限责任公司 | 同步fifo电路系统 |
CA2782414C (en) | 2009-12-14 | 2021-08-03 | Ab Initio Technology Llc | Specifying user interface elements |
CN101739500B (zh) * | 2010-02-10 | 2012-06-06 | 龙芯中科技术有限公司 | 一种多时钟数字系统及其时钟确定装置和方法 |
WO2015192062A1 (en) | 2014-06-12 | 2015-12-17 | The University Of North Carolina At Chapel Hill | Camera sensor with event token based image capture and reconstruction |
CN104298634B (zh) * | 2014-09-24 | 2017-06-30 | 四川九洲电器集团有限责任公司 | 基于fpga和dsp的数据传输系统 |
US9703526B2 (en) * | 2015-03-12 | 2017-07-11 | Altera Corporation | Self-stuffing multi-clock FIFO requiring no synchronizers |
US11423083B2 (en) | 2017-10-27 | 2022-08-23 | Ab Initio Technology Llc | Transforming a specification into a persistent computer program |
CN108268238A (zh) * | 2018-01-24 | 2018-07-10 | 深圳市风云实业有限公司 | 数据处理方法、装置、计算机存储介质及fifo设备 |
CN111274171B (zh) * | 2018-12-04 | 2022-02-11 | 珠海格力电器股份有限公司 | 一种数据传输装置及方法 |
CN110825344A (zh) * | 2019-11-12 | 2020-02-21 | 天津飞腾信息技术有限公司 | 一种异步数据传输方法和结构 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55127637A (en) * | 1979-03-24 | 1980-10-02 | Nec Corp | Data transfer buffer circuit |
JPS587932A (ja) * | 1981-07-08 | 1983-01-17 | Kyosan Electric Mfg Co Ltd | カウンタ回路 |
JPS63167949A (ja) * | 1986-12-30 | 1988-07-12 | Fanuc Ltd | デ−タ転送システム |
JP2577926B2 (ja) * | 1987-02-20 | 1997-02-05 | 日本テキサス・インスツルメンツ株式会社 | 画像データの書き込み及び読み出し方法 |
JPH0277936A (ja) * | 1988-09-14 | 1990-03-19 | Meidensha Corp | Fifoバッファメモリの制御方式 |
JPH03141092A (ja) * | 1989-10-25 | 1991-06-17 | Hitachi Ltd | 半導体メモリ |
JP2597040B2 (ja) * | 1990-09-12 | 1997-04-02 | シャープ株式会社 | Fifoメモリ装置 |
JP2703668B2 (ja) * | 1991-03-18 | 1998-01-26 | 株式会社日立製作所 | データ転送制御装置および磁気ディスク制御装置 |
JPH05197520A (ja) * | 1992-01-22 | 1993-08-06 | Japan Radio Co Ltd | Fifoメモリ |
JPH065220U (ja) * | 1992-06-17 | 1994-01-21 | 横河電機株式会社 | 遅延回路 |
CA2106271C (en) * | 1993-01-11 | 2004-11-30 | Joseph H. Steinmetz | Single and multistage stage fifo designs for data transfer synchronizers |
JPH0798979A (ja) * | 1993-09-29 | 1995-04-11 | Toshiba Corp | 半導体記憶装置 |
JPH0877125A (ja) * | 1994-09-09 | 1996-03-22 | Hitachi Ltd | 非同期データの同期化転送方式 |
JP3712471B2 (ja) * | 1995-07-07 | 2005-11-02 | サン・マイクロシステムズ・インコーポレイテッド | コンピュータシステム及び第1の回路と第2の回路との間でデータを転送するインタフェース回路 |
JPH09180434A (ja) * | 1995-12-27 | 1997-07-11 | Canon Inc | データ処理装置 |
JPH10315548A (ja) * | 1997-05-21 | 1998-12-02 | Canon Inc | データ処理装置および方法ならびに、印刷装置 |
JPH11175310A (ja) * | 1997-12-09 | 1999-07-02 | Toshiba Tec Corp | FiFoメモリ制御回路 |
US6208703B1 (en) * | 1998-05-15 | 2001-03-27 | Hewlett Packard Company | First-in-first-out synchronizer |
US6128678A (en) * | 1998-08-28 | 2000-10-03 | Theseus Logic, Inc. | FIFO using asynchronous logic to interface between clocked logic circuits |
-
2001
- 2001-06-08 AT AT01944392T patent/ATE370448T1/de not_active IP Right Cessation
- 2001-06-08 DE DE60130039T patent/DE60130039T2/de not_active Expired - Lifetime
- 2001-06-08 EP EP01944392A patent/EP1374032B1/de not_active Expired - Lifetime
- 2001-06-08 AU AU2001266808A patent/AU2001266808A1/en not_active Abandoned
- 2001-06-08 CN CNB018138195A patent/CN100429616C/zh not_active Expired - Fee Related
- 2001-06-08 WO PCT/US2001/018667 patent/WO2001095089A2/en active IP Right Grant
- 2001-06-08 JP JP2002502575A patent/JP4849763B2/ja not_active Expired - Fee Related
- 2001-06-08 KR KR1020027016784A patent/KR100761430B1/ko not_active IP Right Cessation
- 2001-06-08 CA CA002412438A patent/CA2412438A1/en not_active Abandoned
-
2011
- 2011-06-24 JP JP2011141050A patent/JP5379826B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE60130039T2 (de) | 2008-05-15 |
KR100761430B1 (ko) | 2007-09-27 |
CN1478226A (zh) | 2004-02-25 |
KR20030066333A (ko) | 2003-08-09 |
EP1374032B1 (de) | 2007-08-15 |
AU2001266808A1 (en) | 2001-12-17 |
CA2412438A1 (en) | 2001-12-13 |
CN100429616C (zh) | 2008-10-29 |
JP4849763B2 (ja) | 2012-01-11 |
WO2001095089A3 (en) | 2003-10-16 |
WO2001095089A2 (en) | 2001-12-13 |
EP1374032A2 (de) | 2004-01-02 |
JP5379826B2 (ja) | 2013-12-25 |
DE60130039D1 (de) | 2007-09-27 |
JP2011227919A (ja) | 2011-11-10 |
JP2004510216A (ja) | 2004-04-02 |
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Legal Events
Date | Code | Title | Description |
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RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |