JPS55127637A - Data transfer buffer circuit - Google Patents

Data transfer buffer circuit

Info

Publication number
JPS55127637A
JPS55127637A JP3496879A JP3496879A JPS55127637A JP S55127637 A JPS55127637 A JP S55127637A JP 3496879 A JP3496879 A JP 3496879A JP 3496879 A JP3496879 A JP 3496879A JP S55127637 A JPS55127637 A JP S55127637A
Authority
JP
Japan
Prior art keywords
memory
capacity
signal generating
generating circuit
transfer buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3496879A
Other languages
Japanese (ja)
Inventor
Hiroshi Funashige
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3496879A priority Critical patent/JPS55127637A/en
Publication of JPS55127637A publication Critical patent/JPS55127637A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To improve transfer efficiency by letting an input inhibition signal generating circuit and read inhibition signal generating circuit supervise the storage capacity of a transfer buffer memory composed of the first-in first-out buffer memory (FIFO) of n-word capacity.
CONSTITUTION: In a data transfer buffer circuit between data processors 1 and 2 differing in transfer rate, transfer buffer memory 3 of m-by-n-word capacity consists of the n-number cascaded FIFO memories of n-word capacity. On detecting the storage capacity of memory 3 reaching m by n, input inhibiton signal generating circuit 13 inhibits the write of memory 3 until the capacity reaches (m-k1)n. Next, read inhibition signal generating circuit 24 detects a signal showing that the storage capacity of memory 3 is zero and then inhibits the read until the capacity reaches k2n and also release the memory from the read inhibition when the input of memory 3 is interrupted. Consequently, the transfer efficiency can be improved.
COPYRIGHT: (C)1980,JPO&Japio
JP3496879A 1979-03-24 1979-03-24 Data transfer buffer circuit Pending JPS55127637A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3496879A JPS55127637A (en) 1979-03-24 1979-03-24 Data transfer buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3496879A JPS55127637A (en) 1979-03-24 1979-03-24 Data transfer buffer circuit

Publications (1)

Publication Number Publication Date
JPS55127637A true JPS55127637A (en) 1980-10-02

Family

ID=12428934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3496879A Pending JPS55127637A (en) 1979-03-24 1979-03-24 Data transfer buffer circuit

Country Status (1)

Country Link
JP (1) JPS55127637A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63167949A (en) * 1986-12-30 1988-07-12 Fanuc Ltd Data transfer system
JPH04233652A (en) * 1990-07-25 1992-08-21 Internatl Business Mach Corp <Ibm> Personal computer bus and video adapter for high-performance parallel interface
JP2011227919A (en) * 2000-06-09 2011-11-10 Trustees Of Columbia Univ In The City Of New York Small standby time fifo circuit for mixed asynchronous and synchronous system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63167949A (en) * 1986-12-30 1988-07-12 Fanuc Ltd Data transfer system
JPH04233652A (en) * 1990-07-25 1992-08-21 Internatl Business Mach Corp <Ibm> Personal computer bus and video adapter for high-performance parallel interface
JP2011227919A (en) * 2000-06-09 2011-11-10 Trustees Of Columbia Univ In The City Of New York Small standby time fifo circuit for mixed asynchronous and synchronous system

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