AU2001257403A1 - A low latency fifo circuit for mixed clock systems - Google Patents

A low latency fifo circuit for mixed clock systems

Info

Publication number
AU2001257403A1
AU2001257403A1 AU2001257403A AU5740301A AU2001257403A1 AU 2001257403 A1 AU2001257403 A1 AU 2001257403A1 AU 2001257403 A AU2001257403 A AU 2001257403A AU 5740301 A AU5740301 A AU 5740301A AU 2001257403 A1 AU2001257403 A1 AU 2001257403A1
Authority
AU
Australia
Prior art keywords
low latency
fifo circuit
clock systems
mixed clock
latency fifo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001257403A
Inventor
Tiberiu Chelcea
Steven M. Nowick
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Columbia University in the City of New York
Original Assignee
Columbia University in the City of New York
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Columbia University in the City of New York filed Critical Columbia University in the City of New York
Publication of AU2001257403A1 publication Critical patent/AU2001257403A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4031—Coupling between buses using bus bridges with arbitration
    • G06F13/4036—Coupling between buses using bus bridges with arbitration and deadlock prevention
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/12—Indexing scheme relating to groups G06F5/12 - G06F5/14
    • G06F2205/126—Monitoring of intermediate fill level, i.e. with additional means for monitoring the fill level, e.g. half full flag, almost empty flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip
AU2001257403A 2000-04-26 2001-04-26 A low latency fifo circuit for mixed clock systems Abandoned AU2001257403A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US19985100P 2000-04-26 2000-04-26
US60/199,851 2000-04-26
PCT/US2001/013777 WO2001082053A2 (en) 2000-04-26 2001-04-26 A low latency fifo circuit for mixed clock systems

Publications (1)

Publication Number Publication Date
AU2001257403A1 true AU2001257403A1 (en) 2001-11-07

Family

ID=22739284

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001257403A Abandoned AU2001257403A1 (en) 2000-04-26 2001-04-26 A low latency fifo circuit for mixed clock systems

Country Status (4)

Country Link
US (1) US7197582B2 (en)
AU (1) AU2001257403A1 (en)
CA (1) CA2407407A1 (en)
WO (1) WO2001082053A2 (en)

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AU2001255640A1 (en) 2000-04-25 2001-11-07 The Trustees Of Columbia University In The City Of New York Circuits and methods for high-capacity asynchronous pipeline processing
KR100783687B1 (en) 2000-10-23 2007-12-07 더 트러스티스 오브 콜롬비아 유니버시티 인 더 시티 오브 뉴욕 Asynchronous pipeline with latch controllers
US7269172B2 (en) 2003-01-07 2007-09-11 Sun Microsystems, Inc. Method and device for managing transmit buffers
CN100370415C (en) * 2003-04-26 2008-02-20 华为技术有限公司 Threading metod for processing data packets based on FIFO queue and device of
US20070186076A1 (en) * 2003-06-18 2007-08-09 Jones Anthony M Data pipeline transport system
EP1636725B1 (en) * 2003-06-18 2018-05-16 Imagination Technologies Limited Circuit register and method therefor
US7840949B2 (en) * 2003-11-03 2010-11-23 Ramal Acquisition Corp. System and method for data transformation using dataflow graphs
US7890684B2 (en) * 2006-08-31 2011-02-15 Standard Microsystems Corporation Two-cycle return path clocking
US7802032B2 (en) * 2006-11-13 2010-09-21 International Business Machines Corporation Concurrent, non-blocking, lock-free queue and method, apparatus, and computer program product for implementing same
JP4763629B2 (en) * 2007-02-20 2011-08-31 富士通セミコンダクター株式会社 Verification device, verification method, and program
US7913007B2 (en) 2007-09-27 2011-03-22 The University Of North Carolina Systems, methods, and computer readable media for preemption in asynchronous systems using anti-tokens
US8176280B2 (en) 2008-02-25 2012-05-08 International Business Machines Corporation Use of test protection instruction in computing environments that support pageable guests
US8669779B2 (en) 2008-06-27 2014-03-11 The University Of North Carolina At Chapel Hill Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits
US8346784B1 (en) 2012-05-29 2013-01-01 Limelight Networks, Inc. Java script reductor
US8352774B2 (en) 2010-06-23 2013-01-08 King Fahd University Of Petroleum And Minerals Inter-clock domain data transfer FIFO circuit
US9721495B2 (en) * 2013-02-27 2017-08-01 E Ink Corporation Methods for driving electro-optic displays
US9520180B1 (en) 2014-03-11 2016-12-13 Hypres, Inc. System and method for cryogenic hybrid technology computing and memory
US10250824B2 (en) 2014-06-12 2019-04-02 The University Of North Carolina At Chapel Hill Camera sensor with event token based image capture and reconstruction
US9703526B2 (en) * 2015-03-12 2017-07-11 Altera Corporation Self-stuffing multi-clock FIFO requiring no synchronizers
US10505704B1 (en) * 2015-08-02 2019-12-10 Wave Computing, Inc. Data uploading to asynchronous circuitry using circular buffer control

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4463443A (en) * 1979-07-24 1984-07-31 The United States Of America As Represented By The Secretary Of The Air Force Data buffer apparatus between subsystems which operate at differing or varying data rates
US5420887A (en) * 1992-03-26 1995-05-30 Pacific Communication Sciences Programmable digital modulator and methods of modulating digital data
CA2106271C (en) * 1993-01-11 2004-11-30 Joseph H. Steinmetz Single and multistage stage fifo designs for data transfer synchronizers
JPH07311735A (en) * 1994-05-18 1995-11-28 Hitachi Ltd Data transfer device
US6523060B1 (en) * 1995-04-07 2003-02-18 Cisco Technology, Inc. Method and apparatus for the management of queue pointers by multiple processors in a digital communications network
US5982772A (en) * 1995-11-06 1999-11-09 Sun Microsystems, Inc. Cell interface block partitioning for segmentation and re-assembly engine
US5956748A (en) * 1997-01-30 1999-09-21 Xilinx, Inc. Asynchronous, dual-port, RAM-based FIFO with bi-directional address synchronization
AU2001255640A1 (en) 2000-04-25 2001-11-07 The Trustees Of Columbia University In The City Of New York Circuits and methods for high-capacity asynchronous pipeline processing
US6850092B2 (en) * 2000-06-09 2005-02-01 The Trustees Of Columbia University Low latency FIFO circuits for mixed asynchronous and synchronous systems
WO2001095089A2 (en) 2000-06-09 2001-12-13 The Trustees Of Columbia University In The City Of New York Low latency fifo circuits for mixed asynchronous and synchronous systems
US6590424B2 (en) 2000-07-12 2003-07-08 The Trustees Of Columbia University In The City Of New York High-throughput asynchronous dynamic pipelines
US20040128413A1 (en) * 2001-06-08 2004-07-01 Tiberiu Chelcea Low latency fifo circuits for mixed asynchronous and synchronous systems

Also Published As

Publication number Publication date
WO2001082053A3 (en) 2003-04-24
CA2407407A1 (en) 2001-11-01
WO2001082053A2 (en) 2001-11-01
US7197582B2 (en) 2007-03-27
US20040125665A1 (en) 2004-07-01

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