AU2001238394A1 - Uniform clock timing circuit - Google Patents

Uniform clock timing circuit

Info

Publication number
AU2001238394A1
AU2001238394A1 AU2001238394A AU3839401A AU2001238394A1 AU 2001238394 A1 AU2001238394 A1 AU 2001238394A1 AU 2001238394 A AU2001238394 A AU 2001238394A AU 3839401 A AU3839401 A AU 3839401A AU 2001238394 A1 AU2001238394 A1 AU 2001238394A1
Authority
AU
Australia
Prior art keywords
timing circuit
clock timing
uniform clock
uniform
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001238394A
Inventor
Lanny L. Lewyn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lewyn Consulting Inc
Original Assignee
Lewyn Consulting Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lewyn Consulting Inc filed Critical Lewyn Consulting Inc
Publication of AU2001238394A1 publication Critical patent/AU2001238394A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10Distribution of clock signals, e.g. skew

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Analogue/Digital Conversion (AREA)
  • Logic Circuits (AREA)
AU2001238394A 2000-02-16 2001-02-14 Uniform clock timing circuit Abandoned AU2001238394A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/505,346 US6255884B1 (en) 2000-02-16 2000-02-16 Uniform clock timing circuit
US09505346 2000-02-16
PCT/US2001/005038 WO2001061439A1 (en) 2000-02-16 2001-02-14 Uniform clock timing circuit

Publications (1)

Publication Number Publication Date
AU2001238394A1 true AU2001238394A1 (en) 2001-08-27

Family

ID=24009947

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001238394A Abandoned AU2001238394A1 (en) 2000-02-16 2001-02-14 Uniform clock timing circuit

Country Status (3)

Country Link
US (1) US6255884B1 (en)
AU (1) AU2001238394A1 (en)
WO (1) WO2001061439A1 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6535038B2 (en) * 2001-03-09 2003-03-18 Micron Technology, Inc. Reduced jitter clock generator circuit and method for applying properly phased clock signals to clocked devices
US6522186B2 (en) * 2001-06-27 2003-02-18 Intel Corporation Hierarchical clock grid for on-die salphasic clocking
US6909127B2 (en) * 2001-06-27 2005-06-21 Intel Corporation Low loss interconnect structure for use in microelectronic circuits
JP2003092352A (en) * 2001-09-18 2003-03-28 Nec Corp Clock signal distributing circuit for semiconductor integrated circuit device
US6583659B1 (en) * 2002-02-08 2003-06-24 Pericom Semiconductor Corp. Reduced clock-skew in a multi-output clock driver by selective shorting together of clock pre-outputs
US7317863B2 (en) * 2006-03-09 2008-01-08 Adc Telecommunications, Inc. Fiber optic cable breakout configuration with retention block
WO2009078003A1 (en) * 2007-12-19 2009-06-25 Microsoft International Holdings B.V. An image sensor and a configuration for improved skew time
US7616043B2 (en) * 2008-02-12 2009-11-10 Sony Computer Entertainment Inc. Methods and apparatus for managing LSI power consumption and degradation using clock signal conditioning
US9459651B2 (en) * 2011-11-04 2016-10-04 Freescale Semiconductor, Inc. Multi-level clock signal distribution network and integrated circuit
US20140266376A1 (en) * 2013-03-15 2014-09-18 Analog Devices, Inc. Active clock tree for data converters
US9000823B2 (en) * 2013-09-12 2015-04-07 Taiwan Semiconductor Manufacturing Co., Ltd. 3D clock distribution circuits and methods
US9256246B1 (en) * 2015-01-29 2016-02-09 Qualcomm Incorporated Clock skew compensation with adaptive body biasing in three-dimensional (3D) integrated circuits (ICs) (3DICs)
US10234891B2 (en) * 2016-03-16 2019-03-19 Ricoh Company, Ltd. Semiconductor integrated circuit, and method for supplying clock signals in semiconductor integrated circuit
WO2020032915A1 (en) * 2018-08-06 2020-02-13 Intel Corporation Multi-voltage domain actuator signal network

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3761826A (en) * 1972-10-13 1973-09-25 Electronic Associates Multichannel programmer
KR100291185B1 (en) * 1997-06-26 2001-07-12 박종섭 Apparatus for minimizing clock skew

Also Published As

Publication number Publication date
US6255884B1 (en) 2001-07-03
WO2001061439A1 (en) 2001-08-23

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