AU2001266808A1 - Low latency fifo circuits for mixed asynchronous and synchronous systems - Google Patents

Low latency fifo circuits for mixed asynchronous and synchronous systems

Info

Publication number
AU2001266808A1
AU2001266808A1 AU2001266808A AU6680801A AU2001266808A1 AU 2001266808 A1 AU2001266808 A1 AU 2001266808A1 AU 2001266808 A AU2001266808 A AU 2001266808A AU 6680801 A AU6680801 A AU 6680801A AU 2001266808 A1 AU2001266808 A1 AU 2001266808A1
Authority
AU
Australia
Prior art keywords
sender
receiver
subsystem
time domain
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001266808A
Inventor
Tiberiu Chelcea
Steven M. Nowick
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Columbia University in the City of New York
Original Assignee
Columbia University in the City of New York
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Columbia University in the City of New York filed Critical Columbia University in the City of New York
Publication of AU2001266808A1 publication Critical patent/AU2001266808A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Information Transfer Systems (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

A FIFO design interfaces a sender subsystem and a receiver subsystem operating on different time domains. The sender subsystem and the receiver subsystem may be synchronous or asynchronous. The FIFO circuit includes a put interface configured to operate in accordance with the sender time domain and get interface configured to operate in accordance with the receiver time domain. The FIFO circuit includes an array of cells having a register and state controller indicative of the state of the cell. Each cell also has a put component part configured to operate according to the sender time domain including a put token passing circuit and put controller circuit. Each cell has get component part configured to operate according to the receiver time domain including a get token passing circuit and a get controller circuit. A mixed-clock relay station design interfaces a sender subsystem and a receiver subsystem working at different time domains, and where the latency between sender and receiver is large.
AU2001266808A 2000-06-09 2001-06-08 Low latency fifo circuits for mixed asynchronous and synchronous systems Abandoned AU2001266808A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US21064200P 2000-06-09 2000-06-09
US60/210,642 2000-06-09
PCT/US2001/018667 WO2001095089A2 (en) 2000-06-09 2001-06-08 Low latency fifo circuits for mixed asynchronous and synchronous systems

Publications (1)

Publication Number Publication Date
AU2001266808A1 true AU2001266808A1 (en) 2001-12-17

Family

ID=22783678

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001266808A Abandoned AU2001266808A1 (en) 2000-06-09 2001-06-08 Low latency fifo circuits for mixed asynchronous and synchronous systems

Country Status (9)

Country Link
EP (1) EP1374032B1 (en)
JP (2) JP4849763B2 (en)
KR (1) KR100761430B1 (en)
CN (1) CN100429616C (en)
AT (1) ATE370448T1 (en)
AU (1) AU2001266808A1 (en)
CA (1) CA2412438A1 (en)
DE (1) DE60130039T2 (en)
WO (1) WO2001095089A2 (en)

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* Cited by examiner, † Cited by third party
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WO2001082064A2 (en) 2000-04-25 2001-11-01 The Trustees Of Columbia University In The City Of New York Circuits and methods for high-capacity asynchronous pipeline processing
US7197582B2 (en) 2000-04-26 2007-03-27 Tiberiu Chelcea Low latency FIFO circuit for mixed clock systems
WO2002035346A1 (en) 2000-10-23 2002-05-02 The Trustees Of Columbia University In The City Of New York Asynchronous pipeline with latch controllers
KR20020094129A (en) * 2001-06-11 2002-12-18 이문기 Data transfer system of Token-ring type for data transfer
US7519759B2 (en) 2003-01-24 2009-04-14 Koninklijke Philips Electronics N.V. Pipeline synchronisation device
CN100463443C (en) * 2005-07-01 2009-02-18 中兴通讯股份有限公司 Asynchronous FIFO realizing system and realizing method
FR2890766B1 (en) * 2005-09-12 2007-11-30 Arteris Sa SYSTEM AND METHOD FOR ASYNCHRONOUS CIRCUIT COMMUNICATION BETWEEN SYNCHRONOUS SUB-CIRCUITS
FR2899413B1 (en) 2006-03-31 2008-08-08 Arteris Sa MESSAGE SWITCHING SYSTEM
FR2900017B1 (en) 2006-04-12 2008-10-31 Arteris Sa EXTERNAL CHIP FUNCTIONAL BLOCK INTERCONNECTION SYSTEM PROVIDED WITH A SINGLE COMMUNICATION PARAMETRABLE PROTOCOL
FR2902957B1 (en) 2006-06-23 2008-09-12 Arteris Sa SYSTEM AND METHOD FOR MANAGING MESSAGES TRANSMITTED IN AN INTERCONNECTION NETWORK
US7913007B2 (en) 2007-09-27 2011-03-22 The University Of North Carolina Systems, methods, and computer readable media for preemption in asynchronous systems using anti-tokens
WO2010039312A2 (en) 2008-06-27 2010-04-08 The University Of North Carolina At Chapel Hill Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits
CN102053815B (en) * 2009-11-05 2012-10-31 上海华虹集成电路有限责任公司 Synchronous first input first output (FIFO) circuit system
CN102754072B (en) 2009-12-14 2016-10-19 起元技术有限责任公司 Regulation user interface element
CN101739500B (en) * 2010-02-10 2012-06-06 龙芯中科技术有限公司 Multi-clock digital system and device and method thereof for clock determination
US10250824B2 (en) 2014-06-12 2019-04-02 The University Of North Carolina At Chapel Hill Camera sensor with event token based image capture and reconstruction
CN104298634B (en) * 2014-09-24 2017-06-30 四川九洲电器集团有限责任公司 Data transmission system based on FPGA and DSP
US9703526B2 (en) * 2015-03-12 2017-07-11 Altera Corporation Self-stuffing multi-clock FIFO requiring no synchronizers
US11423083B2 (en) 2017-10-27 2022-08-23 Ab Initio Technology Llc Transforming a specification into a persistent computer program
CN108268238A (en) * 2018-01-24 2018-07-10 深圳市风云实业有限公司 Data processing method, device, computer storage media and FIFO device
CN111274171B (en) * 2018-12-04 2022-02-11 珠海格力电器股份有限公司 Data transmission device and method
CN110825344A (en) * 2019-11-12 2020-02-21 天津飞腾信息技术有限公司 Asynchronous data transmission method and structure

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JPS587932A (en) * 1981-07-08 1983-01-17 Kyosan Electric Mfg Co Ltd Counter circuit
JPS63167949A (en) * 1986-12-30 1988-07-12 Fanuc Ltd Data transfer system
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JPH0277936A (en) * 1988-09-14 1990-03-19 Meidensha Corp Control system for fifo buffer memory
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JP2597040B2 (en) * 1990-09-12 1997-04-02 シャープ株式会社 FIFO memory device
JP2703668B2 (en) * 1991-03-18 1998-01-26 株式会社日立製作所 Data transfer control device and magnetic disk control device
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CA2106271C (en) * 1993-01-11 2004-11-30 Joseph H. Steinmetz Single and multistage stage fifo designs for data transfer synchronizers
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JPH0877125A (en) * 1994-09-09 1996-03-22 Hitachi Ltd Synchronous transfer system for asynchronous data
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US6208703B1 (en) * 1998-05-15 2001-03-27 Hewlett Packard Company First-in-first-out synchronizer
US6128678A (en) * 1998-08-28 2000-10-03 Theseus Logic, Inc. FIFO using asynchronous logic to interface between clocked logic circuits

Also Published As

Publication number Publication date
JP5379826B2 (en) 2013-12-25
EP1374032B1 (en) 2007-08-15
CN1478226A (en) 2004-02-25
WO2001095089A3 (en) 2003-10-16
CA2412438A1 (en) 2001-12-13
DE60130039D1 (en) 2007-09-27
KR100761430B1 (en) 2007-09-27
KR20030066333A (en) 2003-08-09
EP1374032A2 (en) 2004-01-02
JP2011227919A (en) 2011-11-10
WO2001095089A2 (en) 2001-12-13
JP4849763B2 (en) 2012-01-11
CN100429616C (en) 2008-10-29
JP2004510216A (en) 2004-04-02
ATE370448T1 (en) 2007-09-15
DE60130039T2 (en) 2008-05-15

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