JPH11175310A - Fifo memory control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the omission of asynchronous reception data and to evade time-out for disconnecting connection by a transmission side. SOLUTION: This circuit is provided with an up-down counter 35 for performing a count-up operation every time a write signal (WR) is supplied to a dual port RAM 31 and performing a count-down operation every time a read signal (RD) is supplied to the dual port RAM 31 and a near-full signal output circuit for comparing the counted value of the up-down counter 35 with the counted value (i) before the dual port RAM 31 becomes full set beforehand and outputting (asserting) near-full signals (Near-Full) for indicating that the dual port RAM 31 is near full when the counted value of the up-down counter 35 reaches the set counted value (i) (at the time of satisfying A>=B of a comparator circuit 38 for the near-full signals).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fifo memory control circuit mounted on various electronic devices.

[0002]

2. Description of the Related Art Conventionally, this type of FIFO memory control (F
first-in: First-out (first-in first-out type); one of memory controls for writing and reading data in order, such as in a stack memory of a computer. Memory control circuit 10 for performing the processing control)
As shown in FIG. 4, a k-word dual port RAM 1 as a memory, a write address circuit 2 for generating a write address for the dual port RAM 1, a read address circuit 3 for generating a read address for the dual port RAM 1, Full-empty control circuit 4 indicating the state of valid data in dual port RAM 1 from read address signal (RA) output from read address circuit 3 and write address signal (WA) output from write address circuit 2
Consists of

A reset signal (RESET) is externally connected to the write address circuit 2 for initialization, and a reset signal (RESET) is externally connected to the read address circuit 3 for initialization. ing. The read address signal (RA) is connected to the read address terminal (RA terminal) of the dual port RAM 1, and the write address signal (WA) is connected to the write address terminal (WA terminal) of the dual port RAM 1. I have. Further, the read address signal (RA) and the write address signal (W
A) is connected to the Full-Empty control circuit 4.

[0004] From the Full-Empty control circuit 4,
The write address signal (W
A), read address signal (RA) of read address circuit 3
A full signal (Full) indicating the state of valid data in the dual port RAM 1 and an empty signal (Em) based on the
pty) is output to the outside. This full signal (Fu
11) is output when the dual-port RAM 1 is full, and the empty signal (Empty) is output when the dual-port RAM 1 is empty. Specifically, the full signal (Full) is asserted when k words of data are written to the dual port RAM1, and the empty signal (Empty) is asserted when 0 words of data are written to the dual port RAM1. Is done.

An externally input FIFO memory write signal (WR) is applied to a write terminal (W) of the dual port RAM 1.
R terminal) and the write address circuit 2. Also, an externally input Fifo memory read signal (R
D) is connected to the read terminal (RD terminal) of the dual port RAM 1 and the read address circuit 3. further,
An externally input Fifo memory chip select signal (CS) is connected to a chip select terminal (CS terminal) of the dual port RAM 1.

A data bus 20 for outputting data to the outside is connected to a read data bus terminal (RDATA) of the dual port RAM 1, and a data bus 21 for inputting write data from the outside is connected to the dual port RAM 1.
Are connected to the write data bus terminal (WDATA terminal).

Next, FIG. 5 shows a configuration of a general microprocessor control circuit using the FIFO memory control circuit 10. As shown in FIG. In particular, the microprocessor control circuit receives data from a PC (personal computer) on the transmission side based on, for example, RS232C, and transfers the data word by word to the dual port RA of the FIFO memory control circuit 10.
The case of writing to M1 will be described.

The microprocessor control circuit comprises a CP
U (central processing unit) core 11, control ROM (read only memory) 12 storing execution programs and the like, work RAM (random access memory) 13, and I
1-chip C with built-in I / O port (input / output port) 14
A PU (one-chip CPU) 15 is provided.

A FIFO memory control circuit 10, a receiving section of a serial asynchronous communication control circuit for receiving data from a transmitting section of the serial asynchronous communication control circuit 17 of the PC as a transmitting side as external data, and a FIFO writing control circuit. , A Fifo memory control circuit chip select signal (CS1) output from the FIFO write circuit 16, and a Fifo memory control circuit chip select signal (CS2) output from the one-chip CPU 15. Is provided.

The AND circuit 18 is connected to a chip select terminal (CS terminal) of the FIFO memory control circuit 10. The reset signal (RESET) is connected to a reset terminal (RESET terminal) of the one-chip CPU 15 and the FIFO memory control circuit 10.

The data bus 2 of the one-chip CPU 15
0 is the read data bus terminal (RD
ATA terminal) and the FIFO writing circuit 16
Is connected to a write data bus terminal (WDATA terminal) of the FIFO memory control circuit 10.

The data read signal (RD) of the one-chip CPU 15 is connected to the RD terminal of the FIFO memory control circuit 10, and the full signal (Full) and the empty signal (Empty) of the FIFO memory control circuit 10 are transmitted to the one-chip CPU 15. Interrupt terminals IR (n), IR (n +
1). The I / O port 14 outputs an asynchronous communication control signal (DTR) to the serial asynchronous communication control circuit 17 in the transmitting PC.

A write signal (WR) output from the FIFO write circuit 16 is connected to a write terminal (WR terminal) of the FIFO memory control circuit 10. Also, Fifo
The write circuit 16 is configured to receive asynchronous reception data (RXD) from the serial asynchronous communication control circuit 17 in the PC on the transmission side.

Next, the operation of the microprocessor control circuit when performing asynchronous reception at a speed that can be processed by the one-chip CPU 15 will be described with reference to FIG.

When power is supplied to the microprocessor control circuit, a reset signal (RESET) is asserted, and the one-chip CPU 15 and the FIFO memory control circuit 1
0, the FIFO writing circuit 16 is initialized. Then, the one-chip CPU 15 controls the FIFO memory control circuit 10, F
The initialization process (program) of the iFo writing circuit 16 is executed. The one-chip CPU 15 notifies the transmitting-side PC that the asynchronous reception is enabled by asserting the asynchronous communication control signal DTR.

When the first asynchronous reception data (RXD) is input from the transmitting PC, the FIFO writing circuit 16 transmits the asynchronous reception data (RXD) to the data bus 21.
And the chip select signal (CS1) and the write signal (W
R) is asserted. As a result, the FIFO memory control circuit 10 writes data to the address 0 of the dual port RAM 1.

Subsequently, the FIFO writing circuit 16 places the asynchronous reception data on the data bus 21 and negates the chip select signal (CS1) and the write signal (WR). At this time, the address value of the write address circuit 2 is incremented by one. Then, the empty signal (Empty) is negated.

Next, when the second asynchronous reception data (RXD) is input from the PC on the transmission side, the FIFO writing circuit 16 places the asynchronous reception data (RXD) on the data bus 21 and outputs the chip select signal (CS1). ) And the write signal (W
R) is asserted. Thereby, the FIFO memory control circuit 10 writes data to the address 1 of the dual port RAM 1.

Subsequently, the FIFO write circuit 16 negates the chip select signal (CS1) and the write signal (WR). At this time, the address value of the write address circuit 2 is +1
Is done. The above-described operation is repeatedly performed by the FIFO writing circuit 16.

When the (k + 1) th asynchronous reception data (RXD) is input from the transmitting PC, the FIFO writing circuit 16 places the asynchronous reception data (RXD) on the data bus 21 and outputs the chip select signal (CS1). And a write signal (WR). Fifo memory control circuit 10
Writes data to the address k of the dual port RAM1.

Subsequently, the FIFO writing circuit 16 negates the chip select signal (CS1) and the write signal (WR). At this time, the address value of the write address circuit 2 becomes 0. Then, a full signal (Full) is asserted,
An interrupt signal is input to the interrupt terminal IR (n) of the one-chip CPU 15, and the one-chip CPU 15 starts an IR (n) interrupt process. That is, the one-chip CPU 15 notifies the transmitting PC by negating the DTR that the dual-port RAM 1 is in a full (full) state and the asynchronous reception becomes impossible.

Next, the one-chip CPU 15 asserts a chip select signal (CS2) and a data read signal (RD). Then, the FIFO memory control circuit 10 transfers the 0th data of the dual port RAM 1 to the data bus 20.
Output to Thus, the one-chip CPU 15 reads the data on the data bus 20.

Subsequently, the one-chip CPU 15 negates the chip select signal (CS2) and the data read signal (RD). At this time, the FIFO memory control circuit 10 increments the address value of the read address circuit 3 by one.

Next, the one-chip CPU 15 asserts a chip select signal (CS2) and a data read signal (RD). Then, the FIFO memory control circuit 10 transfers the first data of the dual port RAM 1 to the data bus 21.
Output to Thus, the one-chip CPU 15 reads the data on the data bus 20.

Subsequently, the one-chip CPU 15 negates the chip select signal (CS2) and the data read signal (RD). At this time, the FIFO memory control circuit 10 increments the address value of the read address circuit 3 by one. The above-described operation is repeatedly performed by the one-chip CPU 15.

When the one-chip CPU 15 asserts the chip select signal (CS2) and the data read signal (RD), and the FIFO memory control circuit 10 outputs the (k + 1) th data of the dual port RAM 1 to the data bus 20, the one-chip CPU 15 The CPU 15 reads the data on the data bus 20.

Subsequently, the one-chip CPU 15 negates the chip select signal (CS2) and the data read signal (RD). At this time, when the address value of the read address circuit 3 is incremented by 1, the address value of the read address circuit 3 becomes 0. Then, FiF
o The memory control circuit 10 causes the empty signal (Empt
y) is asserted, and an interrupt signal is input to the interrupt terminal IR (n + 1) of the one-chip CPU 15.

As a result, the one-chip CPU 15
The (n + 1) interrupt process is started. That is, the one-chip CPU 15 notifies the transmitting PC by asserting the DTR that asynchronous reception has become possible. Then, the one-chip CPU 15 returns to the interrupt processing of IR (n), and thereafter returns to the main processing.

[0029]

As described above, when asynchronous reception is performed at a speed that can be processed by the one-chip CPU 15, the dual-port RAM 1 of the FIFO memory control circuit 10 on the receiving side becomes full when the PC on the transmitting side becomes full. The time from outputting the data to be written to address k in a (full) state until outputting the next data is one-chip CPU 15.
From this point of view, if the dual port RAM 1 becomes full on the receiving side and asynchronous reception is disabled during this period (DTR output to the transmitting PC is negated), the transmitting PC Can wait for the next data to be sent, so that this data is not discarded.

However, when the one-chip CPU 15 performs asynchronous reception at a speed that cannot be processed, the transmission-side PC outputs data to be written to address k of the dual port RAM 1 and then outputs the next data. Since the time is shorter when viewed from the one-chip CPU 15, the notification that the dual port RAM 1 is full on the receiving side and asynchronous reception is disabled (the DTR output to the PC on the transmitting side is negated) is made in time. Instead, the transmitting PC may transmit the next data, and in this case, the transmitted data is discarded. That is, there is a problem that data is missed.

The above-mentioned problem which occurs when the one-chip CPU 15 performs asynchronous reception at a speed that cannot be processed by the one-chip CPU 15 will be described below together with the operation of the microprocessor control circuit.
This will be specifically described with reference to FIG.

When power is supplied to the microprocessor control circuit, a reset signal (RESET) is asserted,
One-chip CPU 15, Fifo memory control circuit 10,
The FIFO writing circuit 16 is initialized. The one-chip CPU 15 is connected to the FiFo memory control circuit 10 and the FiF
The initialization processing (program) of the o writing circuit 16 is executed. The one-chip CPU 15 notifies the transmitting-side PC that the asynchronous reception is enabled by asserting the asynchronous communication control signal DTR.

When the first asynchronous reception data (RXD) is input from the transmitting PC, the FIFO writing circuit 16 transmits the asynchronous reception data (RXD) to the data bus 21.
And the chip select signal (CS1) and the write signal (W
R) is asserted. As a result, the FIFO memory control circuit 10 writes data to the address 0 of the dual port RAM 1.

Subsequently, the FIFO writing circuit 16 negates the chip select signal (CS1) and the write signal (WR). At this time, the address value of the write address circuit 2 is +1
Is done. Then, the empty signal (212) is negated.

Next, when the second asynchronous reception data (RXD) is input from the PC on the transmission side, the FIFO writing circuit 16 places the asynchronous reception data (RXD) on the data bus 21 and outputs the chip select signal (CS1). ) And the write signal (W
R) is asserted. Thereby, the FIFO memory control circuit 10 writes data to the address 1 of the dual port RAM 1.

Subsequently, the FIFO write circuit 16 negates the chip select signal (CS1) and the write signal (WR). At this time, the address value of the write address circuit 2 is +1
Is done. The above-described operation is repeatedly performed by the FIFO writing circuit 16.

Thereafter, when the (k + 1) th asynchronous reception data (RXD) is input from the PC on the transmission side, the FIFO writing circuit 16 places the asynchronous reception data (RXD) on the data bus 21 and the chip select signal (CS1). And a write signal (WR). Fifo memory control circuit 10
Writes data to the address k of the dual port RAM1.

Subsequently, the FIFO writing circuit 16 negates the chip select signal (CS1) and the write signal (WR). At this time, the address value of the write address circuit 2 becomes 0. Then, a full signal (Full) is asserted,
An interrupt signal is input to an interrupt terminal IR (n) of the one-chip CPU 15.

In this case, since the data is transmitted from the transmitting PC by asynchronous reception at a speed that cannot be processed by the one-chip CPU 15, the PC on the transmitting side must be transmitted before the DTR is negated by the interrupt processing of the one-chip CPU 15. To k
The + 2nd asynchronous reception data is input. Therefore, the notification that the asynchronous reception is impossible due to the full state of the dual port RAM 1 (negating the DTR to be output to the PC on the transmission side) cannot be made in time, and the k + 2th asynchronous reception data is input to the FIFO writing circuit 16. Will be done.

At this time, since the dual port RAM 1 is in the full state, the FIFO writing circuit 16 discards the (k + 2) th asynchronous reception data. Thus, the asynchronous reception data is missed.

Next, the one-chip CPU 15 asserts the chip select signal (CS2) and the data read signal (RD). Then, the FIFO memory control circuit 10 transfers the 0th data of the dual port RAM 1 to the data bus 21.
Output to Thus, the one-chip CPU 15 reads the data on the data bus 20.

Subsequently, the one-chip CPU 15 negates the chip select signal (CS2) and the data read signal (RD). At this time, the FIFO memory control circuit 10 increments the address value of the read address circuit 3 by one.

Next, the one-chip CPU 15 asserts the chip select signal (CS2) and the data read signal (RD). Then, the FIFO memory control circuit 10 transfers the first data of the dual port RAM 1 to the data bus 21.
Output to Thus, the one-chip CPU 15 reads the data on the data bus 20.

Subsequently, the one-chip CPU 15 negates the chip select signal (CS2) and the data read signal (RD). At this time, the FIFO memory control circuit 10 increments the address value of the read address circuit 3 by one. The above-described operation is repeatedly performed by the one-chip CPU 15.

Thereafter, the one-chip CPU 15 asserts the chip select signal (CS2) and the data read signal (RD), and when the FIFO memory control circuit 10 outputs the (k + 1) th data of the dual port RAM 1 to the data bus 20, the one-chip CPU 15 The CPU 15 reads the data on the data bus 20.

The one-chip CPU 15 negates the chip select signal (CS2) and the data read signal (RD). At this time, when the address value of the read address circuit 3 is incremented by 1, the address value of the read address circuit 3 becomes 0. Then, the empty signal (Empty) is asserted by the FIFO memory control circuit 10 and the one-chip CPU 15 is given an interrupt terminal IR (n).
An interrupt signal is input to +1).

As a result, the one-chip CPU 15
The (n + 1) interrupt process is started. That is, the one-chip CPU 15 notifies the transmitting PC by asserting the DTR that asynchronous reception has become possible. Then, the one-chip CPU 15 returns to the interrupt processing of IR (n), and thereafter returns to the main processing.

On the receiving side, a dual port RAM is used.
After notifying (1) that the 1 has become full and asynchronous reception is no longer possible (negating the DTR to be output to the PC on the transmitting side), the one-chip CPU 15 performs data reading processing on the receiving side. When the port RAM 1 is in the empty (empty) state, the fact that asynchronous reception is possible is notified (the DTR to be output to the PC on the transmitting side is asserted), and during that time, the DTR is negated. On the other hand, while the DTR is negated, the PC on the transmitting side is in a state of stopping data transmission.

Therefore, if the time during which the DTR is negated (the time during which the one-chip CPU 15 is reading data from the dual port RAM 1) is long, the transmission side P
If C has a timeout function,
There is a problem that the Fo memory control circuit 10 determines that it is inoperable and disconnects the connection.

Therefore, the present invention prevents the loss of data when performing asynchronous reception at a speed that cannot be processed by a one-chip CPU.
It is another object of the present invention to provide a FIFO memory control circuit that can avoid a timeout in which the transmission side disconnects the connection.

[0051]

According to the present invention, there is provided a memory capable of reading and writing data, a write address circuit for generating a write address based on a write signal to the memory, and a memory. And a read address circuit for generating a read address based on a read signal to a memory, a count-up operation is performed each time a write signal is supplied to the memory, and a read-out signal is supplied to the memory. An up / down counter for performing a countdown operation, comparing the count value of the up / down counter with a preset count value before the memory is full, when the count value of the up / down counter reaches a set count value, or Near-full signal that outputs a near-full signal indicating that the memory is almost full when the set count value is exceeded A FiFo memory control circuit, characterized in that a and power circuit.

According to a second aspect of the present invention, when the count value of the up / down counter reaches the set count value, the count value of the up / down counter is compared with a preset count value before the memory becomes empty. 2. The FIFO memory control circuit according to claim 1, further comprising a near empty signal output circuit that outputs a near empty signal indicating that the memory is almost empty when the count value becomes smaller than the set count value.

In the present invention having such a configuration, a near-full signal is output before the memory becomes full, and it can be notified to the outside that asynchronous reception becomes impossible based on this near-full signal. Therefore, even if the next data is input from outside before the notification that the asynchronous reception becomes impossible, the next data can be written to the memory without being discarded.

Further, a near empty signal is output before the memory becomes empty, and it is possible to notify the outside of the transmitting side that asynchronous reception is possible. That is, the notification that the asynchronous reception is enabled can be transmitted to the outside more quickly. For this reason, for example, even if the external transmission side PC (personal computer) has a timeout function, it is possible to transmit a notification that asynchronous reception has become possible before the timeout occurs.

[0055]

FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to FIG. FIG. 1 is a diagram showing a configuration of a Fifo memory control circuit according to the present invention. The FIFO memory control circuit 30 includes a k-word dual port RAM 31, a write address circuit 32 for generating a write address for the dual port RAM 31, a read address circuit 33 for generating a read address for the dual port RAM 31, and a read address circuit 33. From the read address signal (RA) output from the write address signal (WA) and the write address signal (WA) output from the write address circuit.
And a Full-Empty control circuit 34 indicating the state of valid data in the data.

An up-down counter 35 which performs a count-up operation each time a write signal (WR) is applied to dual port RAM 31 and performs a count-down operation each time a read signal (RD) is applied to dual port RAM 31; Near-full signal (Near-Full) indicating that the dual port RAM 31 is almost full
, A near full signal setting register 36 for setting the count value of an up / down counter 35 for outputting the near-empty signal (Near-Empty) indicating that the dual-port RAM 31 is almost empty. A near-empty signal setting register 37 for setting a count value is provided.

Further, the actual up / down counter 35
Is compared with the count value B set in the near full signal setting register 36, and a near full signal composed of a comparator or the like that outputs (asserts) a near full signal (Near-Full) when A ≧ B is satisfied. The comparison circuit 38 compares the actual count value A of the up / down counter 35 with the count value B set in the near-empty signal setting register 37, and outputs a near-empty signal (Near-Empty) when A ≦ B is satisfied. A near-empty signal comparison circuit 39 including a comparator for outputting (asserting) is provided.

The near full signal setting register 3
6 and the near-full signal comparison circuit 38 constitute a near-full signal output circuit, and the near-empty signal setting register 37
The near-empty signal comparison circuit 39 forms a near-empty signal output circuit. The near full signal setting register 36 includes a CPU (for example, a one-chip CP described later).
Register write signal (NFC etc.)
By writing data based on K), a count value can be set. The near-empty signal setting register 37 can also set a count value by writing data based on a register write signal (NECK) from the CPU.

A reset signal (RESET) is externally connected to the write address circuit 32 for initialization, and a reset signal (RESET) is externally connected to the read address circuit 33 for initialization. ing. Also,
A reset signal (RESET) is externally connected to the up / down counter 35 for initialization. Further, a reset signal (RESET) is externally connected to the near full signal setting register 36 and the near empty register for initialization.

The read address signal (RA) is connected to the read address terminal (RA terminal) of the dual port RAM 31, and the write address signal (WA) is connected to the write address terminal (WA terminal) of the dual port RAM 31. It is connected. Further, the read address signal (RA)
And the write address signal (WA) is Full-Empty.
It is connected to the control circuit 34.

The full-empty control circuit 34 outputs valid data in the dual port RAM 31 based on the write address signal (WA) to the write address circuit 32 and the read address signal (RA) of the read address circuit 33. A full signal (Full) indicating the state and an empty signal (Empty) are output to the outside. This full signal (Full) is output when the dual port RAM 31 is full, and the empty signal (Empty) is
Output when the dual port RAM 31 is empty. Specifically, the full signal (Full) is asserted when k words of data are written to the dual port RAM 31, and the empty signal (Empty) is asserted when 0 words of data are written to the dual port RAM 31. Is done. The externally input FIFO memory write signal (WR) is connected to the write terminal (WR terminal) of the dual port RAM 31, the write address circuit 32, and the UP terminal of the up / down counter 35. The externally input Fifo memory read signal (RD) is supplied to the read terminal (RD terminal) of the dual port RAM 31, the read address circuit 33, and the DOWN of the up / down counter 35.
Connected to terminal. Further, F input from outside
The ifo memory chip select signal (CS) is connected to the chip select terminal (CS terminal) of the dual port RAM 31.

A data bus 40 for outputting data to the outside is connected to a read data bus terminal (RDATA) of the dual port RAM 31, and a data bus 41 for inputting data from the outside is connected to the dual port RAM 31.
, A write data bus terminal (WDATA terminal), a near full signal setting register 36, and a near empty signal setting register 37.

The near full register write signal (NFCK) input from the outside is connected to the NFCK terminal of the near full signal setting register 36, and the near empty write signal (NECK) input from the outside is near. It is connected to the NECK terminal of the empty signal setting register 37.

The output terminal (CNTQ terminal) of the up / down counter 35 is connected to the A
The terminal and the A terminal of the near-empty signal comparison circuit 39 are connected. The output terminal (NFQ terminal) of the near full signal setting register 36 is connected to the B of the near full signal comparison circuit 38.
The output terminal (NEQ terminal) of the near empty signal setting register 37 is connected to the B terminal of the near empty signal comparison circuit 39.

Next, FIG. 2 shows a configuration of a general microprocessor control circuit using the FIFO memory control circuit 30. In particular, data is received by a microprocessor control circuit from a transmitting PC (personal computer) based on, for example, RS232C, and the data is sent word by word to the dual port RA of the FIFO memory control circuit 30.
The case of writing to M31 will be described.

The microprocessor control circuit includes a CP
U (central processing unit) core 61, control ROM (read only memory) 62 storing execution programs and the like, work RAM (random access memory) 63 and I
1-chip C with built-in / O port (input / output port) 64
A PU (one-chip CPU) 60 is provided.

The FIFO memory control circuit 30, a reception unit of the serial asynchronous communication control circuit for receiving data from the transmission unit of the serial asynchronous communication control circuit 67 of the PC as the transmission side as external data, and a Fifo write control circuit , A chip select signal for a FIFO memory control circuit (CS1) output from the FIFO write circuit 66, and a chip select signal for a FIFO memory control circuit (CS2) output from the one-chip CPU 60. And a logical product circuit 68.

The AND circuit 68 is connected to the chip select terminal (CS terminal) of the FIFO memory control circuit 30. The reset signal (RESET) is connected to the reset terminal (RESET terminal) of the one-chip CPU 60 and the FIFO memory control circuit 30.

The data bus 4 of the one-chip CPU 60
0 is the read data bus terminal (RD
ATA terminal) and the FIFO writing circuit 66
Is connected to the write data bus terminal (WDATA terminal) of the FIFO memory control circuit 30.

The data read signal (RD) of the one-chip CPU 60 is connected to the RD terminal of the FIFO memory control circuit 30, and the full signal (Full) and the empty signal (Empty) of the FIFO memory control circuit 30 are transmitted to the one-chip CPU 60. Interrupt terminals IR (n), IR (n +
1). Further, the near-full signal (Near-Full) and the near-empty signal (Near-Empty) of the FIFO memory control circuit 30 are output to the interrupt terminals IR (m) and IR (m + 1) of the one-chip CPU 60.
Connected to each other. The above I / O port 6
4, the asynchronous communication control signal (DTR) is transmitted from the PC on the transmission side.
Is output to the serial asynchronous communication control circuit 67.

The write signal (WR) output from the FIFO write circuit 66 is connected to the write terminal (WR terminal) of the FIFO memory control circuit 30. Also, Fifo
The asynchronous receiving data (RXD) is input to the writing circuit 66 from the serial asynchronous communication control circuit 67 in the PC on the transmitting side. Further, the one-chip CPU 60 sends a register write signal (NFCK) and a register write signal (NECK) to the FIFO memory control circuit 30.
Has been supplied. Next, the operation of the microprocessor control circuit when the one-chip CPU 60 performs asynchronous reception at a speed that cannot be processed will be described with reference to FIG.

When power is supplied to the microprocessor control circuit, a reset signal (RESET) is asserted, and the one-chip CPU 60 and the FIFO memory control circuit 3
0, the FIFO writing circuit 66 is initialized. Then, the one-chip CPU 60 operates the FIFO memory control circuit 30, F
The initialization process (program) of the iFo writing circuit 66 is executed.

Thus, the up / down counter 35 is initialized to zero. Further, the one-chip CPU 60 asserts a register write signal (NFCK) for a near full signal, and sets a constant i (i <k) as a count value for comparison in the near full signal setting register 36. Further, the one-chip CPU 60 asserts a register write signal (NECK) for the near empty signal and sets the near empty signal setting register 37 as a constant j as a count value for comparison.
(J> 0) is set. The one-chip CPU 60 notifies the transmission-side PC that the asynchronous reception is enabled by asserting the asynchronous communication control signal DTR.

When the first asynchronous reception data (RXD) is input from the PC on the transmission side, the FIFO writing circuit 66 transmits the asynchronous reception data (RXD) to the data bus 41.
And the chip select signal (CS1) and the write signal (W
R) is asserted. As a result, the FIFO memory control circuit 30 writes data to the address 0 of the dual port RAM 31.

Subsequently, the FIFO writing circuit 66 negates the chip select signal (CS1) and the write signal (WR). At this time, the address value of the write address circuit 32 is +
The count value of the up / down counter 35 is +1.
Is done. Then, the empty signal (Empty) is negated.

Next, when the second asynchronous reception data (RXD) is input from the PC on the transmission side, the FIFO writing circuit 66 puts the asynchronous reception data (RXD) on the data bus 41 and outputs the chip select signal (CS1). ) And the write signal (W
R) is asserted. As a result, the FIFO memory control circuit 30 writes data to the address 1 of the dual port RAM 31.

Subsequently, the FIFO writing circuit 66 negates the chip select signal (CS1) and the write signal (WR). At this time, the address value of the write address circuit 32 is +
The count value of the up / down counter 35 is +1.
Is done. The operation described above is repeatedly performed by the FIFO writing circuit 66.

When the (j + 1) th asynchronous reception data (RXD) is input from the transmitting PC, the FIFO writing circuit 66 puts the asynchronous reception data (RXD) on the data bus 41 and outputs the chip select signal (CS1). And a write signal (WR). Fifo memory control circuit 30
Writes data to the address j of the dual port RAM 31.

Subsequently, the FIFO write circuit 66 negates the chip select signal (CS1) and the write signal (WR). At this time, the address value of the write address circuit 32 is +
1 is done. Further, the count value of the up / down counter 35 is incremented by one, and the count value becomes j + 1. As a result, the count value of the up / down counter 35 becomes larger than the count value j set in the near empty signal setting register 37, and does not satisfy A ≦ B. Therefore, the near empty signal comparison circuit 39 causes the near empty signal (Near− Empty) is negated.

Next, when the i-th asynchronous reception data (RXD) is input from the transmitting PC, the FIFO writing circuit 66 puts the asynchronous reception data (RXD) on the data bus 41, and outputs the chip select signal (CS1). ) And the write signal (W
R) is asserted. As a result, the FIFO memory control circuit 30 writes data to the i-1 address of the dual port RAM 31.

Subsequently, the FIFO writing circuit 66 negates the chip select signal (CS1) and the write signal (WR). At this time, the address value of the write address circuit 32 is incremented by one. Further, the count value of the up / down counter 35 is incremented by 1 and the count value becomes i. As a result, the count value of the up / down counter 35 becomes equal to the count value i set in the near full signal setting register 36, so that A ≧ B is satisfied. Therefore, the near full signal (Near-Ful)
1) is asserted, an interrupt signal is input to the interrupt terminal IR (m) of the one-chip CPU 60, and the one-chip CPU 6
0 starts the interrupt processing. That is, one-chip CPU
Numeral 60 indicates to the transmitting PC by negating the DTR that the dual port RAM 31 is in the near full state and asynchronous reception becomes impossible.

In this way, it is possible to notify the transmitting PC that the asynchronous reception becomes impossible before the dual port RAM 31 becomes full (negate the DTR to be output to the transmitting PC). In this state, an empty space still remains in the dual port RAM 31. Therefore, prior to the notification that the asynchronous reception becomes impossible, the i + 1-th asynchronous reception data (RX
Even if D) is input, it can be written to the dual port RAM 31 without discarding it.

That is, when the (i + 1) th asynchronous reception data (RXD) is input from the transmitting PC earlier than the notification that the asynchronous reception becomes impossible, the FIFO writing circuit 6
6 places the asynchronous receive data (RXD) on the data bus 41, and outputs the chip select signal (CS1) and the write signal (WR).
Assert Thereby, the FIFO memory control circuit 30 writes the data to the address i + 1 (≦ k) of the dual port RAM 31.

Subsequently, the FIFO write circuit 66 negates the chip select signal (CS1) and the write signal (WR). At this time, the address value of the write address circuit 32 is +
1 is done. Further, the count value of the up / down counter 35 is incremented by one, and the count value becomes i + 1. Thus, the data received from the transmitting PC is reliably written to the dual port RAM 31 before notifying the transmitting PC that the asynchronous reception becomes impossible. Therefore, there is no possibility of missing the asynchronous reception data.

Next, the one-chip CPU 60 asserts the chip select signal (CS2) and the data read signal (RD). Then, the FIFO memory control circuit 30 transfers the 0th data of the dual port RAM 31 to the data bus 4.
Output to 1. Thus, the one-chip CPU 60 reads the data on the data bus 40.

Subsequently, the one-chip CPU 60 negates the chip select signal (CS2) and the data read signal (RD). At this time, the FIFO memory control circuit 30 increases the address value of the read address circuit 33 by one. Then, the count value of the up / down counter 35 is decremented by one.

Next, the one-chip CPU 60 asserts the chip select signal (CS2) and the data read signal (RD). Then, the FIFO memory control circuit 30 transfers the first data of the dual port RAM 31 to the data bus 4.
Output to 1. Thus, the one-chip CPU 60 reads the data on the data bus 40.

Subsequently, the one-chip CPU 60 negates the chip select signal (CS2) and the data read signal (RD). At this time, the FIFO memory control circuit 30 increases the address value of the read address circuit 33 by one. Then, the count value of the up / down counter 35 is decremented by one. The above operation is repeatedly performed by the one-chip CPU 60.

When the one-chip CPU 60 asserts the chip select signal (CS2) and the data read signal (RD), and the FIFO memory control circuit 30 outputs the (j-1) th data of the dual port RAM 31 to the data bus 40, One-chip CPU 60 reads data on data bus 40.

Subsequently, the one-chip CPU 60 negates the chip select signal (CS2) and the data read signal (RD). At this time, the FIFO memory control circuit 30 increases the address value of the read address circuit 33 by one. Also,
The count value of the up / down counter 35 is decremented by one, and the count value becomes j. Thus, the count value of the up / down counter 35 becomes equal to the count value j set in the near empty signal setting register 37, and A ≦
B, the near-empty signal (Near-Empt) is output by the near-empty signal comparing circuit 39.
y) is asserted, an interrupt signal is input to the interrupt terminal IR (m + 1) of the one-chip CPU 60, and the one-chip CP
U60 starts the interrupt processing. That is, one chip C
The PU 60 notifies the transmitting PC by asserting the DTR that the dual port RAM 31 is in the near-empty state and the asynchronous reception is possible, and returns to the IR (m) interrupt processing, and then returns to the main processing. . Thus,
Before the dual-port RAM 31 enters the empty state, it is possible to notify the transmitting PC that the asynchronous reception has become possible (negate the DTR to be output to the transmitting PC).

As described above, each time the write signal (WR) is applied to the dual port RAM 31, the count-up operation is performed, and the read signal (R) is sent to the dual port RAM 31.
D), an up / down counter 35 that performs a countdown operation each time a given value is given,
When the count value of the up / down counter 35 reaches the set count value i (when A ≧ B of the near-full signal comparison circuit 38 is satisfied) as compared with the count value i before the counter 31 becomes full, the dual port By providing a near-full signal output circuit that outputs (asserts) a near-full signal (Near-Full) indicating that the RAM 31 is almost full, asynchronous reception at a speed at which the one-chip CPU cannot process reception control of asynchronous reception is provided. Is performed, it is possible to notify the transmitting PC that the asynchronous reception is disabled before the dual port RAM 31 becomes full (negate the DTR to be output to the transmitting PC). . Therefore, prior to the notification that the asynchronous reception becomes impossible, the next asynchronous reception data (RX
Even if D) is input, it can be written to the dual port RAM 31 without discarding it. This allows
Data can be prevented from being missed.

Conventionally, data reading has not been started until the dual port RAM 31 is full, but in the present embodiment, the dual port RAM 31
Before the state becomes full, that is, the near full signal (Near
When (r-Full) is output (asserted), data reading is started, so that data reading can be completed earlier than before. For this reason, a notification to the effect that asynchronous reception has become possible earlier is sent to the transmitting PC (P.
The DTR to be output to C can be negated. For this reason, even if the transmitting PC has a timeout function, it is possible to transmit a notification that asynchronous reception has become possible before the timeout occurs, and it is possible to avoid a timeout in which the transmission side disconnects the connection.

Further, the count value of the up / down counter 35 is compared with a preset count value j before the dual port RAM 31 becomes empty, and when the count value of the up / down counter 35 reaches the set count value j, By providing a near empty signal output circuit that outputs (asserts) a near empty signal (Near-Empty) indicating that the port RAM 31 is almost empty, asynchronous reception is possible before the dual port RAM 31 enters the empty state. Can be notified to the transmitting PC (Negative DTR to be output to the transmitting PC). That is, the notification that the asynchronous reception has been enabled can be transmitted to the PC on the transmission side earlier. Therefore, even if the sending PC has a timeout function,
A notification that asynchronous reception has become possible can be transmitted before the timeout occurs, and a timeout in which the transmission side disconnects the connection can be avoided.

In the embodiment of the present invention, the actual count value A of the up / down counter 35 and the near full signal comparison circuit 38 of the near full signal output circuit are the count value set in the near full signal setting register 36. B
Are compared, and when A ≧ B is satisfied, the near full signal (Nea
Although the output of r-Full is described, the present invention is not limited to this, and a near-full signal (Near-Full) may be output when A> B is satisfied.

In the embodiment of the present invention, the actual count value A of the up / down counter 35 and the near empty signal comparison circuit 39 of the near empty signal output circuit are set in the near empty signal setting register 37. In the above description, the count value B is compared and the near-empty signal (Near-Empty) is output when A ≦ B is satisfied. However, the present invention is not limited to this. An empty signal (Near-Empty) may be output.

[0096]

As described above in detail, according to the present invention, it is possible to prevent the loss of data when performing asynchronous reception at a speed that cannot be processed by the one-chip CPU and to prevent data loss. Can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a FIFO memory control circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a general microprocessor control circuit using the FIFO memory control circuit shown in FIG. 1;

FIG. 3 shows an operation of the microprocessor control circuit shown in FIG. 2 when the one-chip CPU 60 performs asynchronous reception at a speed that cannot be processed.

FIG. 4 is a block diagram showing a configuration of a conventional FIFO memory control circuit.

FIG. 5 is a block diagram showing a configuration of a general microprocessor control circuit using the FIFO memory control circuit shown in FIG. 4;

6 is a diagram showing operation timings in the case of performing asynchronous reception at a speed that can be processed by a one-chip CPU for the microprocessor control circuit shown in FIG. 5;

FIG. 7 is a diagram showing operation timings when the one-chip CPU performs asynchronous reception at a speed that cannot be processed by the microprocessor control circuit shown in FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 30 ... Fifo memory control circuit 31 ... Dual port RAM 32 ... Write address circuit 33 ... Read address circuit 35 ... Up / down counter 36 ... Near full signal setting register 37 ... Near empty signal setting register 38 ... Near full signal comparison circuit 39 … Near empty signal comparison circuit 60… One chip CPU

Claims (2)

[Claims] A memory capable of reading and writing data, a write address circuit for generating a write address based on a write signal to the memory, and a read address based on a read signal to the memory An up-down counter for performing a count-up operation each time a write signal is applied to the memory, and performing a count-down operation each time a read signal is applied to the memory; The count value of the up / down counter is compared with a preset count value before the memory is full, and when the count value of the up / down counter reaches the set count value or exceeds the set count value. A near full signal output circuit that outputs a near full signal indicating that the memory is almost full. FiFo memory control circuit, characterized in that a and. And comparing the count value of the up / down counter with a preset count value before the memory is emptied, when the count value of the up / down counter reaches the set count value or the set value. 2. The FiF according to claim 1, further comprising a near-empty signal output circuit that outputs a near-empty signal indicating that the memory is almost empty when the count value becomes smaller than the count value.
o Memory control circuit.