ATE145495T1 - Verfahren zur verdrahtung einer halbleiterschaltung - Google Patents

Verfahren zur verdrahtung einer halbleiterschaltung

Info

Publication number
ATE145495T1
ATE145495T1 AT91304830T AT91304830T ATE145495T1 AT E145495 T1 ATE145495 T1 AT E145495T1 AT 91304830 T AT91304830 T AT 91304830T AT 91304830 T AT91304830 T AT 91304830T AT E145495 T1 ATE145495 T1 AT E145495T1
Authority
AT
Austria
Prior art keywords
wiring
wiring layer
semiconductor circuit
contact hole
hole
Prior art date
Application number
AT91304830T
Other languages
English (en)
Inventor
Shigeyuki Canon Kabu Matsumoto
Osamu Canon Kabushiki Ka Ikeda
Original Assignee
Canon Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Kk filed Critical Canon Kk
Application granted granted Critical
Publication of ATE145495T1 publication Critical patent/ATE145495T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AT91304830T 1990-05-31 1991-05-29 Verfahren zur verdrahtung einer halbleiterschaltung ATE145495T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP13961190 1990-05-31
JP14373190 1990-05-31

Publications (1)

Publication Number Publication Date
ATE145495T1 true ATE145495T1 (de) 1996-12-15

Family

ID=26472361

Family Applications (1)

Application Number Title Priority Date Filing Date
AT91304830T ATE145495T1 (de) 1990-05-31 1991-05-29 Verfahren zur verdrahtung einer halbleiterschaltung

Country Status (4)

Country Link
US (2) US5404046A (de)
EP (1) EP0459772B1 (de)
AT (1) ATE145495T1 (de)
DE (1) DE69123175T2 (de)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07211605A (ja) * 1994-01-14 1995-08-11 Hitachi Ltd 処理装置および処理方法
JPH08293523A (ja) * 1995-02-21 1996-11-05 Seiko Epson Corp 半導体装置およびその製造方法
JP2845176B2 (ja) * 1995-08-10 1999-01-13 日本電気株式会社 半導体装置
US6326318B1 (en) * 1995-09-14 2001-12-04 Sanyo Electric Co., Ltd. Process for producing semiconductor devices including an insulating layer with an impurity
US20010048147A1 (en) * 1995-09-14 2001-12-06 Hideki Mizuhara Semiconductor devices passivation film
US6268657B1 (en) 1995-09-14 2001-07-31 Sanyo Electric Co., Ltd. Semiconductor devices and an insulating layer with an impurity
JP3457123B2 (ja) * 1995-12-07 2003-10-14 株式会社リコー 半導体装置
US6825132B1 (en) 1996-02-29 2004-11-30 Sanyo Electric Co., Ltd. Manufacturing method of semiconductor device including an insulation film on a conductive layer
US5838176A (en) * 1996-07-11 1998-11-17 Foveonics, Inc. Correlated double sampling circuit
KR100383498B1 (ko) 1996-08-30 2003-08-19 산요 덴키 가부시키가이샤 반도체 장치 제조방법
US6288438B1 (en) 1996-09-06 2001-09-11 Sanyo Electric Co., Ltd. Semiconductor device including insulation film and fabrication method thereof
US5861647A (en) * 1996-10-02 1999-01-19 National Semiconductor Corporation VLSI capacitors and high Q VLSI inductors using metal-filled via plugs
US5847442A (en) * 1996-11-12 1998-12-08 Lucent Technologies Inc. Structure for read-only-memory
US6136686A (en) * 1997-07-18 2000-10-24 International Business Machines Corporation Fabrication of interconnects with two different thicknesses
JP3529989B2 (ja) * 1997-09-12 2004-05-24 株式会社東芝 成膜方法及び半導体装置の製造方法
JPH1197525A (ja) * 1997-09-19 1999-04-09 Hitachi Ltd 半導体装置およびその製造方法
JP2975934B2 (ja) 1997-09-26 1999-11-10 三洋電機株式会社 半導体装置の製造方法及び半導体装置
US6690084B1 (en) 1997-09-26 2004-02-10 Sanyo Electric Co., Ltd. Semiconductor device including insulation film and fabrication method thereof
US6332835B1 (en) 1997-11-20 2001-12-25 Canon Kabushiki Kaisha Polishing apparatus with transfer arm for moving polished object without drying it
JPH11154701A (ja) * 1997-11-21 1999-06-08 Mitsubishi Electric Corp 半導体装置
US6081032A (en) * 1998-02-13 2000-06-27 Texas Instruments - Acer Incorporated Dual damascene multi-level metallization and interconnection structure
US6316801B1 (en) * 1998-03-04 2001-11-13 Nec Corporation Semiconductor device having capacitive element structure and multilevel interconnection structure and method of fabricating the same
JP3109478B2 (ja) * 1998-05-27 2000-11-13 日本電気株式会社 半導体装置
US6794283B2 (en) 1998-05-29 2004-09-21 Sanyo Electric Co., Ltd. Semiconductor device and fabrication method thereof
GB2346009B (en) 1999-01-13 2002-03-20 Lucent Technologies Inc Define via in dual damascene process
US7335965B2 (en) * 1999-08-25 2008-02-26 Micron Technology, Inc. Packaging of electronic chips with air-bridge structures
SE521704C2 (sv) * 1999-10-29 2003-11-25 Ericsson Telefon Ab L M Förfarande för att anordna koppling mellan olika skikt i ett kretskort samt kretskort
US6890847B1 (en) * 2000-02-22 2005-05-10 Micron Technology, Inc. Polynorbornene foam insulation for integrated circuits
JP3759367B2 (ja) * 2000-02-29 2006-03-22 沖電気工業株式会社 半導体装置およびその製造方法
US7271489B2 (en) * 2003-10-15 2007-09-18 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US6887753B2 (en) * 2001-02-28 2005-05-03 Micron Technology, Inc. Methods of forming semiconductor circuitry, and semiconductor circuit constructions
US6917110B2 (en) * 2001-12-07 2005-07-12 Sanyo Electric Co., Ltd. Semiconductor device comprising an interconnect structure with a modified low dielectric insulation layer
JP3975099B2 (ja) * 2002-03-26 2007-09-12 富士通株式会社 半導体装置の製造方法
US6878620B2 (en) * 2002-11-12 2005-04-12 Applied Materials, Inc. Side wall passivation films for damascene cu/low k electronic devices
US20080070017A1 (en) * 2005-02-10 2008-03-20 Naoki Yoshii Layered Thin Film Structure, Layered Thin Film Forming Method, Film Forming System and Storage Medium
JP4836730B2 (ja) * 2006-09-26 2011-12-14 株式会社東芝 半導体装置、およびその製造方法
JP2010267673A (ja) * 2009-05-12 2010-11-25 Renesas Electronics Corp 半導体装置の設計方法
US8378490B2 (en) 2011-03-15 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor apparatus including a metal alloy between a first contact and a second contact

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6043656B2 (ja) * 1979-06-06 1985-09-30 株式会社東芝 半導体装置の製造方法
US4403217A (en) * 1981-06-18 1983-09-06 General Electric Company Multiplexed varistor-controlled liquid crystal display
FR2512239A1 (fr) * 1981-08-25 1983-03-04 Thomson Csf Dispositif de visualisation a commande electrique
JPS58158916A (ja) * 1982-03-16 1983-09-21 Fujitsu Ltd 半導体装置の製造方法
JPS59117226A (ja) * 1982-12-24 1984-07-06 Hitachi Tokyo Electronics Co Ltd ボンデイング装置
JPS59117236A (ja) * 1982-12-24 1984-07-06 Hitachi Ltd 半導体装置
US4951601A (en) * 1986-12-19 1990-08-28 Applied Materials, Inc. Multi-chamber integrated process system
US4960732A (en) * 1987-02-19 1990-10-02 Advanced Micro Devices, Inc. Contact plug and interconnect employing a barrier lining and a backfilled conductor material
DE3815569A1 (de) * 1987-05-07 1988-12-29 Intel Corp Verfahren zum selektiven abscheiden eines leitenden materials bei der herstellung integrierter schaltungen
US4988423A (en) * 1987-06-19 1991-01-29 Matsushita Electric Industrial Co., Ltd. Method for fabricating interconnection structure
US5055423A (en) * 1987-12-28 1991-10-08 Texas Instruments Incorporated Planarized selective tungsten metallization system
JP2811004B2 (ja) * 1988-05-23 1998-10-15 日本電信電話株式会社 金属薄膜成長方法および装置
JPH02106968A (ja) * 1988-10-17 1990-04-19 Hitachi Ltd 半導体集積回路装置及びその形成方法
US4980034A (en) * 1989-04-04 1990-12-25 Massachusetts Institute Of Technology High-density, multi-level interconnects, flex circuits, and tape for TAB
EP0420594B1 (de) * 1989-09-26 1996-04-17 Canon Kabushiki Kaisha Verfahren zur Herstellung von einer abgeschiedenen Metallschicht, die Aluminium als Hauptkomponent enthält, mit Anwendung von Alkalimetallaluminiumhydride
US5141897A (en) * 1990-03-23 1992-08-25 At&T Bell Laboratories Method of making integrated circuit interconnection

Also Published As

Publication number Publication date
EP0459772A2 (de) 1991-12-04
EP0459772A3 (en) 1992-06-03
DE69123175T2 (de) 1997-04-03
DE69123175D1 (de) 1997-01-02
US6245661B1 (en) 2001-06-12
EP0459772B1 (de) 1996-11-20
US5404046A (en) 1995-04-04

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties