ATE125629T1 - Busschnittstellenschaltung für digitalen datenprozessor. - Google Patents

Busschnittstellenschaltung für digitalen datenprozessor.

Info

Publication number
ATE125629T1
ATE125629T1 AT87402076T AT87402076T ATE125629T1 AT E125629 T1 ATE125629 T1 AT E125629T1 AT 87402076 T AT87402076 T AT 87402076T AT 87402076 T AT87402076 T AT 87402076T AT E125629 T1 ATE125629 T1 AT E125629T1
Authority
AT
Austria
Prior art keywords
interface circuit
processor
bus interface
controlling
information
Prior art date
Application number
AT87402076T
Other languages
English (en)
Inventor
Paul I Rubinfeld
Anil K Jain
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of ATE125629T1 publication Critical patent/ATE125629T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Communication Control (AREA)
  • Microcomputers (AREA)
  • Communication Cables (AREA)
  • Non-Insulated Conductors (AREA)
AT87402076T 1987-02-24 1987-09-17 Busschnittstellenschaltung für digitalen datenprozessor. ATE125629T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/017,647 US4831520A (en) 1987-02-24 1987-02-24 Bus interface circuit for digital data processor

Publications (1)

Publication Number Publication Date
ATE125629T1 true ATE125629T1 (de) 1995-08-15

Family

ID=21783770

Family Applications (1)

Application Number Title Priority Date Filing Date
AT87402076T ATE125629T1 (de) 1987-02-24 1987-09-17 Busschnittstellenschaltung für digitalen datenprozessor.

Country Status (12)

Country Link
US (1) US4831520A (de)
EP (1) EP0283628B1 (de)
JP (1) JP2547424B2 (de)
KR (1) KR920004402B1 (de)
CN (1) CN1011356B (de)
AT (1) ATE125629T1 (de)
AU (1) AU589815B2 (de)
BR (1) BR8800537A (de)
CA (1) CA1287924C (de)
DE (1) DE3751426T2 (de)
IN (1) IN171632B (de)
MX (1) MX162024A (de)

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AU625293B2 (en) * 1988-12-09 1992-07-09 Tandem Computers Incorporated Synchronization of fault-tolerant computer system having multiple processors
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DE4326740C1 (de) * 1993-08-09 1994-10-13 Martin Kopp Architektur für eine Rechenanlage
US5721882A (en) * 1994-08-05 1998-02-24 Intel Corporation Method and apparatus for interfacing memory devices operating at different speeds to a computer system bus
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US6260126B1 (en) 1998-06-05 2001-07-10 International Busines Machines Corporation Data storage subsystem having apparatus for enabling concurrent housekeeping processing while an input/output data transfer occurs
AU1458501A (en) * 1999-11-05 2001-06-06 Analog Devices, Inc. Generic serial port architecture and system
US6961796B2 (en) * 2001-07-26 2005-11-01 Hewlett-Packard Development Company, L.P. Extendable bus interface
US7133972B2 (en) 2002-06-07 2006-11-07 Micron Technology, Inc. Memory hub with internal cache and/or memory access prediction
US7200024B2 (en) * 2002-08-02 2007-04-03 Micron Technology, Inc. System and method for optically interconnecting memory devices
US7117316B2 (en) * 2002-08-05 2006-10-03 Micron Technology, Inc. Memory hub and access method having internal row caching
US7149874B2 (en) * 2002-08-16 2006-12-12 Micron Technology, Inc. Memory hub bypass circuit and method
US7836252B2 (en) 2002-08-29 2010-11-16 Micron Technology, Inc. System and method for optimizing interconnections of memory devices in a multichip module
US7054971B2 (en) * 2002-08-29 2006-05-30 Seiko Epson Corporation Interface between a host and a slave device having a latency greater than the latency of the host
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US7245145B2 (en) * 2003-06-11 2007-07-17 Micron Technology, Inc. Memory module and method having improved signal routing topology
US7120727B2 (en) * 2003-06-19 2006-10-10 Micron Technology, Inc. Reconfigurable memory module and method
US7107415B2 (en) * 2003-06-20 2006-09-12 Micron Technology, Inc. Posted write buffers and methods of posting write requests in memory modules
US7428644B2 (en) * 2003-06-20 2008-09-23 Micron Technology, Inc. System and method for selective memory module power management
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US20050050237A1 (en) * 2003-08-28 2005-03-03 Jeddeloh Joseph M. Memory module and method having on-board data search capabilities and processor-based system using such memory modules
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US7788451B2 (en) * 2004-02-05 2010-08-31 Micron Technology, Inc. Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
US7412574B2 (en) * 2004-02-05 2008-08-12 Micron Technology, Inc. System and method for arbitration of memory responses in a hub-based memory system
US7257683B2 (en) * 2004-03-24 2007-08-14 Micron Technology, Inc. Memory arbitration system and method having an arbitration packet protocol
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US6980042B2 (en) * 2004-04-05 2005-12-27 Micron Technology, Inc. Delay line synchronizer apparatus and method
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CN100524267C (zh) * 2007-02-15 2009-08-05 威盛电子股份有限公司 数据处理系统及数据处理方法
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CN107978292A (zh) * 2017-12-31 2018-05-01 河南思维轨道交通技术研究院有限公司 一种ttl液晶接口到lvds接口的转换电路和转换方法
CN111813726B (zh) * 2020-07-10 2023-03-07 中科芯集成电路有限公司 控制信号从高速总线向低速总线的转换方法

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US4258417A (en) * 1978-10-23 1981-03-24 International Business Machines Corporation System for interfacing between main store memory and a central processor
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Also Published As

Publication number Publication date
IN171632B (de) 1992-11-28
CA1287924C (en) 1991-08-20
AU589815B2 (en) 1989-10-19
DE3751426D1 (de) 1995-08-31
EP0283628B1 (de) 1995-07-26
EP0283628A3 (en) 1990-05-16
CN1011356B (zh) 1991-01-23
DE3751426T2 (de) 1996-03-14
US4831520A (en) 1989-05-16
MX162024A (es) 1991-03-22
KR920004402B1 (ko) 1992-06-04
AU8003587A (en) 1988-08-25
BR8800537A (pt) 1988-09-27
JPS63208963A (ja) 1988-08-30
CN87107293A (zh) 1988-09-07
JP2547424B2 (ja) 1996-10-23
KR880010365A (ko) 1988-10-08
EP0283628A2 (de) 1988-09-28

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