ATE125629T1 - Busschnittstellenschaltung für digitalen datenprozessor. - Google Patents

Busschnittstellenschaltung für digitalen datenprozessor.

Info

Publication number
ATE125629T1
ATE125629T1 AT87402076T AT87402076T ATE125629T1 AT E125629 T1 ATE125629 T1 AT E125629T1 AT 87402076 T AT87402076 T AT 87402076T AT 87402076 T AT87402076 T AT 87402076T AT E125629 T1 ATE125629 T1 AT E125629T1
Authority
AT
Austria
Prior art keywords
interface circuit
processor
bus interface
controlling
information
Prior art date
Application number
AT87402076T
Other languages
English (en)
Inventor
Paul I Rubinfeld
Anil K Jain
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of ATE125629T1 publication Critical patent/ATE125629T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Communication Control (AREA)
  • Microcomputers (AREA)
  • Non-Insulated Conductors (AREA)
  • Communication Cables (AREA)
AT87402076T 1987-02-24 1987-09-17 Busschnittstellenschaltung für digitalen datenprozessor. ATE125629T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/017,647 US4831520A (en) 1987-02-24 1987-02-24 Bus interface circuit for digital data processor

Publications (1)

Publication Number Publication Date
ATE125629T1 true ATE125629T1 (de) 1995-08-15

Family

ID=21783770

Family Applications (1)

Application Number Title Priority Date Filing Date
AT87402076T ATE125629T1 (de) 1987-02-24 1987-09-17 Busschnittstellenschaltung für digitalen datenprozessor.

Country Status (12)

Country Link
US (1) US4831520A (de)
EP (1) EP0283628B1 (de)
JP (1) JP2547424B2 (de)
KR (1) KR920004402B1 (de)
CN (1) CN1011356B (de)
AT (1) ATE125629T1 (de)
AU (1) AU589815B2 (de)
BR (1) BR8800537A (de)
CA (1) CA1287924C (de)
DE (1) DE3751426T2 (de)
IN (1) IN171632B (de)
MX (1) MX162024A (de)

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US5230067A (en) * 1988-05-11 1993-07-20 Digital Equipment Corporation Bus control circuit for latching and maintaining data independently of timing event on the bus until new data is driven onto
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IT1227711B (it) * 1988-11-18 1991-05-06 Caluso Torino Sistema multiprocessore di elaborazione dati a risorse distribuite condivise e prevenzione di stallo.
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
AU625293B2 (en) * 1988-12-09 1992-07-09 Tandem Computers Incorporated Synchronization of fault-tolerant computer system having multiple processors
JPH0687232B2 (ja) * 1988-12-19 1994-11-02 三菱電機株式会社 データ処理装置
CA1325288C (en) * 1989-02-03 1993-12-14 Ricky C. Hetherington Method and apparatus for controlling the conversion of virtual to physical memory addresses in a digital computer system
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GB2238694A (en) * 1989-12-02 1991-06-05 Motorola Inc "data interface system "
US5295258A (en) * 1989-12-22 1994-03-15 Tandem Computers Incorporated Fault-tolerant computer system with online recovery and reintegration of redundant components
US5203004A (en) * 1990-01-08 1993-04-13 Tandem Computers Incorporated Multi-board system having electronic keying and preventing power to improperly connected plug-in board with improperly configured diode connections
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US5276852A (en) * 1990-10-01 1994-01-04 Digital Equipment Corporation Method and apparatus for controlling a processor bus used by multiple processor components during writeback cache transactions
US5255374A (en) * 1992-01-02 1993-10-19 International Business Machines Corporation Bus interface logic for computer system having dual bus architecture
US5353429A (en) * 1991-03-18 1994-10-04 Apple Computer, Inc. Cache memory systems that accesses main memory without wait states during cache misses, using a state machine and address latch in the memory controller
US5291609A (en) * 1991-06-13 1994-03-01 Sony Electronics Inc. Computer interface circuit
US5265216A (en) * 1991-06-28 1993-11-23 Digital Equipment Corporation High performance asynchronous bus interface
US5471638A (en) * 1991-10-04 1995-11-28 Bull Hn Inforamtion Systems Inc. Bus interface state machines with independent access to memory, processor and registers for concurrent processing of different types of requests
US5414827A (en) * 1991-12-19 1995-05-09 Opti, Inc. Automatic cache flush
US5388237A (en) * 1991-12-30 1995-02-07 Sun Microsystems, Inc. Method of and apparatus for interleaving multiple-channel DMA operations
CA2080210C (en) * 1992-01-02 1998-10-27 Nader Amini Bidirectional data storage facility for bus interface unit
AU662973B2 (en) * 1992-03-09 1995-09-21 Auspex Systems, Inc. High-performance non-volatile ram protected write cache accelerator system
DE4326740C1 (de) * 1993-08-09 1994-10-13 Martin Kopp Architektur für eine Rechenanlage
US5721882A (en) * 1994-08-05 1998-02-24 Intel Corporation Method and apparatus for interfacing memory devices operating at different speeds to a computer system bus
IES950209A2 (en) * 1995-03-24 1995-10-18 Lake Res Ltd Communication apparatus for communicating two microprocessors
US6260126B1 (en) 1998-06-05 2001-07-10 International Busines Machines Corporation Data storage subsystem having apparatus for enabling concurrent housekeeping processing while an input/output data transfer occurs
CN100353349C (zh) * 1999-11-05 2007-12-05 模拟装置公司 通讯处理器的总线结构和共享总线判优方法
US6961796B2 (en) * 2001-07-26 2005-11-01 Hewlett-Packard Development Company, L.P. Extendable bus interface
US7133972B2 (en) 2002-06-07 2006-11-07 Micron Technology, Inc. Memory hub with internal cache and/or memory access prediction
US7200024B2 (en) * 2002-08-02 2007-04-03 Micron Technology, Inc. System and method for optically interconnecting memory devices
US7117316B2 (en) * 2002-08-05 2006-10-03 Micron Technology, Inc. Memory hub and access method having internal row caching
US7149874B2 (en) * 2002-08-16 2006-12-12 Micron Technology, Inc. Memory hub bypass circuit and method
US7836252B2 (en) * 2002-08-29 2010-11-16 Micron Technology, Inc. System and method for optimizing interconnections of memory devices in a multichip module
US7054971B2 (en) * 2002-08-29 2006-05-30 Seiko Epson Corporation Interface between a host and a slave device having a latency greater than the latency of the host
US7102907B2 (en) * 2002-09-09 2006-09-05 Micron Technology, Inc. Wavelength division multiplexed memory module, memory system and method
US7245145B2 (en) * 2003-06-11 2007-07-17 Micron Technology, Inc. Memory module and method having improved signal routing topology
US7120727B2 (en) 2003-06-19 2006-10-10 Micron Technology, Inc. Reconfigurable memory module and method
US7260685B2 (en) * 2003-06-20 2007-08-21 Micron Technology, Inc. Memory hub and access method having internal prefetch buffers
US7428644B2 (en) * 2003-06-20 2008-09-23 Micron Technology, Inc. System and method for selective memory module power management
US7107415B2 (en) * 2003-06-20 2006-09-12 Micron Technology, Inc. Posted write buffers and methods of posting write requests in memory modules
US7133991B2 (en) 2003-08-20 2006-11-07 Micron Technology, Inc. Method and system for capturing and bypassing memory transactions in a hub-based memory system
US20050050237A1 (en) * 2003-08-28 2005-03-03 Jeddeloh Joseph M. Memory module and method having on-board data search capabilities and processor-based system using such memory modules
US7136958B2 (en) 2003-08-28 2006-11-14 Micron Technology, Inc. Multiple processor system and method including multiple memory hub modules
US7120743B2 (en) * 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US7234070B2 (en) 2003-10-27 2007-06-19 Micron Technology, Inc. System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding
US7788451B2 (en) * 2004-02-05 2010-08-31 Micron Technology, Inc. Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
US7412574B2 (en) * 2004-02-05 2008-08-12 Micron Technology, Inc. System and method for arbitration of memory responses in a hub-based memory system
US7257683B2 (en) 2004-03-24 2007-08-14 Micron Technology, Inc. Memory arbitration system and method having an arbitration packet protocol
US7447240B2 (en) * 2004-03-29 2008-11-04 Micron Technology, Inc. Method and system for synchronizing communications links in a hub-based memory system
US7213082B2 (en) 2004-03-29 2007-05-01 Micron Technology, Inc. Memory hub and method for providing memory sequencing hints
US6980042B2 (en) * 2004-04-05 2005-12-27 Micron Technology, Inc. Delay line synchronizer apparatus and method
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KR101160566B1 (ko) * 2004-11-25 2012-06-28 텔레콤 이탈리아 소시에떼 퍼 아찌오니 이동 통신장비용 결합 ｉｃ 카드 및 무선 트랜시버 모듈
CN100524267C (zh) * 2007-02-15 2009-08-05 威盛电子股份有限公司 数据处理系统及数据处理方法
US20080282072A1 (en) * 2007-05-08 2008-11-13 Leonard Todd E Executing Software Within Real-Time Hardware Constraints Using Functionally Programmable Branch Table
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US8161236B1 (en) 2008-04-23 2012-04-17 Netapp, Inc. Persistent reply cache integrated with file system
US8171227B1 (en) 2009-03-11 2012-05-01 Netapp, Inc. System and method for managing a flow based reply cache
CN111813726B (zh) * 2020-07-10 2023-03-07 中科芯集成电路有限公司 控制信号从高速总线向低速总线的转换方法

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US4258417A (en) * 1978-10-23 1981-03-24 International Business Machines Corporation System for interfacing between main store memory and a central processor
JPS5714922A (en) * 1980-07-02 1982-01-26 Hitachi Ltd Storage device
US4503535A (en) * 1982-06-30 1985-03-05 Intel Corporation Apparatus for recovery from failures in a multiprocessing system

Also Published As

Publication number Publication date
JPS63208963A (ja) 1988-08-30
BR8800537A (pt) 1988-09-27
AU8003587A (en) 1988-08-25
CN87107293A (zh) 1988-09-07
CA1287924C (en) 1991-08-20
US4831520A (en) 1989-05-16
DE3751426T2 (de) 1996-03-14
KR880010365A (ko) 1988-10-08
IN171632B (de) 1992-11-28
KR920004402B1 (ko) 1992-06-04
DE3751426D1 (de) 1995-08-31
EP0283628A3 (en) 1990-05-16
AU589815B2 (en) 1989-10-19
EP0283628A2 (de) 1988-09-28
EP0283628B1 (de) 1995-07-26
MX162024A (es) 1991-03-22
JP2547424B2 (ja) 1996-10-23
CN1011356B (zh) 1991-01-23

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