IT1227711B - Sistema multiprocessore di elaborazione dati a risorse distribuite condivise e prevenzione di stallo. - Google Patents

Sistema multiprocessore di elaborazione dati a risorse distribuite condivise e prevenzione di stallo.

Info

Publication number
IT1227711B
IT1227711B IT8822651A IT2265188A IT1227711B IT 1227711 B IT1227711 B IT 1227711B IT 8822651 A IT8822651 A IT 8822651A IT 2265188 A IT2265188 A IT 2265188A IT 1227711 B IT1227711 B IT 1227711B
Authority
IT
Italy
Prior art keywords
data processing
multiprocessor system
distributed resources
stall prevention
shared distributed
Prior art date
Application number
IT8822651A
Other languages
English (en)
Other versions
IT8822651A0 (it
Inventor
Carlo Bagnoli
Guido Perrella
Tommaso Majo
Original Assignee
Caluso Torino
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Caluso Torino filed Critical Caluso Torino
Priority to IT8822651A priority Critical patent/IT1227711B/it
Publication of IT8822651A0 publication Critical patent/IT8822651A0/it
Priority to US07/424,378 priority patent/US5182808A/en
Priority to DE68928772T priority patent/DE68928772T2/de
Priority to EP89120432A priority patent/EP0369264B1/en
Priority to DE68915701T priority patent/DE68915701T2/de
Priority to EP93116232A priority patent/EP0581335B1/en
Application granted granted Critical
Publication of IT1227711B publication Critical patent/IT1227711B/it
Priority to US07/929,605 priority patent/US5253347A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Bus Control (AREA)
IT8822651A 1988-11-18 1988-11-18 Sistema multiprocessore di elaborazione dati a risorse distribuite condivise e prevenzione di stallo. IT1227711B (it)

Priority Applications (7)

Application Number Priority Date Filing Date Title
IT8822651A IT1227711B (it) 1988-11-18 1988-11-18 Sistema multiprocessore di elaborazione dati a risorse distribuite condivise e prevenzione di stallo.
US07/424,378 US5182808A (en) 1988-11-18 1989-10-20 Multiprocessor systems having distributed shared resources and deadlock prevention
DE68928772T DE68928772T2 (de) 1988-11-18 1989-11-04 Datenverarbeitungssystem mit sich um Zugriff auf verteilte Betriebsmittel bewerbenden Einheiten und mit auf den Status der verteilten Betriebsmittel reagierender Schiedsrichtereinheit
EP89120432A EP0369264B1 (en) 1988-11-18 1989-11-04 Multiprocessor system having distributed shared resources and deadlock prevention
DE68915701T DE68915701T2 (de) 1988-11-18 1989-11-04 Multiprozessorsystem mit verteilten gemeinsamen Betriebsmitteln und mit Verklemmungsverhinderung.
EP93116232A EP0581335B1 (en) 1988-11-18 1989-11-04 Data processing system having units competing for access to shared resources and arbitration unit responsive to the status of the shared resources
US07/929,605 US5253347A (en) 1988-11-18 1992-08-13 Centralized arbitration system using the status of target resources to selectively mask requests from master units

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8822651A IT1227711B (it) 1988-11-18 1988-11-18 Sistema multiprocessore di elaborazione dati a risorse distribuite condivise e prevenzione di stallo.

Publications (2)

Publication Number Publication Date
IT8822651A0 IT8822651A0 (it) 1988-11-18
IT1227711B true IT1227711B (it) 1991-05-06

Family

ID=11198868

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8822651A IT1227711B (it) 1988-11-18 1988-11-18 Sistema multiprocessore di elaborazione dati a risorse distribuite condivise e prevenzione di stallo.

Country Status (4)

Country Link
US (1) US5182808A (it)
EP (2) EP0369264B1 (it)
DE (2) DE68928772T2 (it)
IT (1) IT1227711B (it)

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US5301337A (en) * 1990-04-06 1994-04-05 Bolt Beranek And Newman Inc. Distributed resource management system using hashing operation to direct resource request from different processors to the processor controlling the requested resource
US5265257A (en) * 1990-06-22 1993-11-23 Digital Equipment Corporation Fast arbiter having easy scaling for large numbers of requesters, large numbers of resource types with multiple instances of each type, and selectable queuing disciplines
DE69230428T2 (de) * 1991-09-27 2000-08-03 Sun Microsystems, Inc. Verklemmungserkennung und Maskierung enthaltende Busarbitrierungsarchitektur
US5283870A (en) * 1991-10-04 1994-02-01 Bull Hn Information Systems Inc. Method and apparatus for avoiding processor deadly embrace in a multiprocessor system
US5426739A (en) * 1992-03-16 1995-06-20 Opti, Inc. Local bus - I/O Bus Computer Architecture
US5309568A (en) * 1992-03-16 1994-05-03 Opti, Inc. Local bus design
US5388224A (en) * 1992-04-24 1995-02-07 Digital Equipment Corporation Processor identification mechanism for a multiprocessor system
US5666511A (en) * 1992-10-08 1997-09-09 Fujitsu Limited Deadlock suppressing schemes in a raid system
US5500946A (en) * 1992-11-25 1996-03-19 Texas Instruments Incorporated Integrated dual bus controller
FR2708766B1 (fr) * 1993-08-03 1995-09-08 Bull Sa Procédé d'analyse d'interblocages dans un système d'exploitation.
US5708794A (en) * 1993-08-10 1998-01-13 Dell Usa, L.P. Multi-purpose usage of transaction backoff and bus architecture supporting same
WO1995020191A1 (en) * 1994-01-25 1995-07-27 Apple Computer, Inc. System and method for coordinating access to a bus
US5469435A (en) * 1994-01-25 1995-11-21 Apple Computer, Inc. Bus deadlock avoidance during master split-transactions
GB9405855D0 (en) * 1994-03-24 1994-05-11 Int Computers Ltd Computer system
US5586289A (en) * 1994-04-15 1996-12-17 David Sarnoff Research Center, Inc. Method and apparatus for accessing local storage within a parallel processing computer
US5878240A (en) * 1995-05-11 1999-03-02 Lucent Technologies, Inc. System and method for providing high speed memory access in a multiprocessor, multimemory environment
US5682537A (en) * 1995-08-31 1997-10-28 Unisys Corporation Object lock management system with improved local lock management and global deadlock detection in a parallel data processing system
KR0172310B1 (ko) * 1995-12-29 1999-03-30 김주용 교착 상태 방지를 위한 버스 유닛
US6006255A (en) * 1996-04-05 1999-12-21 International Business Machines Corporation Networked computer system and method of communicating using multiple request packet classes to prevent deadlock
US6055605A (en) * 1997-10-24 2000-04-25 Compaq Computer Corporation Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches
US6108737A (en) * 1997-10-24 2000-08-22 Compaq Computer Corporation Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system
US6085263A (en) * 1997-10-24 2000-07-04 Compaq Computer Corp. Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor
US6286090B1 (en) * 1998-05-26 2001-09-04 Compaq Computer Corporation Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches
US6792513B2 (en) 1999-12-29 2004-09-14 The Johns Hopkins University System, method, and computer program product for high speed backplane messaging
CA2322613A1 (en) 2000-10-06 2002-04-06 Ibm Canada Limited-Ibm Canada Limitee Latch mechanism for concurrent computing environments
US6795878B2 (en) * 2000-12-11 2004-09-21 International Business Machines Corporation Verifying cumulative ordering of memory instructions
GB0118294D0 (en) * 2001-07-27 2001-09-19 Ibm Method and system for deadlock detection and avoidance
US8473634B2 (en) * 2003-10-23 2013-06-25 Microsoft Corporation System and method for name resolution
US7185175B2 (en) * 2004-01-14 2007-02-27 International Business Machines Corporation Configurable bi-directional bus for communicating between autonomous units
US7694023B1 (en) 2006-01-24 2010-04-06 Lockheed Martin Corporation Routing a processor communication
WO2008154365A1 (en) * 2007-06-06 2008-12-18 Hunt Technologies, Llc. Dsp workload distribution in a power line carrier system
US8429353B2 (en) * 2008-05-20 2013-04-23 Oracle America, Inc. Distributed home-node hub

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US4038644A (en) * 1975-11-19 1977-07-26 Ncr Corporation Destination selection apparatus for a bus oriented computer system
NL7907179A (nl) * 1979-09-27 1981-03-31 Philips Nv Signaalprocessorinrichting met voorwaardelijke- -interrupteenheid en multiprocessorsysteem met deze signaalprocessorinrichtingen.
US4698746A (en) * 1983-05-25 1987-10-06 Ramtek Corporation Multiprocessor communication method and apparatus
US4763249A (en) * 1983-09-22 1988-08-09 Digital Equipment Corporation Bus device for use in a computer system having a synchronous bus
US4807109A (en) * 1983-11-25 1989-02-21 Intel Corporation High speed synchronous/asynchronous local bus and data transfer method
CA1239227A (en) * 1984-10-17 1988-07-12 Randy D. Pfeifer Method of and arrangement for ordering of multiprocessor operations in a multiprocessor system
EP0179936B1 (de) * 1984-10-31 1990-01-03 Ibm Deutschland Gmbh Verfahren und Einrichtung zur Steuerung einer Sammelleitung
US4760521A (en) * 1985-11-18 1988-07-26 White Consolidated Industries, Inc. Arbitration system using centralized and decentralized arbitrators to access local memories in a multi-processor controlled machine tool
US4779089A (en) * 1985-11-27 1988-10-18 Tektronix, Inc. Bus arbitration controller
CA1274918A (en) * 1985-11-27 1990-10-02 John G. Theus Bus arbitration controller
JPS62243058A (ja) * 1986-04-15 1987-10-23 Fanuc Ltd マルチプロセツサシステムの割込制御方法
IT1199745B (it) * 1986-12-12 1988-12-30 Honeywell Inf Systems Circuito arbitratore di accesso
US4831520A (en) * 1987-02-24 1989-05-16 Digital Equipment Corporation Bus interface circuit for digital data processor
US4866664A (en) * 1987-03-09 1989-09-12 Unisys Corporation Intercomputer communication control apparatus & method
US4858116A (en) * 1987-05-01 1989-08-15 Digital Equipment Corporation Method and apparatus for managing multiple lock indicators in a multiprocessor computer system
US4949239A (en) * 1987-05-01 1990-08-14 Digital Equipment Corporation System for implementing multiple lock indicators on synchronous pended bus in multiprocessor computer system
US4937777A (en) * 1987-10-07 1990-06-26 Allen-Bradley Company, Inc. Programmable controller with multiple task processors
US5038274A (en) * 1987-11-23 1991-08-06 Digital Equipment Corporation Interrupt servicing and command acknowledgement system using distributed arbitration apparatus and shared bus

Also Published As

Publication number Publication date
DE68915701T2 (de) 1994-09-15
EP0581335B1 (en) 1998-08-05
EP0581335A2 (en) 1994-02-02
US5182808A (en) 1993-01-26
DE68928772D1 (de) 1998-09-10
EP0369264A2 (en) 1990-05-23
DE68928772T2 (de) 1999-04-08
DE68915701D1 (de) 1994-07-07
EP0369264B1 (en) 1994-06-01
EP0369264A3 (en) 1990-07-18
EP0581335A3 (en) 1995-11-08
IT8822651A0 (it) 1988-11-18

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971129