IT1229667B - Sistema di elaborazione dati con arbitratore duale di accesso a bus di sistema. - Google Patents

Sistema di elaborazione dati con arbitratore duale di accesso a bus di sistema.

Info

Publication number
IT1229667B
IT1229667B IT8920267A IT2026789A IT1229667B IT 1229667 B IT1229667 B IT 1229667B IT 8920267 A IT8920267 A IT 8920267A IT 2026789 A IT2026789 A IT 2026789A IT 1229667 B IT1229667 B IT 1229667B
Authority
IT
Italy
Prior art keywords
arbitrator
dual
access
data processing
processing system
Prior art date
Application number
IT8920267A
Other languages
English (en)
Other versions
IT8920267A0 (it
Inventor
Fabio Bozzetti
Maurizio Grassi
Calogero Mantellina
Original Assignee
Bull Hn Information Syst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull Hn Information Syst filed Critical Bull Hn Information Syst
Priority to IT8920267A priority Critical patent/IT1229667B/it
Publication of IT8920267A0 publication Critical patent/IT8920267A0/it
Priority to US07/494,659 priority patent/US5038276A/en
Priority to DE69013394T priority patent/DE69013394T2/de
Priority to EP90107202A priority patent/EP0399204B1/en
Application granted granted Critical
Publication of IT1229667B publication Critical patent/IT1229667B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
IT8920267A 1989-04-24 1989-04-24 Sistema di elaborazione dati con arbitratore duale di accesso a bus di sistema. IT1229667B (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT8920267A IT1229667B (it) 1989-04-24 1989-04-24 Sistema di elaborazione dati con arbitratore duale di accesso a bus di sistema.
US07/494,659 US5038276A (en) 1989-04-24 1990-03-16 Data processing system having dual arbiter for controlling access to a system bus
DE69013394T DE69013394T2 (de) 1989-04-24 1990-04-17 Datenverarbeitungssystem mit Zweiwegarbiter zur Steuerung des Zugangs zu einem Systembus.
EP90107202A EP0399204B1 (en) 1989-04-24 1990-04-17 Data processing system having dual arbiter for controlling access to a system bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8920267A IT1229667B (it) 1989-04-24 1989-04-24 Sistema di elaborazione dati con arbitratore duale di accesso a bus di sistema.

Publications (2)

Publication Number Publication Date
IT8920267A0 IT8920267A0 (it) 1989-04-24
IT1229667B true IT1229667B (it) 1991-09-06

Family

ID=11165281

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8920267A IT1229667B (it) 1989-04-24 1989-04-24 Sistema di elaborazione dati con arbitratore duale di accesso a bus di sistema.

Country Status (4)

Country Link
US (1) US5038276A (it)
EP (1) EP0399204B1 (it)
DE (1) DE69013394T2 (it)
IT (1) IT1229667B (it)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5201055A (en) * 1989-11-03 1993-04-06 Compaq Computer Corporation Multiprocessing system includes interprocessor encoding and decoding logic used for communication between two cards through reduced addressing lines
US5461723A (en) * 1990-04-05 1995-10-24 Mit Technology Corp. Dual channel data block transfer bus
US5175847A (en) * 1990-09-20 1992-12-29 Logicon Incorporated Computer system capable of program execution recovery
US5339404A (en) * 1991-05-28 1994-08-16 International Business Machines Corporation Asynchronous TMR processing system
US5432911A (en) * 1991-07-15 1995-07-11 Matsushita Electric Works, Ltd. Controllers request access within one bus cycle causing hardware-wait to stall second controller when first controller is accessing and second controller is still requesting access
US5280591A (en) * 1991-07-22 1994-01-18 International Business Machines, Corporation Centralized backplane bus arbiter for multiprocessor systems
US5191656A (en) * 1991-08-29 1993-03-02 Digital Equipment Corporation Method and apparatus for shared use of a multiplexed address/data signal bus by multiple bus masters
EP0537899B1 (en) * 1991-09-27 1999-12-15 Sun Microsystems, Inc. Bus arbitration architecture incorporating deadlock detection and masking
US5341501A (en) * 1991-10-04 1994-08-23 Bull Hn Information Systems Inc. Processor bus access
US5274785A (en) * 1992-01-15 1993-12-28 Alcatel Network Systems, Inc. Round robin arbiter circuit apparatus
EP0600623B1 (en) * 1992-12-03 1998-01-21 Advanced Micro Devices, Inc. Servo loop control
EP0640929A3 (en) * 1993-08-30 1995-11-29 Advanced Micro Devices Inc Interprocessor communication via a post MEV.
US5706485A (en) * 1993-09-21 1998-01-06 Intel Corporation Method and apparatus for synchronizing clock signals in a multiple die circuit including a stop clock feature
US5875339A (en) * 1993-10-21 1999-02-23 Sun Microsystems, Inc. Asynchronous arbiter using multiple arbiter elements to enhance speed
US5713025A (en) * 1993-10-21 1998-01-27 Sun Microsystems, Inc. Asynchronous arbiter using multiple arbiter elements to enhance speed
JPH0816530A (ja) * 1994-07-04 1996-01-19 Kurieiteibu Design:Kk コプロセサシステムおよび補助演算機能付外部メモリ装置
US5809538A (en) * 1996-02-07 1998-09-15 General Instrument Corporation DRAM arbiter for video decoder
US5737544A (en) * 1996-04-08 1998-04-07 Vlsi Technology, Inc. Link system controller interface linking a PCI bus to multiple other buses
US6061361A (en) * 1997-06-19 2000-05-09 Advanced Micro Devices, Inc. Time multiplexed scheme for deadlock resolution in distributed arbitration
US6389497B1 (en) 1999-01-22 2002-05-14 Analog Devices, Inc. DRAM refresh monitoring and cycle accurate distributed bus arbitration in a multi-processing environment
EP1338956A1 (fr) 2002-02-20 2003-08-27 STMicroelectronics S.A. Dispositif électronique de traitement de données, en particulier processeur audio pour un décodeur audio/vidéo

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4229791A (en) * 1978-10-25 1980-10-21 Digital Equipment Corporation Distributed arbitration circuitry for data processing system
US4504906A (en) * 1982-11-30 1985-03-12 Anritsu Electric Company Limited Multiprocessor system
US4817066A (en) * 1985-10-09 1989-03-28 Hitachi, Ltd Transmitter/receiver for ultrasonic diagnostic system

Also Published As

Publication number Publication date
IT8920267A0 (it) 1989-04-24
DE69013394D1 (de) 1994-11-24
EP0399204B1 (en) 1994-10-19
DE69013394T2 (de) 1995-02-23
US5038276A (en) 1991-08-06
EP0399204A1 (en) 1990-11-28

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Effective date: 19990430