BR8307178A - Sistema de processamento de dados,circuito logico e processo de resolver prioridade distribuida para permitir que uma unidade de baixa prioridade resida em uma posicao de alta prioridade - Google Patents

Sistema de processamento de dados,circuito logico e processo de resolver prioridade distribuida para permitir que uma unidade de baixa prioridade resida em uma posicao de alta prioridade

Info

Publication number
BR8307178A
BR8307178A BR8307178A BR8307178A BR8307178A BR 8307178 A BR8307178 A BR 8307178A BR 8307178 A BR8307178 A BR 8307178A BR 8307178 A BR8307178 A BR 8307178A BR 8307178 A BR8307178 A BR 8307178A
Authority
BR
Brazil
Prior art keywords
priority
reside
allow
data processing
processing system
Prior art date
Application number
BR8307178A
Other languages
English (en)
Inventor
Daniel A Boudreau
Edward R Salas
James M Sandini
Original Assignee
Honeywell Inf Systems
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inf Systems filed Critical Honeywell Inf Systems
Publication of BR8307178A publication Critical patent/BR8307178A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/37—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/378—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a parallel poll method

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
BR8307178A 1982-12-27 1983-12-27 Sistema de processamento de dados,circuito logico e processo de resolver prioridade distribuida para permitir que uma unidade de baixa prioridade resida em uma posicao de alta prioridade BR8307178A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/453,406 US4559595A (en) 1982-12-27 1982-12-27 Distributed priority network logic for allowing a low priority unit to reside in a high priority position

Publications (1)

Publication Number Publication Date
BR8307178A true BR8307178A (pt) 1984-08-07

Family

ID=23800450

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8307178A BR8307178A (pt) 1982-12-27 1983-12-27 Sistema de processamento de dados,circuito logico e processo de resolver prioridade distribuida para permitir que uma unidade de baixa prioridade resida em uma posicao de alta prioridade

Country Status (9)

Country Link
US (1) US4559595A (pt)
EP (1) EP0114523B1 (pt)
JP (1) JPS59167727A (pt)
KR (1) KR900001120B1 (pt)
AU (1) AU570656B2 (pt)
BR (1) BR8307178A (pt)
CA (1) CA1205567A (pt)
FI (1) FI78994C (pt)
YU (1) YU45583B (pt)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1206331B (it) * 1983-10-25 1989-04-14 Honeywell Inf Systems Architettura di sistema di elaborazione dati.
GB2154400B (en) * 1984-02-17 1987-11-04 American Telephone & Telegraph Distributed arbitration circuitry
US4926419A (en) * 1985-03-15 1990-05-15 Wang Laboratories, Inc. Priority apparatus
US4719622A (en) * 1985-03-15 1988-01-12 Wang Laboratories, Inc. System bus means for inter-processor communication
US4724519A (en) * 1985-06-28 1988-02-09 Honeywell Information Systems Inc. Channel number priority assignment apparatus
JPH0619760B2 (ja) * 1986-04-23 1994-03-16 日本電気株式会社 情報処理装置
US5388228A (en) * 1987-09-30 1995-02-07 International Business Machines Corp. Computer system having dynamically programmable linear/fairness priority arbitration scheme
JPH0786853B2 (ja) * 1988-02-29 1995-09-20 株式会社ピーエフユー バス転送制御方式
JPH0276057A (ja) * 1988-09-13 1990-03-15 Toshiba Corp Ｉ／ｏリカバリ方式
JPH02117242A (ja) * 1988-10-27 1990-05-01 Toshiba Corp パケット通信装置のバス制御方式
US5077733A (en) * 1989-02-28 1991-12-31 Wang Laboratories, Inc. Priority apparatus having programmable node dwell time
JPH03142504A (ja) * 1989-10-30 1991-06-18 Toshiba Corp プログラマブルコントローラ
US5150466A (en) * 1990-10-05 1992-09-22 Bull Hn Information Systems Inc. Flexible distributed bus priority network
US5241629A (en) * 1990-10-05 1993-08-31 Bull Hn Information Systems Inc. Method and apparatus for a high performance round robin distributed bus priority network

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4030075A (en) * 1975-06-30 1977-06-14 Honeywell Information Systems, Inc. Data processing system having distributed priority network
US4096569A (en) * 1976-12-27 1978-06-20 Honeywell Information Systems Inc. Data processing system having distributed priority network with logic for deactivating information transfer requests
US4236203A (en) * 1978-01-05 1980-11-25 Honeywell Information Systems Inc. System providing multiple fetch bus cycle operation
IT1100916B (it) * 1978-11-06 1985-09-28 Honeywell Inf Systems Apparato per gestione di richieste di trasferimento dati in sistemi di elaborazione dati
US4385350A (en) * 1980-07-16 1983-05-24 Ford Aerospace & Communications Corporation Multiprocessor system having distributed priority resolution circuitry
FR2490434B1 (fr) * 1980-09-12 1988-03-18 Quinquis Jean Paul Dispositif de resolution des conflits d'acces et d'allocation d'une liaison de type bus interconnectant un ensemble de processeurs non hierarchises
IT1129371B (it) * 1980-11-06 1986-06-04 Cselt Centro Studi Lab Telecom Commutatore di messaggi a struttura distribuita su canale ad accesso casuale per colloquio a messaggi tra unita elaborative
FR2494010B1 (fr) * 1980-11-07 1986-09-19 Thomson Csf Mat Tel Dispositif d'arbitration decentralisee de plusieurs unites de traitement d'un systeme multiprocesseur
US4494113A (en) * 1981-03-13 1985-01-15 Hitachi, Ltd. Method and apparatus for self-control in distributed priority collision
US4451881A (en) * 1981-11-03 1984-05-29 International Business Machines Corp. Data processing system bus for multiple independent users
US4470112A (en) * 1982-01-07 1984-09-04 Bell Telephone Laboratories, Incorporated Circuitry for allocating access to a demand-shared bus
US4560985B1 (en) * 1982-05-07 1994-04-12 Digital Equipment Corp Dual-count, round-robin ditributed arbitration technique for serial buses

Also Published As

Publication number Publication date
FI78994C (fi) 1989-10-10
YU45583B (sh) 1992-07-20
AU570656B2 (en) 1988-03-24
EP0114523B1 (en) 1989-01-04
US4559595A (en) 1985-12-17
FI834657A0 (fi) 1983-12-19
FI78994B (fi) 1989-06-30
YU251583A (en) 1986-10-31
KR900001120B1 (ko) 1990-02-27
CA1205567A (en) 1986-06-03
JPS6237428B2 (pt) 1987-08-12
KR840007186A (ko) 1984-12-05
FI834657A (fi) 1984-06-28
EP0114523A3 (en) 1985-05-02
EP0114523A2 (en) 1984-08-01
AU2183383A (en) 1984-07-05
JPS59167727A (ja) 1984-09-21

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Legal Events

Date Code Title Description
MM Lapse due to non-payment of fees (art. 50)