GB1499742A - Interface adaptor circuits in combination with a processo - Google Patents

Abstract

1499742 Interface circuits MOTOROLA Inc 26 March 1975 [30 Oct 1974] 12727/75 Heading G4A An interface circuit (8M, Fig. 1, not shown) coupled to a first bidirectional data bus (6M), 13 (Fig. 2) and a second bidirectional peripheral data bus (7M); 29, 31, includes a control register (3M); 21, 24 coupled to the bus for defining under programme control the direction of data transfer on individual conductors of the peripheral data bus. Locations in direction registers 27, 34 control whether an associated peripheral data line is designated as in an input or an output. Control registers 21, 24 enable control of four peripheral control lines CA1, CA2, CB1, CB2 and bits 0-5 of the registers may be written or read by the processor when the proper chip select and register select signals are applied. Bit 0 enables processor interrupt signals IRQA, IRQB. Bit 1 determines the active transition of the interrupt signals CA1, CB1. Bits 3, 4 and 5 control the CA2, CB2 peripheral control lines. Bits 6 and 7 are interrupt flag bits set by transitions of signals on the lines CA1, CA2, CB1, CB2. As described the interface circuit is fabricated on a MOS chip.