JPS56155429A - Input-output control system - Google Patents
Input-output control systemInfo
- Publication number
- JPS56155429A JPS56155429A JP5783580A JP5783580A JPS56155429A JP S56155429 A JPS56155429 A JP S56155429A JP 5783580 A JP5783580 A JP 5783580A JP 5783580 A JP5783580 A JP 5783580A JP S56155429 A JPS56155429 A JP S56155429A
- Authority
- JP
- Japan
- Prior art keywords
- host computer
- speed
- memory device
- blocks
- addresses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To make the data transfer possible between a host computer and a high- speed external memory device by performing address conversion through operation by microprograms in an input-output control system. CONSTITUTION:Addresses from a host computer 1 are set in the input latch/buffer 4 of a control circuit 10, and the following address conversion is performed by the operation function of a microprocessor 3. The continuous block addresses from the host computer 1 are converted to the desultory addresses of a magnetic disc 2 as an external memory device. Hence, even when the read speed of the continuous blocks from the magnetic disc is higher than the speed of transferring the blocks to the host computer 1, reading out the desultory blocks from the disc 2 suffices in spite of sending the continuous block addresses from the host computer 1, and therefore the data transfer between the host computer 1 and the high-speed external memory device is made possible without any transfer skip.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5783580A JPS56155429A (en) | 1980-05-02 | 1980-05-02 | Input-output control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5783580A JPS56155429A (en) | 1980-05-02 | 1980-05-02 | Input-output control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56155429A true JPS56155429A (en) | 1981-12-01 |
Family
ID=13066999
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5783580A Pending JPS56155429A (en) | 1980-05-02 | 1980-05-02 | Input-output control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56155429A (en) |
-
1980
- 1980-05-02 JP JP5783580A patent/JPS56155429A/en active Pending
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