AR002790A1 - Dispositivo de celulas de memoria estacionaria grabables y borrables electricamente y procedimiento para su elaboracion. - Google Patents
Dispositivo de celulas de memoria estacionaria grabables y borrables electricamente y procedimiento para su elaboracion.Info
- Publication number
- AR002790A1 AR002790A1 ARP960103507A AR10350796A AR002790A1 AR 002790 A1 AR002790 A1 AR 002790A1 AR P960103507 A ARP960103507 A AR P960103507A AR 10350796 A AR10350796 A AR 10350796A AR 002790 A1 AR002790 A1 AR 002790A1
- Authority
- AR
- Argentina
- Prior art keywords
- recordable
- memory cells
- elaboration
- procedure
- electronic erasable
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
Abstract
Un dispositivo de células de memoria estacionaria grabables y borrables eléctricamente comprende células de memoria, siempre con un transistor MOS conuna puerta flotante (6). Los transistores MOS están dispuestos en hileras que corren paralelas.En él, las hileras contiguas siempre corren en formaalternada en el piso de los surcos longitudinales (4) y entre surcos longitudinales (4). Mediante pasos de proceso autoajustables se logra unrequerimiento de superficie por célula dememo ria de 2F exponente 2 (F:tamano estructural mínimo).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19525070A DE19525070C2 (de) | 1995-07-10 | 1995-07-10 | Elektrisch schreib- und löschbare Festwertspeicherzellenanordnung und Verfahren zu deren Herstellung |
Publications (1)
Publication Number | Publication Date |
---|---|
AR002790A1 true AR002790A1 (es) | 1998-04-29 |
Family
ID=7766442
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ARP960103507A AR002790A1 (es) | 1995-07-10 | 1996-07-10 | Dispositivo de celulas de memoria estacionaria grabables y borrables electricamente y procedimiento para su elaboracion. |
Country Status (8)
Country | Link |
---|---|
US (1) | US5943572A (es) |
EP (1) | EP0838092B1 (es) |
JP (1) | JPH11509044A (es) |
KR (1) | KR100417727B1 (es) |
AR (1) | AR002790A1 (es) |
DE (2) | DE19525070C2 (es) |
IN (1) | IN189362B (es) |
WO (1) | WO1997003469A1 (es) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19603810C1 (de) * | 1996-02-02 | 1997-08-28 | Siemens Ag | Speicherzellenanordnung und Verfahren zu deren Herstellung |
US6576547B2 (en) | 1998-03-05 | 2003-06-10 | Micron Technology, Inc. | Residue-free contact openings and methods for fabricating same |
DE19823733A1 (de) * | 1998-05-27 | 1999-12-02 | Siemens Ag | Halbleiter-Speicherzellenanordnung und entsprechendes Herstellungsverfahren |
DE19929233C1 (de) * | 1999-06-25 | 2001-02-01 | Siemens Ag | Speicherzellenanordnung mit auf einer Grabenseitenwand angeordnetem Floating-Gate und Herstellungsverfahren |
US6329687B1 (en) * | 2000-01-27 | 2001-12-11 | Advanced Micro Devices, Inc. | Two bit flash cell with two floating gate regions |
US6762092B2 (en) * | 2001-08-08 | 2004-07-13 | Sandisk Corporation | Scalable self-aligned dual floating gate memory cell array and methods of forming the array |
US6952033B2 (en) | 2002-03-20 | 2005-10-04 | Silicon Storage Technology, Inc. | Semiconductor memory array of floating gate memory cells with buried bit-line and raised source line |
US6917069B2 (en) * | 2001-10-17 | 2005-07-12 | Silicon Storage Technology, Inc. | Semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor |
US6720611B2 (en) * | 2002-01-28 | 2004-04-13 | Winbond Electronics Corporation | Fabrication method for flash memory |
US7411246B2 (en) | 2002-04-01 | 2008-08-12 | Silicon Storage Technology, Inc. | Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby |
US6952034B2 (en) * | 2002-04-05 | 2005-10-04 | Silicon Storage Technology, Inc. | Semiconductor memory array of floating gate memory cells with buried source line and floating gate |
US6891220B2 (en) * | 2002-04-05 | 2005-05-10 | Silicon Storage Technology, Inc. | Method of programming electrons onto a floating gate of a non-volatile memory cell |
US6894930B2 (en) | 2002-06-19 | 2005-05-17 | Sandisk Corporation | Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND |
EP1514309B1 (en) * | 2002-06-19 | 2013-11-27 | SanDisk Technologies Inc. | Deep wordline trench to shield cross coupling between adjacent cells of nand memory |
US6906379B2 (en) * | 2003-08-28 | 2005-06-14 | Silicon Storage Technology, Inc. | Semiconductor memory array of floating gate memory cells with buried floating gate |
TWI241017B (en) * | 2005-01-03 | 2005-10-01 | Powerchip Semiconductor Corp | Non-volatile memory device and manufacturing method and operating method thereof |
US7745285B2 (en) * | 2007-03-30 | 2010-06-29 | Sandisk Corporation | Methods of forming and operating NAND memory with side-tunneling |
US8148768B2 (en) * | 2008-11-26 | 2012-04-03 | Silicon Storage Technology, Inc. | Non-volatile memory cell with self aligned floating and erase gates, and method of making same |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0715953B2 (ja) * | 1985-08-09 | 1995-02-22 | 株式会社リコー | 書換え可能なメモリ装置とその製造方法 |
US5156989A (en) * | 1988-11-08 | 1992-10-20 | Siliconix, Incorporated | Complementary, isolated DMOS IC technology |
JPH05102436A (ja) * | 1991-10-09 | 1993-04-23 | Ricoh Co Ltd | 半導体メモリ装置とその製造方法 |
JPH07254651A (ja) * | 1994-03-16 | 1995-10-03 | Toshiba Corp | 半導体集積回路装置 |
US5376572A (en) * | 1994-05-06 | 1994-12-27 | United Microelectronics Corporation | Method of making an electrically erasable programmable memory device with improved erase and write operation |
-
1995
- 1995-07-10 DE DE19525070A patent/DE19525070C2/de not_active Expired - Fee Related
-
1996
- 1996-05-30 IN IN986CA1996 patent/IN189362B/en unknown
- 1996-07-02 KR KR10-1998-0700127A patent/KR100417727B1/ko not_active IP Right Cessation
- 1996-07-02 JP JP9505402A patent/JPH11509044A/ja not_active Ceased
- 1996-07-02 US US08/952,168 patent/US5943572A/en not_active Expired - Fee Related
- 1996-07-02 WO PCT/DE1996/001171 patent/WO1997003469A1/de active IP Right Grant
- 1996-07-02 DE DE59608152T patent/DE59608152D1/de not_active Expired - Fee Related
- 1996-07-02 EP EP96921877A patent/EP0838092B1/de not_active Expired - Lifetime
- 1996-07-10 AR ARP960103507A patent/AR002790A1/es unknown
Also Published As
Publication number | Publication date |
---|---|
US5943572A (en) | 1999-08-24 |
DE19525070A1 (de) | 1997-01-16 |
IN189362B (es) | 2003-02-15 |
KR100417727B1 (ko) | 2004-04-17 |
KR19990028827A (ko) | 1999-04-15 |
DE19525070C2 (de) | 2001-12-06 |
DE59608152D1 (de) | 2001-12-13 |
EP0838092A1 (de) | 1998-04-29 |
WO1997003469A1 (de) | 1997-01-30 |
JPH11509044A (ja) | 1999-08-03 |
EP0838092B1 (de) | 2001-11-07 |
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