WO2024045264A1 - 半导体结构及存储器 - Google Patents

半导体结构及存储器 Download PDF

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Publication number
WO2024045264A1
WO2024045264A1 PCT/CN2022/124056 CN2022124056W WO2024045264A1 WO 2024045264 A1 WO2024045264 A1 WO 2024045264A1 CN 2022124056 W CN2022124056 W CN 2022124056W WO 2024045264 A1 WO2024045264 A1 WO 2024045264A1
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Prior art keywords
sub
word line
line driver
gates
gate
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PCT/CN2022/124056
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English (en)
French (fr)
Inventor
吴奇龙
刘志拯
李宗翰
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长鑫科技集团股份有限公司
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Priority to EP22946032.4A priority Critical patent/EP4358137A1/en
Priority to US18/530,183 priority patent/US20240130119A1/en
Publication of WO2024045264A1 publication Critical patent/WO2024045264A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a memory.
  • word lines can be used as conductive lines to carry the gate voltage required to drive one or more transistors of a memory cell.
  • the transistor can operate in response to the potential state of the word line, so that the dynamic random access memory can write data to or read data from the memory cell through the transistor.
  • the line delay caused by such word lines can be considered as one of the most important delay factors limiting the operating speed of dynamic random access memories.
  • methods have been developed for dividing the long main word line (MWL, Main Wordline) into multiple sub-word lines (SWL, Sub Wordline) and for driving each sub-word line.
  • Sub Wordline Driver SWD, Sub Wordline Driver
  • embodiments of the present disclosure provide a semiconductor structure and a memory.
  • a semiconductor structure including: at least one sub-word line driver, the sub-word line driver including:
  • the main word line includes a plurality of interconnected first gates and a plurality of second gates; the plurality of first gates correspond to the plurality of first active regions;
  • the extending direction of the plurality of first gates in the main word line and/or the extending direction of at least part of the second gates in the main word line intersects with both the first direction and the second direction;
  • the first direction is parallel to the direction in which the first active area extends, and the second direction is parallel to the plane where the first active area is located and perpendicular to the first direction.
  • the plurality of first gates are physically connected and extend along a third direction, the plurality of first active regions are spaced apart along the third direction, and at least part of the second gates are physically connected.
  • the connections all extend along the fourth direction;
  • the angle range of the straight line of the third direction and the straight line of the second direction is: 0-45°; and/or the angle range of the straight line of the fourth direction and the straight line of the second direction is: :0-45°.
  • the plurality of first gates are physically connected and all extend along the third direction
  • the plurality of second gates are physically connected at one end of the plurality of first gates and all extend along the fourth direction.
  • the plurality of first gates are physically connected and all extend along the third direction
  • a part of the second gates are physically connected at one end of the plurality of first gates and all extend along the fourth direction
  • Another part of the second gates is physically connected to the other end of the plurality of first gates and extends along the fifth direction.
  • the angle range between the straight line in the fifth direction and the straight line in the second direction is :0-45°.
  • the angle between the straight line in the fourth direction and the straight line in the third direction is the first included angle
  • the straight line in the fifth direction and the straight line in the third direction are equal to each other.
  • the included angle between is the second included angle
  • the first included angle is equal to the second included angle.
  • the angle between the straight line in the third direction and the straight line in the second direction is 45°
  • the plurality of first active areas are arranged at intervals in a step-like manner
  • the straight line in the fourth direction The angle between the straight line of the second direction and the straight line of the fifth direction is 45°.
  • the angle between the straight line of the fifth direction and the straight line of the second direction is 45°.
  • the entire first gate extends along the third direction
  • the first gate includes a first part and a second part extending along the third direction and a third part connecting the first part and the second part.
  • the semiconductor structure includes N sub-word line drivers, and N is a positive integer greater than or equal to 1;
  • the physically connected first gates included in each of the N sub-word line drivers are parallel and both ends are flush;
  • the physically connected second gates included in each of the N sub-word line drivers are parallel and both ends are flush.
  • the sub-word line driver further includes: a plurality of third gates, the plurality of third gates are located at the second gates of two adjacent sub-word line drivers among the N sub-word line drivers. between extremes.
  • the N sub-word line drivers include a first sub-word line driver and a second sub-word line driver
  • the third gate electrode in the first sub-word line driver and the second sub-word line driver is located between the second gate electrode of the first sub-word line driver and the second gate electrode of the second sub-word line driver. .
  • the N sub-word line drivers include a first sub-word line driver, a second sub-word line driver, a third sub-word line driver and a fourth sub-word line driver arranged sequentially along the first direction;
  • the first gates of the N sub-word line drivers all extend along the first direction; the distance between the second gates of the first sub-word line driver and the second sub-word line driver is L1, and the The distance between the second gate electrodes of the second sub-word line driver and the third sub-word line driver is L2, and the distance between the second gate electrodes of the third sub-word line driver and the fourth sub-word line driver is L2.
  • the third gate of the N sub-word line driver is located between the second gate of the first sub-word line driver and the second gate of the second sub-word line driver, and the third sub-word line driver between the second gate and the second gate of the fourth sub-word line driver.
  • the first gate electrode of the second sub-word line driver and the first gate electrode of the third sub-word line driver have a common active region.
  • the N sub-word line drivers include a first sub-word line driver, a second sub-word line driver, a third sub-word line driver and a fourth sub-word line driver arranged sequentially along the first direction;
  • the first gate of the N sub-word line driver includes a first part and a second part extending along the first direction and a third part connecting the first part and the second part;
  • two adjacent sub-word lines A spacing between the first portions of the first gates between the drivers is a first distance or a second distance, and a spacing between the second portions of the first gates between two adjacent sub-word line drivers is the second distance or the first distance, the first distance is greater than the second distance;
  • the third gate electrode of the N sub-word line driver is located between the second gate electrodes of two adjacent first gate electrodes connected by a first distance in the N sub-word line driver.
  • the first active region is shared between two adjacent first gates with a second distance in the N sub-word line driver.
  • two third gates adjacent along the first direction are formed in a "C” shape or an "I" shape.
  • the transistor corresponding to the first gate includes a P-type transistor; the transistor corresponding to the second gate and the transistor corresponding to the third gate both include N-type transistors.
  • the sub-word line driver further includes at least one second active region corresponding to the plurality of second gates and the plurality of third gates;
  • the first active area is in a strip shape, and the second active area is in a grid shape.
  • the sub-word line driver structure further includes a plurality of conductive contacts; each of the conductive contacts is respectively connected to the source or drain in the first active region or the second active region.
  • a memory including: a semiconductor structure as described in the above embodiments of the present disclosure.
  • the extension direction of the first active region corresponding to the first gate is defined as the first direction, and the direction is parallel to the plane where the first active region is located and perpendicular to the first direction.
  • the extending direction of at least one of the connections formed by the plurality of first gates and at least part of the second gates in the main word line is set to be consistent with the first direction and the second direction.
  • the directions all intersect, so that the width of the main word line along the second direction (the projected size of the main word line in the first direction) can be reduced while keeping the channel length unchanged, and the occupied area of the sub-word line driver can be reduced. , thereby improving the integration of semiconductor structures.
  • Figure 1a is a partial circuit schematic diagram of a memory provided in an embodiment of the present disclosure
  • Figure 1b is a schematic layout diagram of a semiconductor structure with a sub-word line driver provided in an embodiment of the present disclosure
  • Figure 2 is a schematic circuit diagram of a sub-word line driver provided in an embodiment of the present disclosure
  • Figure 3a is a schematic diagram of a wiring method of a sub-word line driver provided in an embodiment of the present disclosure
  • Figure 3b is a schematic diagram of a wiring method of another sub-word line driver provided in an embodiment of the present disclosure
  • Figure 4a is a schematic diagram of a semiconductor structure in which a first conductor extends along a direction intersecting both the first direction and the second direction provided in an embodiment of the present disclosure
  • 4b is a schematic diagram of a semiconductor structure in which a second conductor extends along a direction intersecting both the first direction and the second direction provided in an embodiment of the present disclosure
  • Figure 4c is a schematic diagram of a semiconductor structure in which another second conductor extends along a direction intersecting both the first direction and the second direction provided in an embodiment of the present disclosure
  • Figure 4d is a schematic diagram of a semiconductor structure in which the first conductor and the second conductor both extend in directions intersecting with the first direction and the second direction provided in an embodiment of the present disclosure
  • Figure 5a is a schematic diagram of a semiconductor structure in which another first conductor extends along a direction intersecting both the first direction and the second direction provided in an embodiment of the present disclosure
  • Figure 5b is a schematic diagram of a semiconductor structure in which another second conductor extends along a direction intersecting both the first direction and the second direction provided in an embodiment of the present disclosure
  • Figure 5c is a schematic diagram of another semiconductor structure in which the first conductor and the second conductor both extend in a direction intersecting the first direction and the second direction provided in an embodiment of the present disclosure
  • Figure 5d is a schematic diagram of another semiconductor structure in which the first conductor and the second conductor both extend in directions intersecting with both the first direction and the second direction provided in the embodiment of the present disclosure
  • Figure 6a is a schematic diagram of a semiconductor structure in which the first conductor is in a "Z" shape provided in an embodiment of the present disclosure
  • Figure 6b is an enlarged schematic diagram of the first conductor in a "Z" shape shown in Figure 6a;
  • FIG. 7 is a schematic diagram of a semiconductor structure in which the first conductor and the second conductor both extend in directions intersecting with both the first direction and the second direction provided in an embodiment of the present disclosure.
  • spatially relative terms such as “on”, “over”, “over”, “on”, “upper”, etc. may be used herein to describe the figures The relationship of one element or feature to another element or feature.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • the term "substrate” refers to a material on which subsequent layers of material are added.
  • the substrate itself can be patterned.
  • the material added on top of the substrate can be patterned or can remain unpatterned.
  • the substrate may include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, arsenide, indium phosphide, and the like.
  • the substrate may be made of non-conductive material, such as glass, plastic or sapphire wafers.
  • the term "layer" refers to a portion of material that includes a region having a thickness.
  • a layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure.
  • a layer may be a region of a homogeneous or non-homogeneous continuous structure having a thickness less than the thickness of the continuous structure.
  • the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal plane at the top and bottom surfaces of the continuous structure. Layers may extend horizontally, vertically and/or along inclined surfaces.
  • a layer can include multiple sub-layers.
  • an interconnect layer may include one or more conductor and contact sublayers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sublayers.
  • the terms "first”, “second”, etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
  • the semiconductor structure involved in the embodiments of the present disclosure is at least a portion that will be used in subsequent processes to form a final device structure.
  • the final device may include a memory, and the memory includes but is not limited to a dynamic random access memory.
  • the following description only takes the dynamic random access memory as an example, and is not intended to limit the scope of the present disclosure.
  • each memory unit is mainly composed of a transistor and a capacitor controlled by the transistor, that is, the dynamic random access memory is a structure of 1 transistor (T, Transistor) and 1 capacitor (C, Capacitor) (1T1C) ; Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.
  • Figure 1a is a schematic diagram of a memory using a 1T1C architecture provided in an embodiment of the present disclosure; as shown in Figure 1a, the drain of the transistor T is electrically connected to the bit line (BL, Bit Line), and the source of the transistor T is connected to the capacitor C One of the electrode plates of the capacitor C is electrically connected, and the other electrode plate of the capacitor C can be connected to a reference voltage.
  • the reference voltage can be the ground voltage or other voltages.
  • the gate of the transistor T is connected to the word line (WL, Word Line); Applying a voltage through the word line WL controls the transistor T to be turned on or off, and the bit line BL is used to perform a read or write operation on the transistor T when the transistor T is turned on.
  • FIG. 1 b is a schematic layout diagram of a semiconductor structure with a sub-word line driver provided in an embodiment of the present disclosure.
  • the dynamic random access memory may include at least one memory cell array (CA, Cell Array), and a circuit for controlling the cell array including a main word line.
  • FIG. 1b shows a plurality of memory cell arrays CA.
  • Each memory cell array CA may include at least one bit line sense amplifier (BLSA, Bit Line Sense Amplifier) and at least one sub-word line driver SWD.
  • BLSA bit line sense amplifier
  • SWD sub-word line driver
  • Each memory cell array CA may include a plurality of memory cells in an array shape for storing data.
  • the memory cell array may include a plurality of sub-word lines SWL, each sub-word line may be coupled to a plurality of memory cells, the plurality of sub-word lines may be sequentially and successively arranged above the memory cell array, and the plurality of sub-word lines may be connected to a main word line MWL.
  • main word lines and main word line drivers have been developed to divide the long main word line into multiple sub-word lines and multiple sub-words for driving the corresponding sub-word lines.
  • line driver The sub-word line driver can selectively drive one or more sub-word lines in response to the main word line driving signal.
  • the main word line driving signal may represent a memory cell driving signal transmitted through the main word line.
  • the sub-word line driver can be divided into an even sub-word line driver circuit SWD(EVEN) provided along one side of the memory cell array and an odd sub-word line driver provided along the opposite side with respect to the memory cell array.
  • the even sub-word line driver circuit can drive one or more even sub-word lines
  • the odd sub-word line driver circuit can drive one or more odd sub-word lines. It can be understood that the even sub-word line driver circuit and the odd sub-word line driver circuit have basically similar structures.
  • the even sub-word line driver circuit and the odd sub-word line driver are collectively referred to as sub-word line drivers.
  • the sense amplifier can sense and amplify cell data of an associated memory cell array. Sense amplifiers may be arranged along the other side of the memory cell array.
  • FIG. 2 shows a circuit schematic diagram of a sub-word line driver in an embodiment.
  • the sub-word line driver is used to drive four sub-word lines, including four P-type metal-oxide-semiconductor (PMOS, P-Metal-Oxide-Semiconductor) transistors and four N-type metal-oxide - Semiconductor (NMOS, N-Metal-Oxide-Semiconductor) transistor, in other words, each sub-word line SWL includes a PMOS transistor and an NMOS transistor, wherein the PMOS transistor and the NMOS transistor can be formed as an inverter for Control the switching state of the target sub-word line.
  • PMOS P-type metal-oxide-semiconductor
  • NMOS N-Metal-Oxide-Semiconductor
  • the transistor controls the voltage VPP to turn on the sub-word line or controls the voltage VKK to turn off the sub-word line.
  • the sub-word line driver also includes a transistor connected to a group of PMOS transistors and NMOS transistors. This transistor is a noise suppression unit (Noise Killer). The noise suppression unit can be used to control other sub-word lines when a certain sub-word line is turned on.
  • the word line inputs the VKK voltage to turn it off to prevent it from affecting the signal that turns on the sub-word line.
  • the circuit of the sub-word line driver shown in FIG. 2 is only used as an example and is not used to limit the circuit structure of the sub-word line driver in the embodiment of the present disclosure.
  • FIG. 3a and 3b show two different wiring methods of sub-word line drivers. It should be noted that both FIG. 3a and FIG. 3b correspond to two (two groups) of main word line drivers shown in FIG. 2 .
  • the area corresponding to 301 is the area where the PMOS transistor is placed
  • the area corresponding to 302 is the area where the NMOS transistor is placed
  • the area corresponding to 303 is the area where the noise suppression unit is placed.
  • the area corresponding to 301 is the area where the PMOS transistor is placed.
  • the area corresponding to the gate electrode 302 is connected to the gate electrode of the NMOS transistor to form the main word line.
  • the area corresponding to 304 is the area where the gate of the PMOS transistor is placed
  • the area corresponding to 305 is the area where the gate of the NMOS transistor is placed
  • the area corresponding to 306 is the area where the noise suppression unit is placed
  • 304 corresponds to
  • the gate electrode of the PMOS transistor in the region is connected to the gate electrode of the NMOS transistor in the region 305 provided on both sides of the region 304 to form a main word line.
  • the area of all sub-word line drivers contained in the semiconductor structure can be equivalent to the product of the length along the X-axis direction and the length along the Y-axis direction, and the length along the Y-axis direction is determined by the pitch of the main word line (Pitch). ) and quantity (including the total number of actual word lines and dummy word lines), the installation space is limited. Therefore, the length of the sub-word line driver can be optimized by optimizing the length of the sub-word line driver along the X-axis direction. area effect. It should be noted that the length H shown in FIG. 3b can be understood as the length of the sub-word line driver along the Y-axis direction, and the width L can be understood as the length of the sub-word line driver along the X-axis direction.
  • placing the noise suppression unit in the middle of the gates of two transistors can reduce the width L of the sub-word line driver compared to placing it on one side of the transistor; at the same time, the width of the sub-word line driver Limited by the design of the gate.
  • embodiments of the present disclosure provide a semiconductor structure, including: at least one sub-word line driver, where the sub-word line driver includes:
  • the main word line includes a plurality of interconnected first gates and a plurality of second gates; the plurality of first gates correspond to the plurality of first active regions;
  • the extending direction of the plurality of first gates in the main word line and/or the extending direction of at least part of the second gates in the main word line intersects with both the first direction and the second direction;
  • the first direction is parallel to the direction in which the first active area extends, and the second direction is parallel to the plane where the first active area is located and perpendicular to the first direction.
  • the first direction is the extending direction of the plurality of first active regions; the extending direction of each first active region in the plurality of first active regions is the same and uniform. is the first direction; the second direction is perpendicular to the first direction and parallel to the plane where the first active area is located.
  • the first direction can be represented as the Y-axis direction in the drawings; the second direction can be represented as the X-axis direction in the drawings; and the plane where the first active area is located can be represented as XOY in the drawings. flat.
  • the direction that intersects both the first direction and the second direction does not refer to a fixed direction, but can be understood as being parallel to the plane where the first active area is located, and is neither parallel to the first direction nor Any direction parallel to the second direction.
  • first gates are physically connected to form a first conductive line; a plurality of second gates are physically connected to form a second conductive line. It should be noted that in this embodiment of the present disclosure, multiple first gates in each main word line may form one first conductive line; multiple second gates may form one or two second conductive lines. All first conductive lines and second conductive lines are connected to form a main word line.
  • each main word line may include a first conductor and a second conductor, one end of the first conductor is connected to one end of the second conductor, and the positions of the first conductor and the second conductor may be interchanged.
  • the arrangement of the first conductor and the second conductor may be: the extension direction of the first conductor intersects both the first direction and the second direction, and the extension direction of the second conductor is parallel to the second direction; or it may be: The extension direction of the first conductor is parallel to the second direction, and the extension direction of the second conductor intersects both the first direction and the second direction; or it can also be: the extension direction of the first conductor intersects both the first direction and the second direction, The extending direction of the second conductive wire also intersects both the first direction and the second direction.
  • each main word line may include a first conductor and two second conductors, and the two second conductors are respectively located on both sides of the first conductor; at this time, the first conductor and the second conductor are
  • the arrangement may be: the extension direction of the first conductor intersects both the first direction and the second direction, the extension direction of one of the two second conductors is parallel to the second direction, and the extension direction of the other second conductor is parallel to the second direction.
  • the extension directions can be intersecting or perpendicular.
  • the first gate electrode and the second gate electrode represent different transistor types, and the transistor types represented by the first gate electrode and the second gate electrode can be interchanged.
  • the transistor corresponding to the first gate may include a PMOS transistor; the transistor corresponding to the second gate may include an NMOS transistor; or, the transistor corresponding to the first gate may include an NMOS transistor; The transistor corresponding to the second gate may include a PMOS transistor.
  • Figures 4a to 4d show a variety of different wiring methods of sub-word line drivers.
  • the semiconductor structure may include at least one sub-word line driver, as shown in Figures 4a to 4d.
  • the semiconductor structure includes two sub-word line drivers.
  • the total length of the first conductor and the second conductor are set to be the same, and the direction that intersects both the first direction and the second direction is set to be the same as the first direction and the second direction.
  • the angle between the two directions is 45°, and when both the first conductor and the second conductor are extended along the second direction, the width L of the sub-word line driver in the X-axis direction in Figure 3b is used as a reference value.
  • the semiconductor structure 100 corresponding to FIG. 4a shows that the first conductor 401 extends in a direction that intersects both the first direction and the second direction, and the second conductor (402a, 402b) is parallel to the second direction.
  • the projected width of the first conductor 401 in the second direction is smaller than the width of the first conductor 401 in the second direction when the first conductor 401 is arranged along the second direction. According to calculations, the width of the sub-word line driver in the second direction in Figure 4a is reduced by 29.3% compared with the reference value.
  • the semiconductor structure 200 corresponding to FIG. 4b shows that the second conductive lines (402a, 402b) extend along a direction that intersects both the first direction and the second direction, and the first conductive line 401 is parallel to the second direction.
  • the projected width of the second conductor line (402a, 402b) in the second direction is smaller than the width of the second conductor line (402a, 402b) in the second direction when the second conductor line (402a, 402b) is arranged along the second direction. According to calculations, the width of the sub-word line driver in the second direction is reduced by 29.3% compared with the reference value.
  • the difference between the semiconductor structure 300 corresponding to Figure 4c and the semiconductor structure 200 shown in Figure 4b is that the shape of the first conductor 401 is different, and the extension directions of the two parts (402a, 402b) of the second conductor are different.
  • the width in the second direction is the same. According to calculations, the width of the sub-word line driver in the second direction is reduced by 29.3% compared with the reference value.
  • the semiconductor structure 400 corresponding to FIG. 4d shows that the first conductive line 401 and the second conductive line (402a, 402b) both extend along the direction intersecting the first direction and the second direction.
  • the widths of the first conductive line 401 and the second conductive line (402a, 402b) in the second direction are both reduced; according to calculations, the width of the sub-word line driver in the second direction is reduced by 58.6% compared to the reference value.
  • the width of the first conductive line and/or the second conductive line in the first direction is relatively increased.
  • the increased width is related to the angle between the first conductor or the second conductor and the second direction.
  • the sub-word line The driver area is reduced by 1-(2-2cos ⁇ )/4. For example, when the included angle ⁇ is 45°, the area of the sub-word line driver is reduced by 14.6%.
  • the extending direction of at least one of the connections formed by the plurality of first gates in the main word line and the connections formed by at least part of the second gates is set to be consistent with the first direction and the second direction.
  • the width of the main word line along the second direction can be reduced to varying degrees while keeping the channel length unchanged, thereby achieving the purpose of reducing the area of the sub-word line driver.
  • the preset angle is 45°.
  • the plurality of first gates are physically connected and extend along a third direction, the plurality of first active regions are spaced apart along the third direction, and at least part of the second gates Both physical connections extend along the fourth direction; the angle range between the straight line in the third direction and the straight line in the second direction is: 0-45°; and/or, the straight line in the fourth direction and the straight line in the second direction The angle range of the straight line in the second direction is: 0-45°.
  • the plurality of first gates are physically connected and extend along a third direction
  • the plurality of second gates are physically connected at one end of the plurality of first gates and extend along a third direction.
  • the fourth direction extends.
  • the plurality of first gates are physically connected and all extend along the third direction
  • a part of the second gates are physically connected at one end of the plurality of first gates and all extend along the third direction.
  • another part of the second gates is physically connected to the other end of the plurality of first gates and extends in a fifth direction.
  • the straight line in the fifth direction and the straight line in the second direction are The included angle range is: 0-45°.
  • the third direction is the extension direction of the first conductor, which is a direction that intersects both the first direction and the second direction;
  • the fourth direction and the fifth direction are both the extension directions of part of the second conductor, which are both the extension directions of the first conductor and the second conductor.
  • the angle range of the straight line of the third direction, the fourth direction and the fifth direction and the straight line of the second direction are all equal. Set to 0-45°.
  • the plurality of first active areas corresponding to the first conductive lines are arranged at intervals along the extension direction of the first conductive lines.
  • the semiconductor structure 500 includes a plurality of first active regions 403 and four main word lines 404, and each main word line 404 includes a first conductive line 401 and a second conductive line (402a, 402b). ;
  • the second conductors (402a, 402b) are respectively located on both sides of the first conductor 401.
  • Each first conductor 401 extends along the third direction (refer to the AP direction in Figure 5a), and the second conductors (402a, 402b) both extend along the third direction.
  • the fourth direction extends (here, the fourth direction is parallel to the X-axis direction in Figure 5a).
  • each main word line 404 includes a first conductor 401 and a second conductor (402a, 402b).
  • the second conductors (402a, 402b) are respectively located on the first conductor 401.
  • the first conductor 401 extends along the third direction (here, the third direction is parallel to the X-axis direction in Figure 5b)
  • a part of the second conductor 402a extends along the fourth direction (refer to the BP direction in Figure 5b)
  • the other A portion of the second wire 402b extends along the fifth direction (refer to the CP direction in FIG. 5b).
  • each main word line 404 includes a first conductor 401 and a second conductor (402a, 402b).
  • the second conductors (402a, 402b) are respectively located on the first conductor 401.
  • the first conductor 401 extends along the third direction (refer to the DP direction in Figure 5c)
  • a part of the second conductor 402a extends along the fourth direction (refer to the EP direction in Figure 5c)
  • the other part of the second conductor 402b extends along the fifth direction. (Refer to the PF direction in Figure 5c) extension.
  • each main word line 404 includes a first conductor 401 and a second conductor 402.
  • the second conductor 402 is only located on one side of the first conductor 401, and the first conductor 401 is located along The third direction (refer to the GP direction in Figure 5d) extends; the second wire 402 extends in the fourth direction (refer to the HP direction in Figure 5d).
  • the angle between the straight line of the fourth direction and the straight line of the third direction is a first included angle
  • the straight line of the fifth direction and the straight line of the third direction are The angle between the straight lines is the second angle
  • the first angle is equal to the second angle
  • the first included angle is ⁇ CPX
  • the second included angle is ⁇ BP(-X).
  • the first included angle is ⁇ DPE
  • the second included angle is ⁇ DPF.
  • the fourth direction and the fifth direction are parallel.
  • the first included angle is different from the second included angle.
  • the width of the two parts of the second conductor along the second direction is reduced to the same extent, and at the same time, the two parts of the second conductor (402a, 402b)
  • the degree of change in the length along the first direction is also the same, which will facilitate control of the overall size of the second gate.
  • the angle between the straight line in the third direction and the straight line in the second direction is 45°
  • the plurality of first active areas are arranged at intervals in a stepwise manner
  • the fourth direction The angle between the straight line and the straight line of the second direction is 45°
  • the angle between the straight line of the fifth direction and the straight line of the second direction is 45°.
  • the angle between the third direction and the X-axis direction is ⁇ DPO; the angle between the fourth direction and the X-axis direction is ⁇ EPX; the angle between the fifth direction and the X-axis direction is ⁇ OPF;
  • the width of the sub-word line driver in the second direction decreases to the greatest extent compared with the reference value.
  • the fourth direction and the fifth direction are parallel but not parallel to the third direction, compared with when the fourth direction is parallel to both the fifth direction and the third direction, the sub-word line driver in the first direction Length is smaller.
  • the entire first gate extends along the third direction; alternatively, the first gate includes a first portion and a second portion extending along the third direction and connects the first portion to the third direction. part three and part two.
  • the first conductor 401 formed by physical connection of multiple first gates is linear.
  • the first conductor 401 formed by physical connection of multiple first gates is in a "Z" shape or an inverse "Z" shape, as shown in FIG. 6a and FIG. 6b.
  • the first wire 401 includes a first portion 401a, a second portion 401b and a third portion 401c that are connected to each other.
  • the first portion 401a and the second portion 401b both extend along the third direction but do not overlap
  • the third part 401c is used to connect the first part 401a and the second part 401b, so that the first wire 401 has a "Z" shape or an inverted "Z” shape.
  • a plurality of "Z"-shaped first conductors 401 and inverse "Z"-shaped first conductors 401 in the semiconductor structure 900 are arranged at intervals.
  • FIG. 6b is an enlarged schematic diagram of the “Z”-shaped first conductor 401 in FIG. 6a.
  • the semiconductor structure includes N sub-word line drivers, where N is a positive integer greater than or equal to 1; each of the N sub-word line drivers includes the physically connected first One gate is parallel and both ends are flush; the physically connected second gate included in each of the N sub-word line drivers is parallel and both ends are flush.
  • each sub-word line driver 404 includes four first gates and four corresponding first active regions 403.
  • the four first active regions 403 are spaced apart along the third direction.
  • the four second gates are parallel to each other and both ends are substantially flush.
  • the sub-word line driver further includes: a plurality of third gates, the third gates are located between the second gates of two adjacent sub-word line drivers in the N sub-word line drivers. between.
  • a third gate 405 is also disposed between two adjacent sub-word line drivers 404 in the semiconductor structure 500.
  • the third gate 405 is located between two adjacent second sub-word line drivers 404 arranged side by side along the first direction. between the gate electrodes (second conductor 402a).
  • the sub-word line driver further includes at least one second active region corresponding to the plurality of second gates and the plurality of third gates; the first active region The shape is a long strip, and the second active area is in a grid shape.
  • the first active region 403 may be in a long strip shape, and the first gate electrode corresponds to the first active region 403 one-to-one.
  • the second active region 406 can be formed in a strip shape or in a grid shape; when the second active region 406 is formed in a strip shape, a second gate electrode and a second active region are formed one by one. Correspondingly; when the second active region is formed in a grid shape, multiple second gates correspond to one second active region.
  • the third gate located between two adjacent second gates also corresponds to the second active region, that is, a plurality of second gates
  • the second active region 406 is shared with multiple third gates; in this way, the arrangement of the active region can be reduced, thereby reducing the area of the sub-word line driver.
  • the third gate and its corresponding transistor can be used to form a noise suppression unit.
  • FIG. 7 when the second conductor 402 is located between the two first conductors 401 , the third gate 405 is located at two adjacent second gates along the Y direction (ie, adjacent second conductors 402 ). between.
  • FIG. 7 only shows one arrangement method of the second conductor line 402 and the first conductor line 401. In other embodiments, other types of arrangement methods are possible, which will not be described again here.
  • two third gates adjacent along the first direction are formed in a "C" shape or an "I" shape.
  • the third gate 405 located between two adjacent second wires (402a or 402b) along the Y-axis direction is in the shape of a "C" Type or reverse "C" shape.
  • the N sub-word line drivers include a first sub-word line driver and a second sub-word line driver arranged sequentially along the first direction; the first sub-word line driver and the second sub-word line driver The third gates in the line drivers are located between the second gates of the first sub-word line driver and the second gates of the second sub-word line drivers.
  • the semiconductor structure 100 shown in FIG. 4a includes two sub-word line drivers, namely a first sub-word line driver 100-1 and a second sub-word line driver 100-2 that are adjacently arranged along the Y-axis direction.
  • the third gate 405 is located between the second gate 402a of the first sub-word line driver 100-1 and the second gate 402a of the second sub-word line driver 100-2; between the second gate 402b of the word line driver 100-1 and the second gate 402b of the second sub-word line driver 100-2.
  • the N sub-word line drivers include a first sub-word line driver, a second sub-word line driver, a third sub-word line driver and a fourth sub-word line driver arranged sequentially along the first direction.
  • the first gates of the N sub-word line drivers all extend along the first direction; the distance between the second gates of the first sub-word line driver and the second sub-word line driver is L1, and the second gate
  • the third gate of the N sub-word line driver is located between the second gate of the first sub-word line driver and the second gate of the second sub-word line driver, and between the second gate of the third sub-word line driver and the second gate of the fourth sub-word line driver.
  • the semiconductor structure 600 shown in FIG. 5b includes four sub-word line drivers arranged sequentially along the first direction, namely a first sub-word line driver, a second sub-word line driver, and a third sub-word line driver. driver and a fourth sub-word line driver, wherein the distance between the second gate electrode 402a-1 of the first sub-word line driver and the second gate electrode 402a-2 of the second sub-word line driver is L1, and the distance between the second gate electrode 402a-1 of the first sub-word line driver and the second sub-word line driver is L1.
  • the distance between the second gate 402a-2 of the word line driver and the second gate 402a-3 of the third sub-word line driver is L2, and the second gate 402a-3 of the third sub-word line driver and the fourth
  • the third gate 405 is disposed between the second gate 402a-1 of the first sub-word line driver and the second gate of the second sub-word line driver. 402a-2; and/or, the third gate 405 is disposed between the second gate 402a-3 of the third sub-word line driver and the second gate 402a-4 of the fourth sub-word line driver.
  • the first gate electrode of the second sub-word line driver and the first gate electrode of the third sub-word line driver have a common active region.
  • the semiconductor structure 600 shown in FIG. 5b includes a plurality of first gate electrodes 401-1 of second sub-word line drivers and a plurality of first gate electrodes 401-2 of third sub-word line drivers, as well as a plurality of first gate electrodes 401-1. Active area 403.
  • the distance between the first gate 401-1 of the second sub-word line driver and the first gate 401-2 of the third sub-word line driver adjacent along the Y-axis direction is L2.
  • the second sub-word The distance between the second gate 402a-2 of the line driver and the second gate 402a-3 of the third sub-word line driver is also L2.
  • the distance L1 between the second sub-word line drivers is relatively small. Therefore, the first gate electrode 401-1 of the second sub-word line driver and the first gate electrode 401 of the third sub-word line driver can be connected. -2 share a first active area 403. In this way, the total area of the sub-word line driver can also be reduced.
  • the N sub-word line drivers include a first sub-word line driver, a second sub-word line driver, a third sub-word line driver and a fourth sub-word line driver arranged sequentially along the first direction.
  • the first gate of the N sub-word line driver includes a first part and a second part extending along the first direction and a third part connecting the first part and the second part; two adjacent sub-word lines
  • the spacing between the first portion of the first gate between the word line drivers is a first distance or a second distance
  • the spacing between the second portion of the first gate between two adjacent sub-word line drivers is the first distance. distance or the second distance, the first distance is greater than the second distance
  • the third gate of the N sub-word line driver is located in two phases of the N sub-word line driver that are spaced a first distance apart. between the second gate connected to the first gate.
  • a plurality of first gates corresponding to the first sub-word line driver 400-1 are physically connected, and the first conductive line formed includes a first part 401a and a second part 401b and connects the first part and Section 3 of Part II 401c.
  • a plurality of first gates corresponding to the second sub-word line driver 400-2 are physically connected, and the formed first conductive line includes a first part 401a, a second part 401b, and a third part 401c connecting the first part and the second part.
  • a plurality of first gates corresponding to the third sub-word line driver 400-3 are physically connected, and the first conductive line formed includes a first part 401a and a second part 401b, and a third part 401c connecting the first part and the second part.
  • a plurality of first gates corresponding to the fourth sub-word line driver 400-4 are physically connected, and the formed first conductive line 401 includes a first part 401a and a second part 401b, and a third part 401c connecting the first part and the second part. .
  • the distance between the first part 401a corresponding to the first sub-word line driver 400-1 and the first part 401a corresponding to the second sub-word line driver 400-2 is R1; the second part corresponding to the first sub-word line driver 400-1 The distance between 401b and the second portion 401b corresponding to the second sub-word line driver 400-2 is R2.
  • the distance between the first part 401a corresponding to the second sub-word line driver 400-2 and the first part 401a corresponding to the third sub-word line driver 400-3 is R2; the second part corresponding to the second sub-word line driver 400-2 The distance between 401b and the second portion 401b corresponding to the third sub-word line driver 400-3 is R1.
  • the distance between the first part 401a corresponding to the third sub-word line driver 400-3 and the first part 401a corresponding to the fourth sub-word line driver 400-4 is R1; the second part corresponding to the third sub-word line driver 400-3 The distance between 401b and the second portion 401b corresponding to the fourth sub-word line driver 400-4 is R2.
  • the first distance R1 is greater than the second distance R2; based on this, a plurality of third gates corresponding to the N sub-word line drivers are arranged on two adjacent gates along the Y-axis direction that are apart from the first distance R1. Between a first gate connected to a second gate. In other words, the third gate is located between two adjacent second gates, and the distance between the two first gates respectively connected to the two adjacent second gates is the first distance R1.
  • the first active region is shared between two adjacent first gates spaced a second distance apart in the N sub-word line driver.
  • the transistor corresponding to the first gate includes a PMOS transistor; the transistor corresponding to the second gate and the transistor corresponding to the third gate both include NMOS transistors.
  • the first gate, the second gate, and the third gate correspond to the sub-word line driver circuit shown in FIG. 2, there may be the above-mentioned corresponding relationship between PMOS and NMOS.
  • the transistor corresponding to the first gate includes an NMOS transistor; the transistor corresponding to the second gate and the transistor corresponding to the third gate both include PMOS transistors.
  • the corresponding circuit connection relationship can be adjusted according to the functional requirements of the circuit.
  • the sub-word line driver further includes a plurality of conductive contacts; each of the conductive contacts is respectively connected to the source or the drain in the first active region or the second active region.
  • each sub-word line driver is also provided with a plurality of conductive contacts 407; the conductive contacts 407 can be located on at least one side of the first gate electrode and in contact with the first active area 403.
  • the source or drain is connected; the conductive contact 407 can also be located on at least one side of the second gate and connected to the source or drain in the second active region 406 .
  • the extension direction of the first active region corresponding to the first gate is defined as the first direction, and the direction parallel to the plane where the first active region is located and perpendicular to the first direction is defined.
  • the extending direction of at least one of the connections formed by the plurality of first gates in the main word line and the connections formed by at least part of the second gates is set to be consistent with the first direction and the second direction. All intersect, so that the width of the main word line along the second direction (the projected size of the main word line in the first direction) can be reduced while keeping the channel length unchanged, and the occupied area of the sub-word line driver can be reduced. This further improves memory integration.
  • An embodiment of the present disclosure also provides a memory, including: a semiconductor structure as described in the above embodiments of the present disclosure.
  • the layout of the relevant structures in the memory may refer to the related description of FIG. 1b mentioned above.
  • the extension direction of the first active region corresponding to the first gate is defined as the first direction, and the direction is parallel to the plane where the first active region is located and perpendicular to the first direction.
  • the extending direction of at least one of the connections formed by the plurality of first gates and at least part of the second gates in the main word line is set to be consistent with the first direction and the second direction.
  • the directions all intersect, so that the width of the main word line along the second direction (the projected size of the main word line in the first direction) can be reduced while keeping the channel length unchanged, and the occupied area of the sub-word line driver can be reduced. , thereby improving the integration of semiconductor structures.

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Abstract

本公开实施例公开了一种半导体结构及存储器，其中，所述半导体结构包括：至少一个子字线驱动器，所述子字线驱动器包括：多个第一有源区；以及主字线，包括互连的多个第一栅极和多个第二栅极；所述多个第一栅极对应所述多个第一有源区；其中，所述主字线中的所述多个第一栅极的延伸方向和/或所述主字线中的至少部分第二栅极的延伸方向与第一方向和第二方向均相交；所述第一方向平行于所述第一有源区延伸的方向，所述第二方向与所述第一有源区所在的平面平行且垂直于所述第一方向。

Description

半导体结构及存储器
相关申请的交叉引用
本公开基于申请号为202211070194.3、申请日为2022年09月02日、发明名称为“半导体结构及存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，具体地，涉及一种半导体结构及存储器。
背景技术
半导体结构，例如动态随机存取存储器(DRAM，Dynamic Random Access Memory)，字线可以用作传送驱动存储单元的一个或更多个晶体管所需的栅极电压的导电线。其中，晶体管可以响应于字线的电位状态而操作，使得动态随机存取存储器可以通过晶体管将数据写入存储单元或从存储单元读取数据。
随着芯片尺寸和芯片的存储器容量的增加，由此类字线引起的线延迟可以被认为是限制动态随机存取存储器的操作速度的最重要的延迟因素之一。为了使此类字线的线延迟最小化，已经开发了用于将长的主字线(MWL，Main Wordline)划分为多条子字线(SWL，Sub Wordline)以及用于驱动每条子字线的子字线驱动器(SWD，Sub Wordline Driver)。
发明内容
有鉴于此，本公开实施例提出一种半导体结构及存储器。
根据本公开的一个方面，提供了一种半导体结构，包括：至少一个子字线驱动器，所述子字线驱动器包括：
多个第一有源区；以及
主字线，包括互连的多个第一栅极和多个第二栅极；所述多个第一栅极对应所述多个第一有源区；
其中，所述主字线中的所述多个第一栅极的延伸方向和/或所述主字线中的至少部分第二栅极的延伸方向与第一方向和第二方向均相交；所述第一方向平行于所述第一有源区延伸的方向，所述第二方向与所述第一有源区所在的平面平行且垂直于所述第一方向。
上述方案中，所述多个第一栅极物理连接且均沿第三方向延伸，所述多个第一有源区沿所述第三方向间隔排布，至少部分所述第二栅极物理连接均沿第四方向延伸；
所述第三方向所在直线与所述第二方向所在直线的夹角范围为：0-45°；和/或，所述第四方向所在直线与所述第二方向所在直线的夹角范围为：0-45°。
上述方案中，所述多个第一栅极物理连接且均沿第三方向延伸，所述多个第二栅极物理连接在所述多个第一栅极的一端且均沿第四方向延伸。
上述方案中，所述多个第一栅极物理连接且均沿第三方向延伸，一部分所述第二栅极物理连接在所述多个第一栅极的一端且均沿第四方向延伸，另一部分所述第二栅极物理连接在所述多个第一栅极的另一端且均沿第五方向延伸，所述第五方向所在直线与所述第二方向所在直线的夹角范围为：0-45°。
上述方案中，所述第四方向所在的直线与所述第三方向所在的直线之间的夹角为第一夹角，所述第五方向所在的直线与所述第三方向所在的直线之间的夹角为第二夹角，所述第一夹角与所述第二夹角相等。
上述方案中，所述第三方向所在直线与所述第二方向所在直线的夹角为45°，所述多个第一有源区呈步进状间隔排布，所述第四方向所在直线与所述第二方向所在直线的夹角为45°，所述第五方向所在直线与所述第二方向所在直线的夹角为45°。
上述方案中，所述第一栅极整体均沿所述第三方向延伸；
或者，
所述第一栅极包括沿所述第三方向延伸的第一部分和第二部分以及连接所述第一部分和第二部分的第三部分。
上述方案中，所述半导体结构包括N个子字线驱动器，所述N为大于等于1的正整数；
所述N个子字线驱动器中每一子字线驱动器包含的物理连接的所述第一栅极均平行且两端均齐平；
所述N个子字线驱动器中每一子字线驱动器包含的物理连接的所述第二栅极均平行且两端均齐平。
上述方案中，所述子字线驱动器还包括：多个第三栅极，所述多个第三栅极均位于所述N个子字线驱动器中相邻的两个子字线驱动器的第二栅极之间。
上述方案中，所述N个子字线驱动器包括第一子字线驱动器和第二子字线驱动器；
所述第一子字线驱动器和第二子字线驱动器中的第三栅极均位于所述第一子字线驱动器的第二栅极和第二子字线驱动器的第二栅极之间。
上述方案中，所述N个子字线驱动器包括沿所述第一方向依次设置的第一子字线驱动器、第二子字线驱动器、第三子字线驱动器和第四子字线驱动器；所述N个子字线驱动器的第一栅极整体均沿所述第一方向延伸；所述第一子字线驱动器和第二子字线驱动器的第二栅极之间的距离为L1，所述第二子字线驱动器和第三子字线驱动器的第二栅极之间的距离为L2，所述第三子字线驱动器和第四子字线驱动器的第二栅极之间的距离为L3；其中，L1＝L3，L1＞L2；
所述N个子字线驱动器的第三栅极位于所述第一子字线驱动器的第二栅极和第二子字线驱动器的第二栅极之间，以及所述第三子字线驱动器的第二栅极和第四子字线驱动器的第二栅极之间。
上述方案中，所述第二子字线驱动器的第一栅极与所述第三子字线驱动器的第一栅极存在共用的有源区。
上述方案中，所述N个子字线驱动器包括沿所述第一方向依次设置的第一子字线驱动器、第二子字线驱动器、第三子字线驱动器和第四子字线驱动器；所述N个子字线驱动器的所述第一栅极包括沿所述第一方向延伸的第一部分和第二部分以及连接所述第一部分和第二部分的第三部分；相邻的两个子字线驱动器之间的第一栅极的第一部分的间距为第一距离或第二距离，相邻的两个子字线驱动器之间的第一栅极的第二部分的间距为所述第二距离或所述第一距离，所述第一距离大于所述第二距离；
所述N个子字线驱动器的第三栅极位于所述N个子字线驱动器中间距为第一距离的两个相邻第一栅极连接的第二栅极之间。
上述方案中，所述N个子字线驱动器中间距为第二距离的两个相邻第一栅极之间存在共用的所述第一有源区。
上述方案中，沿所述第一方向相邻的两个第三栅极形成为“C”字型或“I”字型。
上述方案中，所述第一栅极对应的晶体管包括P型晶体管；所述第二栅极对应的晶体管、所述第三栅极对应的晶体管均包括N型晶体管。
上述方案中，所述子字线驱动器还包括至少一个第二有源区，与所述多个第二栅极、所述多个第三栅极对应；
所述第一有源区的形状为长条形，所述第二有源区的形状为网格状。
上述方案中，所述子字线驱动器结构还包括多个导电接触；每个所述导电接触分别与所述第一有源区或所述第二有源区中的源极或漏极连接。
根据本公开的一个方面，提供了一种存储器，包括：如本公开上述实施例中所述的半导体结构。
本公开实施例提供的半导体结构中，将第一栅极对应的第一有源区的延伸方向定义为第一方向，将与第一有源区所在的平面平行且垂直于第一方向的方向定义为第二方向，通过将主字线中的多个第一栅极形成的连线、至少部分第二栅极形成的连线中至少之一的延伸方向设置为与第一方向和第二方向均相交，从而可以在保持沟道长度不变的前提下，使得主字线沿第二方向的宽度(主字线在第一方向上的投影尺寸)缩小，子字线驱动器的占用面积缩小，进而提高半导体结构的集成度。
附图说明
图1a为本公开实施例中提供的一种存储器的局部电路示意图；
图1b为本公开实施例中提供的一种具有子字线驱动器的半导体结构的布局示意图；
图2为本公开实施例中提供的一种子字线驱动器的电路示意图；
图3a为本公开实施例中提供的一种子字线驱动器的布线方式示意图；
图3b为本公开实施例中提供的另一种子字线驱动器的布线方式示意图；
图4a为本公开实施例中提供的一种第一导线沿与第一方向和第二方向均相交的方向延伸的半导体结构示意图；
图4b为本公开实施例中提供的一种第二导线沿与第一方向和第二方向均相交的方向延伸的半导体结构示意图；
图4c为本公开实施例中提供的另一种第二导线沿与第一方向和第二方向均相交的方向延伸的半导体结构示意图；
图4d为本公开实施例中提供的一种第一导线、第二导线均沿与第一方向和第二方向均相交的方向延伸的半导体结构示意图；
图5a为本公开实施例中提供的另一种第一导线沿与第一方向和第二方向均相交的方向延伸的半导体结构示意图；
图5b为本公开实施例中提供的另一种第二导线沿与第一方向和第二方向均相交的方向延伸的半导体结构示意图；
图5c为本公开实施例中提供的另一种第一导线、第二导线均沿与第一方向和第二方向均相交的方向延伸的半导体结构示意图；
图5d为本公开实施例中提供的又一种第一导线、第二导线均沿与第一方向和第二方向均相交的方向延伸的半导体结构示意图；
图6a为本公开实施例中提供的一种第一导线呈“Z”字型的半导体结构的示意图；
图6b为图6a示出的呈“Z”字型的第一导线的放大示意图；
图7为本公开实施例中提供的再一种第一导线、第二导线均沿与第一方向和第二方向均相交的方向延伸的半导体结构示意图。
在上述附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
具体实施方式
为使本公开实施例的技术方案和优点更加清楚，下面将结合附图和实施例对本公开的技术方案进一步详细阐述。虽然附图中显示了本公开的示例性实施方法，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了能够更透彻的理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下列段落中参照附图以举例方式更具体的描述本公开。根据下面说明和权利要求书，本公开的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本公开实施例的目的。
可以理解的是，本公开中的“在……上”、“在……之上”和“在……上方”的含义应当以最宽方式被解读，以使得“在……上”不仅表示其“在”某物“上”且其间没有居间特征或层(即直接在某物上)的含义，而且还包括在某物“上”且其间有居间特征或层的含义。
此外，为了便于描述，可以在本文中使用诸如“在……上”、“在……之上”、“在……上方”、“上”、“上部”等的空间相对术语来描述如图所示的一个元件或特征与另一个元件或特征的关系。除了在附图中所描绘的取向之外，空间相对术语旨在涵盖设备在使用或操作中的不同取向。装置可以以其它方式定向(旋转90度或处于其它取向)并且同样可以相应地解释本文使用的空间相对描述词。
在本公开实施例中，术语“衬底”是指在其上添加后续材料层的材料。衬底本身可以被图案化。被添加在衬底顶部的材料可以被图案化或者可以保持未被图案化。此外，衬底可以包括多种半导体材料，例如硅、硅锗、锗、砷化嫁、磷化锢等。替代地，衬底可以由非导电材料制成，例如玻璃、塑料或蓝宝石晶圆。
在本公开实施例中，术语“层”是指包括具有厚度的区域的材料部分。层可以在下方或上方结构的整体之上延伸，或者可以具有小于下方或上方结构范围的范围。此外，层可以是厚度小于连续结构厚度的均质或非均质连续结构的区域。例如，层可位于连续结构的顶表面和底表面之间，或者层可在连续结构顶表面和底表面处的任何水平面对之间。层可以水平、垂直和/或沿倾斜表面延伸。层可以包括多个子层。例如，互连层可包括一个或多个导体和接触子层(其中形成互连线和/或过孔触点)、以及一个或多个电介质子层。
在本公开实施例中，术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
本公开实施例涉及的半导体结构是将被用于后续制程以形成最终的器件结构的至少一部分。这里，所述最终的器件可以包括存储器，所述存储器包括但不限于动态随机存取存储器，以下仅以动态随机存取存储器为例进行说明，并不用来限制本公开的范围。
随着动态随机存取存储器技术的发展，存储单元阵列的架构由8F 2到6F 2再到4F 2；然而，不论8F 2还是4F 2的阵列架构，动态随机存取存储器均由多个存储单元构成，每一个存储单元主要是由一个晶体管与一个由晶体管所操控的电容构成，即动态随机存取存储器是1个晶体管(T，Transistor)和1个电容(C，Capacitor)(1T1C)的架构；其 主要的作用原理是利用电容内存储电荷的多少来代表一个二进制比特是l还是0。
图1a为本公开实施例中提供的一种存储器采用1T1C架构的示意图；如图1a所示，晶体管T的漏极与位线(BL，Bit Line)电连接，晶体管T的源极与电容C的其中一个电极板电连接，电容C的另外一个电极板可以连接参考电压，所述参考电压可以是地电压也可以是其他电压，晶体管T的栅极与字线(WL，Word Line)连接；通过字线WL施加电压控制晶体管T导通或截止，位线BL用于在晶体管T导通时，对所述晶体管T执行读取或写入操作。
图1b为本公开实施例中提供的一种具有子字线驱动器的半导体结构的布局示意图。如图1b所示，动态随机存取存储器可以包括至少一个存储单元阵列(CA，Cell Array)、以及用于控制包括主字线的单元阵列的电路。图1b示出了多个存储单元阵列CA，每个存储单元阵列CA可以包括至少一个位线感测放大器(BLSA，Bit Line Sense Amplifier)和至少一个子字线驱动器SWD。
每个存储单元阵列CA可以包括呈阵列形状的、用于存储数据的多个存储单元。存储单元阵列可以包括多条子字线SWL，每条子字线可以联接到多个存储单元，多条子字线可以顺序地并且相继地布置在存储单元阵列上方，并且多条子字线可以连接到一条主字线MWL。
前已述及，为了使主字线的线延迟最小化，已经开发了将长的主字线及主字线驱动器划分为多条子字线以及用于驱动相应的每条子字线的多个子字线驱动器。子字线驱动器可以响应于主字线驱动信号而选择性地驱动一条或更多条子字线。在这种情况下，主字线驱动信号可以表示通过主字线传输的存储单元驱动信号。
在图1b中，子字线驱动器可以分为沿着存储单元阵列的一侧设置的偶数子字线驱动器电路SWD(EVEN)和沿着相对于存储单元阵列的相对侧设置的奇数子字线驱动器电路SWD(ODD)。偶数子字线驱动器电路可以驱动一条或更多条偶数子字线，奇数子字线驱动器电路可以驱动一条或更多条奇数子字线。可以理解的是，偶数子字线驱动器电路和奇数子字线驱动器电路具有基本相似的结构，以下将偶数子字线驱动器电路和奇数子字线驱动器统称为子字线驱动器。感测放大器可以感测并放大相关联的存储单元阵列的单元数据。感测放大器可以沿着存储单元阵列的另一侧布置。
图2示出了一实施例中子字线驱动器的电路示意图。如图2所示，子字线驱动器用于驱动四个子字线，包括四个P型金属-氧化物-半导体(PMOS，P-Metal-Oxide-Semiconductor)晶体管和四个N型金属-氧化物-半导体(NMOS，N-Metal-Oxide-Semiconductor)晶体管，换言之，每一子字线SWL包括一个PMOS晶体管和一个NMOS晶体管，其中，所述PMOS晶体管和NMOS晶体管可以形成为反相器以用于控制目标子字线的开关状态。示例性的，晶体管控制电压VPP使子字线开启或控制电压VKK使子字线关闭。需要说明的是，四个PMOS晶体管和四个NMOS晶体管对应的栅极相互连接，形成主字线MWL。子字线驱动器还包括与一组PMOS晶体管和NMOS晶体管均连接的晶体管，该晶体管为噪声抑制单元(Noise Killer)，所述噪声抑制单元可以用于在某一个子字线开启时，对其他子字线输入VKK电压使其关闭，防止影响开启子字线的信号。需要说明的是，图2中示出的子字线驱动器的电路仅用于作为示例，不用于限定本公开实施例中的子字线驱动器的电路结构。
为了降低延迟时间，缩小子字线驱动器所占的面积，子字线驱动器中各元件的布线方式尤为重要。图3a、图3b中示出了两种不同的子字线驱动器的布线方式。需要说明的是，图3a、图3b均对应两个(两组)图2中示出的主字线驱动器。如图3a所示，301对应的区域为PMOS晶体管放置的区域，302对应的区域为NMOS晶体管放置的区域，303对应的区域为噪声抑制单元放置的区域，其中，301对应的区域中PMOS 晶体管的栅极与302对应的区域为NMOS晶体管的栅极连接形成主字线。
如图3b所示，304对应的区域为PMOS晶体管的栅极放置的区域，305对应的区域为NMOS晶体管的栅极放置的区域，306对应的区域为噪声抑制单元放置的区域，其中，304对应的区域中PMOS晶体管的栅极与设置在304区域两侧的305对应的区域为NMOS晶体管的栅极连接形成主字线。
实际应用中，半导体结构包含的所有子字线驱动器的面积可以等效为沿X轴方向的长度和沿Y轴方向的长度乘积，而沿Y轴方向的长度是由主字线的间距(Pitch)和数量(包括起实际作用的字线和虚设的字线的总数量)决定的，设置空间有限，因此，可以通过优化子字线驱动器沿X轴方向的长度来达到优化子字线驱动器的面积的效果。需要说明的是，图3b中示出的长度H可以理解为子字线驱动器沿Y轴方向的长度，宽度L可以理解为子字线驱动器沿X轴方向的长度。
从图3a、图3b可以看出，噪声抑制单元放置在两个晶体管栅极的中间相较于放置在晶体管的一侧，可以缩小子字线驱动器的宽度L；同时，子字线驱动器的宽度受栅极的设计限制。
鉴于此，本公开实施例提供了一种半导体结构，包括：至少一个子字线驱动器，所述子字线驱动器包括：
多个第一有源区；以及
主字线，包括互连的多个第一栅极和多个第二栅极；所述多个第一栅极对应所述多个第一有源区；
其中，所述主字线中的所述多个第一栅极的延伸方向和/或所述主字线中的至少部分第二栅极的延伸方向与第一方向和第二方向均相交；所述第一方向平行于所述第一有源区延伸的方向，所述第二方向与所述第一有源区所在的平面平行且垂直于所述第一方向。
这里及下文中，为了便于描述本公开实施例，第一方向为多个第一有源区的延伸方向；多个第一有源区中的每一个第一有源区的延伸方向相同且均为第一方向；第二方向为与第一方向垂直且与第一有源区所在的平面平行的方向。在一些具体示例中，第一方向可以表示为附图中的Y轴方向；第二方向可以表示为附图中的X轴方向；第一有源区所在的平面可以表示为附图中的XOY平面。
这里，与第一方向和第二方向均相交的方向并不指代某一个固定的方向，而是可以理解为平行于所第一有源区所在的平面，且不与第一方向平行也不与第二方向平行的任意一个方向。
这里，多个第一栅极物理连接形成第一导线；多个第二栅极物理连接形成第二导线。需要说明的是，本公开实施例中，每一个主字线中多个第一栅极可以形成一个第一导线；多个第二栅极可以形成一个或两个第二导线。所有的第一导线和第二导线连接，形成主字线。
在一些具体实施例中，每一主字线可以包括一个第一导线和一个第二导线，第一导线的一端和第二导线的一端相连，第一导线和第二导线的位置可以互换。此时，第一导线和第二导线的排布方式可以是：第一导线的延伸方向与第一方向和第二方向均相交，第二导线的延伸方向与第二方向平行；也可以是：第一导线的延伸方向与第二方向平行，第二导线的延伸方向与第一方向和第二方向均相交；还可以是：第一导线的延伸方向与第一方向和第二方向均相交，第二导线的延伸方向也与第一方向和第二方向均相交。
在一些具体实施例中，每一主字线可以包括一个第一导线和两个第二导线，两个第二导线分别位于第一导线的两侧；此时，第一导线和第二导线的排布方式可以 是：第一导线的延伸方向与第一方向和第二方向均相交，两个第二导线中的一个第二导线的延伸方向与第二方向平行，另一个第二导线的延伸方向与第一方向和第二方向均相交；也可以是：第一导线的延伸方向与第二方向平行，两个第二导线的延伸方向与第一方向和第二方向均相交；还可以是：第一导线的延伸方向与第一方向和第二方向均相交，两个第二导线的延伸方向与第一方向和第二方向均相交；这里，第一导线的延伸方向与第二导线的延伸方向可以相交也可以垂直。
需要说明的是，第一栅极和第二栅极表征的晶体管类型不同，第一栅极和第二栅极表征的晶体管类型可以互换。示例性地，所述第一栅极对应的晶体管可以包括PMOS晶体管；所述第二栅极对应的晶体管可以包括NMOS晶体管；或者，所述第一栅极对应的晶体管可以包括NMOS晶体管；所述第二栅极对应的晶体管可以包括PMOS晶体管。
为了便于理解本公开的立意，下面结合附图，对第一导线和第二导线的具体排布方式进行详细说明。图4a至图4d示出了多种不同的子字线驱动器的布线方式，需要说明的是，本公开实施例中半导体结构可以包括至少一个子字线驱动器，图4a至图4d中均示出了半导体结构包括2个子字线驱动器的情况。此外，为了方便后续的计算比较，将第一导线的总长度和第二导线的总长度设定为相同，将与第一方向和第二方向均相交的方向设定为与第一方向和第二方向的夹角均为45°，同时将第一导线和第二导线均沿第二方向延伸时，图3b中子字线驱动器在X轴方向上的宽度L作为参考值。
图4a对应的半导体结构100中示出了第一导线401沿与第一方向和第二方向均相交的方向延伸，第二导线(402a、402b)与第二方向平行。此时，第一导线401在第二方向上的投影宽度，小于第一导线401沿第二方向设置时第一导线401在第二方向上的宽度。根据计算，图4a中子字线驱动器在第二方向上的宽度相较于参考值减小了29.3％。
图4b对应的半导体结构200中示出了第二导线(402a、402b)沿与第一方向和第二方向均相交的方向延伸，第一导线401与第二方向平行。第二导线(402a、402b)在第二方向上的投影宽度，小于第二导线(402a、402b)沿第二方向设置时第二导线(402a、402b)在第二方向上的宽度。根据计算，子字线驱动器在第二方向上的宽度相较于参考值减小了29.3％。
图4c对应的半导体结构300与图4b中示出的半导体结构200中不同之处在于第一导线401的形状不同，第二导线的两个部分(402a、402b)的延伸方向不同，二者在第二方向上的宽度相同。根据计算，子字线驱动器在第二方向上的宽度相较于参考值减小了29.3％。
图4d对应的半导体结构400中示出了第一导线401、第二导线(402a、402b)均沿与第一方向和第二方向均相交的方向延伸。第一导线401和第二导线(402a、402b)在第二方向上的宽度均减小；根据计算，子字线驱动器在第二方向上的宽度相较于参考值减小了58.6％。
然而，在第一导线和/或第二导线与第一方向和第二方向均相交时，第一导线和/或第二导线在第一方向上的宽度相对增加。其增大的宽度与第一导线或第二导线与第二方向之间的夹角相关，根据计算，在第一导线和第二导线与第二方向的夹角均为α时，子字线驱动器的面积缩小了1-(2-2cosα)/4。示例性的，在夹角α为45°时，子字线驱动器的面积缩小了14.6％。
可以理解的是，通过将主字线中的多个第一栅极形成的连线、至少部分第二栅极形成的连线中至少之一的延伸方向设置为与第一方向和第二方向均相交，如此， 可以在保持沟道长度不变的前提下，使得主字线沿第二方向的宽度出现不同程度的缩小，从而达到缩小子字线驱动器面积的目的。
实际应用中，考虑到当沿与第一方向和第二方向均相交的方向与第二方向的角度大于预设角度时，存在两方面问题：一方面，主字线沿第一方向的长度增加过大；另一方面，主字线中相邻位置处的栅极对应的有源区可能出现重叠、相交的情况。基于此，进一步限定第一导线或第二导线延伸方向与第二方向的角度可以优化上述存在的两个问题。在一些实施例中，所述预设角度为45°。
在一些实施例中，所述多个第一栅极物理连接且均沿第三方向延伸，所述多个第一有源区沿所述第三方向间隔排布，至少部分所述第二栅极物理连接均沿第四方向延伸；所述第三方向所在直线与所述第二方向所在直线的夹角范围为：0-45°；和/或，所述第四方向所在直线与所述第二方向所在直线的夹角范围为：0-45°。
例如，在一些实施例中，所述多个第一栅极物理连接且均沿第三方向延伸，所述多个第二栅极物理连接在所述多个第一栅极的一端且均沿第四方向延伸。
例如，在一些实施例中，所述多个第一栅极物理连接且均沿第三方向延伸，一部分所述第二栅极物理连接在所述多个第一栅极的一端且均沿第四方向延伸，另一部分所述第二栅极物理连接在所述多个第一栅极的另一端且均沿第五方向延伸，所述第五方向所在直线与所述第二方向所在直线的夹角范围为：0-45°。
这里，第三方向为第一导线的延伸方向，其为与第一方向和第二方向均相交的方向；第四方向和第五方向均为部分第二导线的延伸方向，其均为与第一方向和第二方向均相交的方向。在第二导线仅位于第一导线的一侧时，第二导线仅沿第四方向延伸；在第二导线分别位于第一导线的两侧时，第二导线分别沿第四方向和第五方向延伸。考虑到在预设角度过大时可能存在前述的两个问题，本公开实施例中，将第三方向、第四方向以及第五方向所在直线与所述第二方向所在直线的夹角范围均设置为0-45°。
需要说明的是，第一导线对应的多个第一有源区沿着第一导线的延伸方向间隔排布。
示例性的，参考图5a，半导体结构500中包括多个第一有源区403和四个主字线404，每一主字线404中包括第一导线401和第二导线(402a、402b)；第二导线(402a、402b)分别位于第一导线401的两侧，每一第一导线401均沿第三方向(参考图5a中AP方向)延伸，第二导线(402a、402b)均沿第四方向延伸(这里，第四方向与附图5a中的X轴方向平行)。
示例性的，参考图5b，半导体结构600中，每一主字线404中包括第一导线401和第二导线(402a、402b)，第二导线(402a、402b)分别位于第一导线401的两侧，第一导线401沿第三方向(这里，第三方向与附图5b中的X轴方向平行)延伸，一部分第二导线402a沿第四方向(参考图5b中BP方向)延伸，另一部分第二导线402b沿第五方向(参考图5b中CP方向)延伸。
示例性的，参考图5c，半导体结构700中，每一主字线404中包括第一导线401和第二导线(402a、402b)，第二导线(402a、402b)分别位于第一导线401的两侧，第一导线401沿第三方向(参考图5c中DP方向)延伸，一部分第二导线402a沿第四方向(参考图5c中EP方向)延伸，另一部分第二导线402b沿第五方向(参考图5c中PF方向)延伸。
示例性的，参考图5d，半导体结构800中，每一主字线404中包括第一导线401和第二导线402，第二导线402仅位于第一导线401的一侧，第一导线401沿第三方向(参考图5d中GP方向)延伸；第二导线402沿第四方向(参考图5d中HP方向)延伸。
需要说明的是，图5a至图5d中，在第三方向、第四方向、第五方向均与所述第一方向、第二方向相交时，第三方向、第四方向、第五方向所在直线分别与所述第二方向所在直线的夹角的值可以相同，也可以不同。
在一些实施例中，所述第四方向所在的直线与所述第三方向所在的直线之间的夹角为第一夹角，所述第五方向所在的直线与所述第三方向所在的直线之间的夹角为第二夹角，所述第一夹角与所述第二夹角相等。
示例性的，参考图5b，所述第一夹角为∠CPX，所述第二夹角为∠BP(-X)，这里，所述第一夹角与所述第二夹角相等，即∠CPX＝∠BP(-X)。
示例性的，参考图5c，所述第一夹角为∠DPE，所述第二夹角为∠DPF，这里，所述第一夹角与所述第二夹角相等，即∠DPE＝∠DPF。此时，第四方向和第五方向平行。
在另一些实施例中，所述第一夹角与所述第二夹角不同。
可以理解的是，当第一夹角与第二夹角相同时，第二导线的两个部分沿第二方向的宽度出现缩减的程度相同，同时第二导线的两个部分(402a、402b)沿第一方向的长度的变化程度也是相同的，这将有利于第二栅极的整体尺寸的控制。
在一些实施例中，所述第三方向所在直线与所述第二方向所在直线的夹角为45°，所述多个第一有源区呈步进状间隔排布，所述第四方向所在直线与所述第二方向所在直线的夹角为45°，所述第五方向所在直线与所述第二方向所在直线的夹角为45°。
示例性的，参考图5c，第三方向与X轴方向的夹角为∠DPO；第四方向与X轴方向的夹角为∠EPX；第五方向与X轴方向的夹角为∠OPF；这里，∠DPO＝∠EPX＝∠OPF＝45°。
结合前面的计算方法，当第三方向、第四方向、第五方向的夹角均为45度时，子字线驱动器在第二方向上的宽度相较于参考值减小的程度最大。同时，当第四方向和第五方向平行，但不与第三方向平行时，相较于当第四方向与第五方向和第三方向均平行时，子字线驱动器在第一方向上的长度更小。
在一些实施例中，所述第一栅极整体均沿所述第三方向延伸；或者，所述第一栅极包括沿所述第三方向延伸的第一部分和第二部分以及连接所述第一部分和第二部分的第三部分。
示例性的，参考图5a、图5b、图5c、图5d，多个第一栅极物理连接形成的第一导线401呈直线型。在另一些实施例中，多个第一栅极物理连接形成的第一导线401呈“Z”字型或反“Z”字型，如图6a、图6b所示。
具体地，参考图6a、图6b，第一导线401包括相互连接的第一部分401a、第二部分401b和第三部分401c，第一部分401a和第二部分401b均沿第三方向延伸但不重叠，第三部分401c用于连接第一部分401a和第二部分401b，进而使得第一导线401呈“Z”字型或反“Z”字型。其中，半导体结构900中多个呈“Z”字型的第一导线401和呈反“Z”字型的第一导线401间隔排布，如此，可以使得沿Y轴方向相邻设置的两个第一导线401之间的部分区域间距较大，该较大间距区域可以根据需求设置其他器件结构，例如噪声抑制单元；后文中有相关内容，这里不再详述。
需要说明的是，图6b为图6a中呈“Z”字型的第一导线401的放大示意图。
在一些实施例中，所述半导体结构包括N个子字线驱动器，所述N为大于等于1的正整数；所述N个子字线驱动器中每一子字线驱动器包含的物理连接的所述第一栅极均平行且两端均齐平；所述N个子字线驱动器中每一子字线驱动器包含的物 理连接的所述第二栅极均平行且两端均齐平。
示例性的，参考图5b，半导体结构600包括N个子字线驱动器404，这里，N＝4；其中，每一个子字线驱动器404包含四个第一栅极物理连接，形成第一导线401；其中，四个第一栅极相互平行，且两端基本齐平。
需要说明的是，每一个子字线驱动器404中包含四个第一栅极，以及与其对应的四个第一有源区403，四个第一有源区403沿第三方向间隔排布。
示例性的，参考图5a，半导体结构500包括N个子字线驱动器404，这里，N＝4；其中，每一个子字线驱动器404包含四个第二栅极物理连接；其中，两个第二栅极位于第一导线401的一侧，两个第二栅极位于第一导线401的另一侧。这里，四个第二栅极相互平行，且两端基本齐平。
在一些实施例中，所述子字线驱动器还包括：多个第三栅极，第三栅极均位于所述N个子字线驱动器中相邻的两个子字线驱动器的第二栅极之间。
参考图5a，在半导体结构500中相邻的两个子字线驱动器404之间还设置有第三栅极405，所述第三栅极405位于沿第一方向并列设置的相邻两个第二栅极(第二导线402a)之间。
在一些实施例中，所述子字线驱动器还包括至少一个第二有源区，与所述多个第二栅极、所述多个第三栅极对应；所述第一有源区的形状为长条形，所述第二有源区的形状为网格状。
参考图5a，第一有源区403的形状可以为长条状，所述第一栅极与所述第一有源区403一一对应。第二有源区406的形成可以为长条状，也可以为网格状；在第二有源区406的形成为长条状时，一个第二栅极与一个第二有源区一一对应；在第二有源区的形成为网格状时，多个第二栅极与一个第二有源区对应。另外，在第二有源区406的形成为网格状时，位于相邻两个第二栅极之间的第三栅极也与该第二有源区对应，即多个第二栅极和多个第三栅极共用一个第二有源区406；如此，可以减少有源区的设置，进而减小子字线驱动器的面积。
需要说明的是，第三栅极及其对应的晶体管可以用于形成噪声抑制单元。
参考图7，在第二导线402位于两个第一导线401之间时，第三栅极405位于沿Y中方向上相邻的两个第二栅极(即相邻的第二导线402)之间。另外，图7中仅示出了一种第二导线402与第一导线401的排布方式，在另一些实施例中，还可以是其他类型的排布方式，这里不再一一赘述。
在一些实施例中，沿所述第一方向相邻的两个第三栅极形成为“C”字型或“I”字型。
参考图5a，在第二导线(402a或402b)与X轴方向平行时，位于沿Y轴方向相邻两个第二导线(402a或402b)之间的第三栅极405呈“C”字型或反“C”字型。
参考图6a，在第二导线(402a或402b)与X轴方向所在的直线相交时，沿Y轴方向相邻设置的两个第三栅极405呈“I”字型。
在一些实施例中，所述N个子字线驱动器包括沿所述第一方向依次设置的第一子字线驱动器和第二子字线驱动器；所述第一子字线驱动器和第二子字线驱动器中的第三栅极均位于所述第一子字线驱动器的第二栅极和第二子字线驱动器的第二栅极之间。
参考图4a，图4a中示出的半导体结构100包括2个子字线驱动器，即沿Y轴方向相邻设置的第一子字线驱动器100-1和第二子字线驱动器100-2，第三栅极405位于第一子字线驱动器100-1的第二栅极402a和第二子字线驱动器100-2的第二栅 极402a之间；或者，第三栅极405位于第一子字线驱动器100-1的第二栅极402b和第二子字线驱动器100-2的第二栅极402b之间。
在一些实施例中，所述N个子字线驱动器包括沿所述第一方向依次设置的第一子字线驱动器、第二子字线驱动器、第三子字线驱动器和第四子字线驱动器；所述N个子字线驱动器的第一栅极整体均沿所述第一方向延伸；第一子字线驱动器和第二子字线驱动器的第二栅极之间的距离为L1，第二子字线驱动器和第三子字线驱动器的第二栅极之间的距离为L2，第三子字线驱动器和第四子字线驱动器的第二栅极之间的距离为L3，其中，L1＝L3，L1＞L2；所述N个子字线驱动器的第三栅极位于所述第一子字线驱动器的第二栅极和第二子字线驱动器的第二栅极之间，以及所述第三子字线驱动器的第二栅极和第四子字线驱动器的第二栅极之间。
参考图5b，图5b中示出的半导体结构600包括4个沿所述第一方向依次设置的子字线驱动器，即第一子字线驱动器、第二子字线驱动器、第三子字线驱动器和第四子字线驱动器，其中，第一子字线驱动器的第二栅极402a-1与第二子字线驱动器的第二栅极402a-2之间的距离为L1，第二子字线驱动器的第二栅极402a-2与第三子字线驱动器的第二栅极402a-3之间的距离为L2，第三子字线驱动器的第二栅极402a-3与第四子字线驱动器的第二栅极402a-4之间的距离为L3，这里，L1＞L2，L3＞L2；在一些实施例中，L1＝L3；基于此，L1＝L3＞L2。
在此情况下，为了减小子字线驱动器的总面积，将第三栅极405设置在第一子字线驱动器的第二栅极402a-1与第二子字线驱动器的第二栅极402a-2之间；和/或，将第三栅极405设置在第三子字线驱动器的第二栅极402a-3与第四子字线驱动器的第二栅极402a-4之间。
在一些实施例中，第二子字线驱动器的第一栅极与所述第三子字线驱动器的第一栅极存在共用的有源区。
图5b中示出的半导体结构600中包括多个第二子字线驱动器的第一栅极401-1和多个第三子字线驱动器的第一栅极401-2，以及多个第一有源区403。沿Y轴方向相邻的第二子字线驱动器的第一栅极401-1和第三子字线驱动器的第一栅极401-2之间的距离为L2，对应的，第二子字线驱动器的第二栅极402a-2与第三子字线驱动器的第二栅极402a-3之间的距离也为L2，相较于沿Y轴方向相邻的第一子字线驱动器和第二子字线驱动器之间的距离L1而言相对较小，因此，可以将第二子字线驱动器的第一栅极401-1与所述第三子字线驱动器的第一栅极401-2共用一个第一有源区403，如此，也可以减小子字线驱动器的总面积。
在一些实施例中，所述N个子字线驱动器包括沿所述第一方向依次设置的第一子字线驱动器、第二子字线驱动器、第三子字线驱动器和第四子字线驱动器；所述N个子字线驱动器的所述第一栅极包括沿所述第一方向延伸的第一部分和第二部分以及连接所述第一部分和第二部分的第三部分；相邻的两个子字线驱动器之间的第一栅极的第一部分的间距为第一距离或第二距离，相邻的两个子字线驱动器之间的第一栅极的第二部分的间距为所述第一距离或所述第二距离，所述第一距离大于所述第二距离；所述N个子字线驱动器的第三栅极位于所述N个子字线驱动器中间距为第一距离的两个相邻第一栅极连接的第二栅极之间。
参考图6a，半导体结构900中，第一子字线驱动器400-1对应的多个第一栅极物理连接，形成的第一导线包括第一部分401a和第二部分401b以及连接所述第一部分和第二部分的第三部分401c。第二子字线驱动器400-2对应的多个第一栅极物理连接，形成的第一导线包括第一部分401a和第二部分401b以及连接所述第一部分和第二部分的第三部分401c。第三子字线驱动器400-3对应的多个第一栅极物理 连接，形成的第一导线包括第一部分401a和第二部分401b以及连接所述第一部分和第二部分的第三部分401c。第四子字线驱动器400-4对应的多个第一栅极物理连接，形成的第一导线401包括第一部分401a和第二部分401b以及连接所述第一部分和第二部分的第三部分401c。
第一子字线驱动器400-1对应的第一部分401a与第二子字线驱动器400-2对应的第一部分401a之间的距离为R1；第一子字线驱动器400-1对应的第二部分401b与第二子字线驱动器400-2对应的第二部分401b之间的距离为R2。
第二子字线驱动器400-2对应的第一部分401a与第三子字线驱动器400-3对应的第一部分401a之间的距离为R2；第二子字线驱动器400-2对应的第二部分401b与第三子字线驱动器400-3对应的第二部分401b之间的距离为R1。
第三子字线驱动器400-3对应的第一部分401a与第四子字线驱动器400-4对应的第一部分401a之间的距离为R1；第三子字线驱动器400-3对应的第二部分401b与第四子字线驱动器400-4对应的第二部分401b之间的距离为R2。
这里，所述第一距离R1大于所述第二距离R2；基于此，将N个子字线驱动器对应的多个第三栅极设置在相距第一距离R1的沿Y轴方向相邻设置的两个第一栅极连接的第二栅极之间。换言之，第三栅极位于相邻的两个第二栅极之间，且与该相邻的两个第二栅极分别连接的两个第一栅极之间的距离为第一距离R1。
在一些实施例中，所述N个子字线驱动器中间距为第二距离的两个相邻第一栅极之间存在共用的所述第一有源区。
参考图6a，第一子字线驱动器400-1对应的第二部分401b与第二子字线驱动器400-2对应的第二部分401b之间、第二子字线驱动器400-2对应的第一部分401a与第三子字线驱动器400-3对应的第一部分401a之间、以及第三子字线驱动器400-3对应的第二部分401b与第四子字线驱动器400-4对应的第二部分401b之间的距离均为第二距离R2，基于此，该区域中，相邻的两个第一栅极之间可以共用一个第一有源区403，以减子小字线驱动器的总面积。
在一些实施例中，所述第一栅极对应的晶体管包括PMOS晶体管；所述第二栅极对应的晶体管、所述第三栅极对应的晶体管均包括NMOS晶体管。
这里，上述第一栅极、第二栅极、第三栅极对应图2中示出的子字线驱动器电路时，可以有上述的PMOS和NMOS的对应关系。
可以理解的是，在另一些实施例中，所述第一栅极对应的晶体管包括NMOS晶体管；所述第二栅极对应的晶体管、所述第三栅极对应的晶体管均包括PMOS晶体管。此时，可以根据电路的功能需求，调整相应的电路连接关系。
在一些实施例中，所述子字线驱动器还包括多个导电接触；每个所述导电接触分别与第一有源区或第二有源区中的源极或漏极连接。
参考图5a、图6a，每一子字线驱动器中还设置有多个导电接触407；所述导电接触407可以位于第一栅极的至少一侧，与所述第一有源区403中的源极或漏极连接；所述导电接触407也可以位于第二栅极的至少一侧，与所述第二有源区406中的源极或漏极连接。
基于此，本公开实施例中，将第一栅极对应的第一有源区的延伸方向定义为第一方向，将与第一有源区所在的平面平行且垂直于第一方向的方向定义为第二方向，通过将主字线中的多个第一栅极形成的连线、至少部分第二栅极形成的连线中至少之一的延伸方向设置为与第一方向和第二方向均相交，从而可以在保持沟道长度不变的前提下，使得主字线沿第二方向的宽度(主字线在第一方向上的投影尺寸)缩小，子字线驱动器的占用面积缩小，进而提高存储器的集成度。
本公开实施例还提供了一种存储器，包括：如本公开上述实施例中所述的半导体结构。
这里，所述存储器中的相关结构的布局可以参考前述的图1b的相关描述。
本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例提供的半导体结构中，将第一栅极对应的第一有源区的延伸方向定义为第一方向，将与第一有源区所在的平面平行且垂直于第一方向的方向定义为第二方向，通过将主字线中的多个第一栅极形成的连线、至少部分第二栅极形成的连线中至少之一的延伸方向设置为与第一方向和第二方向均相交，从而可以在保持沟道长度不变的前提下，使得主字线沿第二方向的宽度(主字线在第一方向上的投影尺寸)缩小，子字线驱动器的占用面积缩小，进而提高半导体结构的集成度。

Claims (19)

  1. 一种半导体结构，包括：至少一个子字线驱动器，所述子字线驱动器包括：
    多个第一有源区；以及
    主字线，包括互连的多个第一栅极和多个第二栅极；所述多个第一栅极对应所述多个第一有源区；
    其中，所述主字线中的所述多个第一栅极的延伸方向和/或所述主字线中的至少部分第二栅极的延伸方向与第一方向和第二方向均相交；所述第一方向平行于所述第一有源区延伸的方向，所述第二方向与所述第一有源区所在的平面平行且垂直于所述第一方向。
  2. 根据权利要求1所述的半导体结构，其中，所述多个第一栅极物理连接且均沿第三方向延伸，所述多个第一有源区沿所述第三方向间隔排布，至少部分所述第二栅极物理连接均沿第四方向延伸；
    所述第三方向所在直线与所述第二方向所在直线的夹角范围为：0-45°；和/或，所述第四方向所在直线与所述第二方向所在直线的夹角范围为：0-45°。
  3. 根据权利要求2所述的半导体结构，其中，所述多个第一栅极物理连接且均沿第三方向延伸，所述多个第二栅极物理连接在所述多个第一栅极的一端且均沿第四方向延伸。
  4. 根据权利要求2所述的半导体结构，其中，所述多个第一栅极物理连接且均沿第三方向延伸，一部分所述第二栅极物理连接在所述多个第一栅极的一端且均沿第四方向延伸，另一部分所述第二栅极物理连接在所述多个第一栅极的另一端且均沿第五方向延伸，所述第五方向所在直线与所述第二方向所在直线的夹角范围为：0-45°。
  5. 根据权利要求4所述的半导体结构，其中，所述第四方向所在的直线与所述第三方向所在的直线之间的夹角为第一夹角，所述第五方向所在的直线与所述第三方向所在的直线之间的夹角为第二夹角，所述第一夹角与所述第二夹角相等。
  6. 根据权利要求5所述的半导体结构，其中，所述第三方向所在直线与所述第二方向所在直线的夹角为45°，所述多个第一有源区呈步进状间隔排布，所述第四方向所在直线与所述第二方向所在直线的夹角为45°，所述第五方向所在直线与所述第二方向所在直线的夹角为45°。
  7. 根据权利要求2所述的半导体结构，其中，
    所述第一栅极整体均沿所述第三方向延伸；
    或者，
    所述第一栅极包括沿所述第三方向延伸的第一部分和第二部分以及连接所述第一部分和第二部分的第三部分。
  8. 根据权利要求2至7中任一项所述的半导体结构，其中，所述半导体结构包括N个子字线驱动器，所述N为大于等于1的正整数；
    所述N个子字线驱动器中每一子字线驱动器包含的物理连接的所述第一栅极均平行且两端均齐平；
    所述N个子字线驱动器中每一子字线驱动器包含的物理连接的所述第二栅极均平行且两端均齐平。
  9. 根据权利要求8所述的半导体结构，其中，所述子字线驱动器还包括：多个第三栅极，所述多个第三栅极均位于所述N个子字线驱动器中相邻的两个子字线驱动器的第二栅极之间。
  10. 根据权利要求9所述的半导体结构，其中，所述N个子字线驱动器包括第一子字线驱动器和第二子字线驱动器；
    所述第一子字线驱动器和第二子字线驱动器中的第三栅极均位于所述第一子字线驱动器的第二栅极和第二子字线驱动器的第二栅极之间。
  11. 根据权利要求9所述的半导体结构，其中，所述N个子字线驱动器包括沿所述第一方向依次设置的第一子字线驱动器、第二子字线驱动器、第三子字线驱动器和第四子字线驱动器；所述N个子字线驱动器的第一栅极整体均沿所述第一方向延伸；所述第一子字线驱动器和第二子字线驱动器的第二栅极之间的距离为L1，所述第二子字线驱动器和第三子字线驱动器的第二栅极之间的距离为L2，所述第三子字线驱动器和第四子字线驱动器的第二栅极之间的距离为L3；其中，L1＝L3，L1＞L2；
    所述N个子字线驱动器的第三栅极位于所述第一子字线驱动器的第二栅极和第二子字线驱动器的第二栅极之间，以及所述第三子字线驱动器的第二栅极和第四子字线驱动器的第二栅极之间。
  12. 根据权利要求11所述的半导体结构，其中，所述第二子字线驱动器的第一栅极与所述第三子字线驱动器的第一栅极存在共用的有源区。
  13. 根据权利要求9所述的半导体结构，其中，所述N个子字线驱动器包括沿所述第一方向依次设置的第一子字线驱动器、第二子字线驱动器、第三子字线驱动器和第四子字线驱动器；所述N个子字线驱动器的所述第一栅极包括沿所述第一方向延伸的第一部分和第二部分以及连接所述第一部分和第二部分的第三部分；相邻的两个子字线驱动器之间的第一栅极的第一部分的间距为第一距离或第二距离，相邻的两个子字线驱动器之间的第一栅极的第二部分的间距为所述第二距离或所述第一距离，所述第一距离大于所述第二距离；
    所述N个子字线驱动器的第三栅极位于所述N个子字线驱动器中间距为第一距离的两个相邻第一栅极连接的第二栅极之间。
  14. 根据权利要求13所述的半导体结构，其中，所述N个子字线驱动器中间距为第二距离的两个相邻第一栅极之间存在共用的所述第一有源区。
  15. 根据权利要求9所述的半导体结构，其中，沿所述第一方向相邻的两个第三栅极形成为“C”字型或“I”字型。
  16. 根据权利要求9所述的半导体结构，其中，所述第一栅极对应的晶体管包括P型晶体管；所述第二栅极对应的晶体管、所述第三栅极对应的晶体管均包括N型晶体管。
  17. 根据权利要求9所述的半导体结构，其中，所述子字线驱动器还包括至少一个第二有源区，与所述多个第二栅极、所述多个第三栅极对应；
    所述第一有源区的形状为长条形，所述第二有源区的形状为网格状。
  18. 根据权利要求17所述的半导体结构，其中，所述子字线驱动器结构还包括多个导电接触；每个所述导电接触分别与所述第一有源区或所述第二有源区中的源极或漏极连接。
  19. 一种存储器，包括：
    如权利要求1至18任一项所述的半导体结构。
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