JP2012080100A - 縦型トランジスタstramアレイ - Google Patents
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 25
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
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- 229910052782 aluminium Inorganic materials 0.000 description 1
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- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
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- 239000010937 tungsten Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
- G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
- H10B63/34—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the vertical channel field-effect transistor type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
【解決手段】方法は、半導体ウェハから垂直に伸延する複数のピラー構造を有する半導体ウェハを提供するステップを含む。導電相互接続素子が、少なくとも選択された縦型ピラートランジスタ上に堆積されるとともに、不揮発性可変抵抗メモリセルが、導電相互接続素子上に堆積されて、縦型トランジスタメモリアレイを形成する。
【選択図】図14B
Description
ソリッドステートメモリ(Solid State Memory:SSM)は、携帯用電子装置のような広範囲の用途において、データを記憶しかつ転送するための効果的な機構を提供する。このようなメモリにおける個々のメモリセルは、揮発性または不揮発性であり、ビット列を記憶するために、セルへの適当な書込電流の印加によって、データを記憶することができる。記憶されたビットは、引き続いて、適当な読出電流を印加するとともにセルにかかる電圧降下を検出することによって、読出アクセスの間に読み出され得る。
本開示は、各々のメモリセルが導電相互接続素子によって縦型ピラートランジスタに電気的に接続される、複数の不揮発性可変抵抗メモリセルを含むメモリアレイに関する。導通相互接続素子は、メモリセルと縦型ピラートランジスタとの間の界面抵抗および/または応力を低減することができる。これも形成する方法も開示される。
以下の説明においては、本明細書の一部を形成するとともに、いくつかの特定の実施形態の例示のために示される添付の一組の図面が参照される。他の実施形態が予期され、本開示の範囲または精神から逸脱することなくなされることが理解されるべきである。したがって、以下の詳細な説明は、限定の意味として採用されるべきではない。本明細書で与えられる定義は、本明細書で頻繁に用いられる特定の語句の理解を容易にするものであり、本開示の範囲を限定することを意味するものではない。
Claims (25)
- 方法であって、
半導体ウェハを提供するステップを備え、前記半導体ウェハは前記半導体ウェハから垂直に伸延する複数のピラー構造を有し、各ピラー構造は、上面および前記上面に垂直な側面を有する縦型ピラートランジスタを形成し、
前記方法は、
少なくとも選択された縦型ピラートランジスタの上面上に導電相互接続素子を堆積させるステップと、
前記導電相互接続素子上に不揮発性可変抵抗メモリセルを堆積させて、縦型トランジスタメモリアレイを形成するステップとをさらに備える、方法。 - 隣接する不揮発性可変抵抗メモリセルは、互いに電気的に絶縁される、請求項1に記載の方法。
- 隣接する導電相互接続素子は、酸化物材料で、互いに電気的に絶縁される、請求項1に記載の方法。
- 前記導電相互接続素子を堆積させるステップは、少なくとも選択された縦型ピラートランジスタ上面上に、400℃より低い堆積温度で、シリサイド層を堆積させるステップを含む、請求項1に記載の方法。
- 前記上面は、前記半導体ウェハの主表面に平行である、請求項1に記載の方法。
- 前記不揮発性可変抵抗メモリセルは、楕円形の断面形状を有し、
前記縦型ピラートランジスタは、円形の断面形状を有する、請求項1に記載の方法。 - 前記不揮発性可変抵抗メモリセルは、円形の断面形状を有し、
前記縦型ピラートランジスタは、円形の断面形状を有する、請求項1に記載の方法。 - 前記不揮発性可変抵抗メモリセルは、スピントルクトランスファメモリセルを含む、請求項1に記載の方法。
- 前記縦型ピラートランジスタは、前記不揮発性可変抵抗メモリセルと位置合わせされる、請求項7に記載の方法。
- 前記不揮発性可変抵抗メモリセルの選択された行または列上に、ビットラインを堆積させるステップをさらに備える、請求項1に記載の方法。
- 前記シリサイド層は、前記不揮発性可変抵抗メモリセルと位置合わせされる前記縦型ピラートランジスタを、電気的に接続するとともに分離する、請求項4に記載の方法。
- 方法であって、
半導体ウェハを提供するステップを備え、前記半導体ウェハは前記半導体ウェハから垂直に伸延する複数のピラー構造を有し、各ピラー構造は、上面および前記上面に垂直な側面を有する縦型ピラートランジスタを形成し、
前記方法は、
前記縦型ピラートランジスタの前記上面上に酸化物材料層を堆積させるステップと、
前記酸化物材料層内にビアをエッチングするステップとをさらに備え、各ビアは、前記縦型ピラートランジスタの選択された上面に位置合わせされ、
前記方法は、
少なくとも選択されたビア内に、導電相互接続素子を堆積させるステップと、
前記導電相互接続素子上に不揮発性可変抵抗メモリセルを堆積させて、縦型トランジスタメモリアレイを形成するステップとをさらに備える、方法。 - 前記上面は、前記半導体ウェハの主表面に平行である、請求項12に記載の方法。
- 少なくとも選択された不揮発性可変抵抗メモリセルは、少なくとも選択された縦型ピラートランジスタに電気的に接続され、少なくとも選択された不揮発性可変抵抗メモリセルは、少なくとも選択された縦型ピラートランジスタからオフセットされる、請求項12に記載の方法。
- 前記不揮発性可変抵抗メモリセルは、円形の断面形状を有し、
前記縦型ピラートランジスタは、円形の断面形状を有する、請求項12に記載の方法。 - 前記不揮発性可変抵抗メモリセルは、楕円形の断面形状を有する、請求項12に記載の方法。
- 前記メモリセルは、スピントルクトランスファメモリセルを含む、請求項12に記載の方法。
- 前記酸化物材料層を堆積させるステップの前に、少なくとも選択された縦型ピラートランジスタ上面上に、400℃より低い堆積温度で、シリサイド層を堆積させるステップをさらに備える、請求項1に記載の方法。
- 方法であって、
半導体ウェハを提供するステップを備え、前記半導体ウェハは前記半導体ウェハから垂直に伸延する複数のピラー構造を有し、各ピラー構造は、上面および前記上面に垂直な側面を有する縦型ピラートランジスタを形成し、
前記方法は、
少なくとも選択された縦型ピラートランジスタ上面上に、400℃より低い堆積温度で、シリサイド層を堆積させるステップと、
前記シリサイド層上に不揮発性可変抵抗メモリセルを堆積させて、縦型トランジスタメモリアレイを形成するステップとをさらに備える、方法。 - 前記メモリセルは、スピントルクトランスファメモリセルを含む、請求項19に記載の方法。
- メモリアレイであって、
複数のピラー構造を有する半導体ウェハを備え、前記複数のピラー構造は前記半導体ウェハから垂直に伸延し、各ピラー構造は、上面および前記上面に垂直な側面を有する縦型ピラートランジスタを形成し、
前記メモリアレイは、
複数のメモリセルをさらに備え、少なくとも選択されたメモリセルは、前記縦型ピラートランジスタから垂直にオフセットするとともに前記縦型ピラートランジスタに電気的に接続する断面形状を有し、
前記メモリアレイは、
前記メモリセルと前記縦型ピラートランジスタとの間のシリサイド層をさらに備える、メモリアレイ。 - 前記メモリセルは、STRAMセルである、請求項21に記載のメモリアレイ。
- 上面を有する前記縦型ピラートランジスタ上に堆積された導電相互接続素子をさらに備え、
前記メモリセルは、前記導電相互接続素子に電気的に接続されるとともに前記導電相互接続素子から垂直にオフセットした断面形状を有する、請求項21に記載のメモリアレイ。 - 前記メモリセルは、楕円形の断面形状を有する、請求項21に記載のメモリアレイ。
- 前記メモリセルは、ソースラインおよびビットラインに対して、40°から50°の角度に方向付けられる、請求項21に記載のメモリアレイ。
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Application Number | Priority Date | Filing Date | Title |
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US12/894,405 | 2010-09-30 | ||
US12/894,405 US20120080725A1 (en) | 2010-09-30 | 2010-09-30 | Vertical transistor memory array |
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JP2012080100A true JP2012080100A (ja) | 2012-04-19 |
JP5566981B2 JP5566981B2 (ja) | 2014-08-06 |
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US (1) | US20120080725A1 (ja) |
JP (1) | JP5566981B2 (ja) |
KR (1) | KR101405860B1 (ja) |
CN (1) | CN102543847A (ja) |
Cited By (2)
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KR101464859B1 (ko) * | 2012-11-12 | 2014-11-25 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 고밀도 rram 및 mram을 위한 4f² 구동기 형성 방법 |
US9520446B2 (en) | 2012-11-12 | 2016-12-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Innovative approach of 4F2 driver formation for high-density RRAM and MRAM |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
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US8575584B2 (en) * | 2011-09-03 | 2013-11-05 | Avalanche Technology Inc. | Resistive memory device having vertical transistors and method for making the same |
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JP5566981B2 (ja) | 2014-08-06 |
CN102543847A (zh) | 2012-07-04 |
KR20120034045A (ko) | 2012-04-09 |
KR101405860B1 (ko) | 2014-06-12 |
US20120080725A1 (en) | 2012-04-05 |
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