US20180182448A1 - Sub word line driver of semiconductor memory device - Google Patents
Sub word line driver of semiconductor memory device Download PDFInfo
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- US20180182448A1 US20180182448A1 US15/691,945 US201715691945A US2018182448A1 US 20180182448 A1 US20180182448 A1 US 20180182448A1 US 201715691945 A US201715691945 A US 201715691945A US 2018182448 A1 US2018182448 A1 US 2018182448A1
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- word line
- active regions
- active region
- sub word
- line driver
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
Definitions
- Embodiments of the present disclosure relate to a sub word line driver of a semiconductor memory device, and more particularly to a layout of forming a well pickup in a PMOS region of a sub word line driver.
- a semiconductor memory device includes a plurality of memory cells and a circuit for controlling the memory cells.
- FIG. 1 is a conceptual diagram illustrating an arrangement structure of cell mats MATs for use in a general semiconductor memory device.
- the semiconductor memory device includes a plurality of mats MATs, each of which includes array-shaped memory cells for storing data.
- Each mat MAT may include a bit-line sense amplifier BLSA arranged in a row direction to sense/amplify cell data, and a plurality of sub word line drivers SWDs arranged in a column direction to enable sub word lines coupled to gates of cell transistors.
- the respective sub word line drivers SWDs may operate word lines WLs of the right and left cell mats MATs.
- FIG. 2 is a circuit diagram illustrating a general sub word line driver.
- the sub word line driver may be formed in a sub word line driver array shape which respectively outputs the sub word line drive signals SWL 0 ⁇ SWL 3 and SWL 4 ⁇ SWL 7 in response to main word line drive signals MWLB 0 and MWLB 1 and word line selection signals FX 0 , FX 2 , FX 4 , and FX 6 .
- the respective sub word line drivers may have the same structure in the remaining parts other than input/output (I/O) signals.
- Each sub word line driver may include a PMOS transistor P 11 and NMOS transistors N 11 and N 12 .
- the PMOS transistor P 11 and the NMOS transistor N 11 may be coupled in series between an input terminal of a word line selection signal FX 0 and an input terminal of a back-bias voltage VBBW (or ground voltage VSS), and may receive a main word line drive signal MWLB 0 through a common gate terminal.
- the NMOS transistor N 12 may be coupled in series between an output terminal of a sub word line drive signal SWL 0 and the back-bias voltage VBBW (or ground voltage VSS) input terminal, and may receive an inversion signal FXB 0 of the word line selection signal FX 0 through a gate terminal thereof.
- a regional gain gradually increases in proportion to the increasing size of the sub word line driver, such that a minimum-sized sub word line driver must be arranged in the semiconductor memory device.
- the conventional art has difficulty in forming a well pickup active region in a PMOS region while simultaneously reducing the region of a sub word line driver, such that the conventional art unavoidably shares well pickup active regions of the other regions.
- Various embodiments of the present disclosure are directed to providing a sub word line driver of a semiconductor memory device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
- An embodiment of the present disclosure relates to a sub word line driver for preventing an increase of the region of a sub word line driver by improving a structure of a sub word line, resulting in formation of a well pickup active region in a PMOS region.
- a sub word line driver of a semiconductor memory device includes: a plurality of first active regions arranged in a line shape in a first direction; a plurality of second active regions spaced apart from the plurality of first active regions a predetermined distance in a second direction, and arranged in a line shape in the first direction; a first main word line disposed over the first active regions, and formed in a diagonal direction in the first active regions; a second main word line disposed over the second active regions, and formed in a diagonal direction in the second active regions; and a pickup active region disposed between the first main word line and the second main word line.
- a sub word line driver of a semiconductor memory device includes: a first transistor including a first gate located in a first active region and first contacts disposed at both sides of the first gate; a second transistor including a second gate located in a second active region adjacent to the first active region in a first direction, and second contacts located at both sides of the second gate; a third transistor including a third gate located in a third active region adjacent to the first active region in a second direction, and third contacts located at both sides of the third gate; a fourth transistor including a fourth gate located in a fourth active region adjacent to the third active region in the first direction, and fourth contacts located at both sides of the fourth gate; and a pickup active region disposed among the first to fourth active regions.
- FIG. 1 is a conceptual diagram illustrating a prior art arrangement structure of cell mats MATs for use in a general semiconductor memory device.
- FIG. 2 is a conceptual diagram illustrating prior art sub word lines SWLs arranged in the cell mats MATs.
- FIG. 3 is a structural diagram illustrating a layout structure of a PMOS region in the sub word line driver according to an embodiment of the present disclosure.
- FIG. 4 is a structural diagram illustrating not only the layout structure of FIG. 3 , but also sub word lines and metal pads coupled to a pickup contact.
- FIG. 3 is a structural diagram illustrating a layout structure of a PMOS region of a sub word line driver according to an embodiment of the present disclosure.
- a PMOS region of the sub word line driver includes a plurality of active regions A_TR 1 ⁇ A_TR 8 in which transistors P 11 ⁇ P 24 are formed, and a plurality of pickup active regions A_PU 1 and A_PU 2 in which pickup regions PU 1 and PU 2 are formed.
- the active regions A_TR 1 ⁇ A_TR 4 may be spaced apart from each other a predetermined distance in a first direction (X direction).
- the active regions A_TR 5 ⁇ A_TR 8 (for example, second group of active regions) may also be spaced apart from each other a predetermined distance in the first direction, and may be spaced apart from the active regions A_TR 1 ⁇ A_TR 4 a predetermined distance in a second direction (Y direction).
- the pickup active regions A_PU 1 and A_PU 2 may be used as pickup regions for applying a bulk bias to an N well in which PMOS transistors P 11 ⁇ P 24 are formed, in a word line driver, and the pickup active regions A_PU 1 and A_PU 2 may be coupled to a contact 26 for receiving a back-bias voltage VBBW or a ground voltage.
- the pickup active regions A_PU 1 and A_PU 2 may be spaced apart from each other a predetermined distance in the first direction, and may be enclosed by the active regions A_TR 1 ⁇ A_TR 8 .
- the pickup active region A_PU 1 may be formed in a diamond (or lozenge) shape, and may be enclosed by four active regions A_TR 1 , A_TR 2 , A_TR 5 , and A_TR 6 .
- the pickup active region A_PU 2 may also be formed in a diamond shape, and may be enclosed by four active regions A_TR 3 , A_TR 4 , A_TR 7 , and A_TR 8 .
- a main word line 11 may be disposed over the active regions A_TR 1 -A_TR 4
- a main word line 12 may be disposed over the active regions A_TR 5 -A_TR 8
- the parts formed to overlap the active regions A_TR 1 -A_TR 8 may be used as gates G, or G 1 -G 4 for receiving main word line drive signals MWLB 0 and MWLB 1 illustrated in the sub word line driver of FIG. 2 .
- the gates designated by G include all gates including gates G 1 -G 4 .
- the parts i.e., the gates of the respective PMOS transistors P 11 -P 24 ) formed to overlap the active regions A_TR 1 -A_TR 8 in the main word lines 11 and 12 may be formed in a line shape extending in a diagonal direction with respect to the first direction and the second direction (Y direction).
- the gates G of the PMOS transistors P 11 -P 14 and P 21 -P 24 located adjacent to each other in the first direction may be formed to cross each other if the gates G were extended.
- the main word lines 11 and 12 may extend in a diagonal direction in the active regions A_TR 1 ⁇ A_TR 8 , and may be formed in a zigzag pattern in such a manner so that oblique directions of the main word lines 11 and 12 may be formed to cross each other in the active regions adjacent to the first direction. Moreover, the main word lines 11 and 12 may be formed to be symmetrical to each other based around the X-axis.
- the respective PMOS transistors P 11 -P 24 of FIG. 3 which are denoted by dotted lines for convenience of description and better understanding of the present disclosure, regions of the PMOS transistors P 11 -P 24 are not limited thereto.
- the main word lines 11 and 12 are formed to extend in symmetrical diagonal directions in the respective active regions A_TR 1 -A_TR 8 , such that a space between the main word lines 11 and 12 in which the pickup regions PU 1 and PU 2 can be formed may be guaranteed.
- the pickup active regions A_PU 1 and A_PU 2 for forming the pickup regions PU 1 and PU 2 may be formed between every two adjacent active regions.
- the pickup active region A_PU 1 is disposed between a first active region A_TR 1 and a sixth active region A_TR 6 and a second active region A_TR 2 and a fifth active region A_TRS.
- gates G of the respective PMOS transistors P 11 ⁇ P 24 are formed in a diagonal direction, such that the length of each gate G can be more freely elongated or shortened and the width of each transistor can be more freely enlarged as compared to the other case in which each gate G is formed in a horizontal or vertical direction.
- metal contacts 22 for receiving main word line selection signals FX 0 , FX 2 , FX 4 , and FX 6 and other metal contacts 24 coupled to sub word lines ⁇ circle around ( 1 ) ⁇ - ⁇ circle around ( 8 ) ⁇ may be respectively located at both sides of the main word lines 11 and 12 .
- a diagonal direction of the metal contacts 22 and 24 is parallel to the main word line located in the same active region A_TR 1 -A_TR 8 as the contacts 22 and 24 , such that the metal contacts 22 and 24 may be formed in a substantially rectangular shape (or, alternatively an oval shape) and may be spaced a same distance apart from each other at both sides of the main word lines 11 and 12 in the same active region A_TR 1 -A_TR 8 .
- Reference to the contacts 22 and 24 includes contacts 22 A- 22 D and contacts 24 A- 24 D.
- a first transistor P 11 may include a first gate G 1 located in the first active region A_TR 1 and first contacts 22 A and 24 A may be disposed at both sides of the first gate G 1 .
- a second transistor P 12 may include a second gate G 2 located in the second active region A_TR 2 adjacent to the first active region A_TR 1 in the first direction, and second contacts 22 B and 24 B located at both sides of the second gate G 2 .
- a third transistor P 21 may include a third gate G 3 located in a third active region A_TR 5 adjacent to the first active region A_TR 1 in the second direction, and third contacts 22 C and 24 C located at both sides of the third of the third gate G 3 .
- a fourth transistor P 22 may include a fourth gate G 4 located in a fourth active region A_TR 6 adjacent to the third active region A_TR 5 in the first direction, and fourth contacts 22 D and 24 D located at both sides of the fourth gate G 4 .
- the metal contacts 22 and 24 are spaced apart from the gates G by the same distance, such that the respective transistors P 11 -P 24 may have the same operating characteristics.
- FIG. 4 is a structural diagram illustrating not only the layout structure of FIG. 3 , but also sub word lines and metal pads 32 coupled to a pickup contact 26 .
- the sub word lines ⁇ circle around ( 1 ) ⁇ - ⁇ circle around ( 8 ) ⁇ may be coupled to the active regions A_TR 1 -A_TR 8 through the metal contacts 24 , and may be coupled to word lines of each mat (MAT) in which memory cells are formed.
- the sub word lines ⁇ ⁇ ⁇ may be formed as metal lines MO disposed over the main word lines 11 and 12 .
- the sub word lines ⁇ ⁇ ⁇ may be formed to extend in the diagonal direction at upper portions of the pickup regions PU 1 and PU 2 in the same manner as in the main word lines 11 and 12 , such that a space in which the metal pad 32 coupled to the contact 26 can be formed is guaranteed at an upper portion of the contact 26 of the pickup regions PU 1 and PU 2 .
- the embodiments of the present disclosure can form a well pickup active region in a PMOS region of the sub word line driver without increasing the region of the sub word line driver.
- Embodiments of the present disclosure can have a same distance between a gate and a contact of transistors in a PMOS region of the sub word line driver, such that the corresponding transistors can have the same operation characteristics.
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Abstract
Description
- The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application No. 10-2016-0179757 filed on Dec. 27, 2016, the disclosure of which is hereby incorporated by reference in its entirety.
- Embodiments of the present disclosure relate to a sub word line driver of a semiconductor memory device, and more particularly to a layout of forming a well pickup in a PMOS region of a sub word line driver.
- Generally, a semiconductor memory device includes a plurality of memory cells and a circuit for controlling the memory cells.
-
FIG. 1 is a conceptual diagram illustrating an arrangement structure of cell mats MATs for use in a general semiconductor memory device. - Referring to
FIG. 1 , the semiconductor memory device includes a plurality of mats MATs, each of which includes array-shaped memory cells for storing data. Each mat MAT may include a bit-line sense amplifier BLSA arranged in a row direction to sense/amplify cell data, and a plurality of sub word line drivers SWDs arranged in a column direction to enable sub word lines coupled to gates of cell transistors. - In this case, the respective sub word line drivers SWDs may operate word lines WLs of the right and left cell mats MATs.
-
FIG. 2 is a circuit diagram illustrating a general sub word line driver. - Referring to
FIG. 2 , the sub word line driver may be formed in a sub word line driver array shape which respectively outputs the sub word line drive signals SWL0 □ SWL3 and SWL4 □ SWL7 in response to main word line drive signals MWLB0 and MWLB1 and word line selection signals FX0, FX2, FX4, and FX6. In this case, the respective sub word line drivers may have the same structure in the remaining parts other than input/output (I/O) signals. - Representatively, the structure of the respective sub word line drivers will hereinafter be described using a sub word line driver of a first stage.
- Each sub word line driver may include a PMOS transistor P11 and NMOS transistors N11 and N12. The PMOS transistor P11 and the NMOS transistor N11 may be coupled in series between an input terminal of a word line selection signal FX0 and an input terminal of a back-bias voltage VBBW (or ground voltage VSS), and may receive a main word line drive signal MWLB0 through a common gate terminal. The NMOS transistor N12 may be coupled in series between an output terminal of a sub word line drive signal SWL0 and the back-bias voltage VBBW (or ground voltage VSS) input terminal, and may receive an inversion signal FXB0 of the word line selection signal FX0 through a gate terminal thereof.
- In the above-mentioned structure, a regional gain gradually increases in proportion to the increasing size of the sub word line driver, such that a minimum-sized sub word line driver must be arranged in the semiconductor memory device.
- However, the conventional art has difficulty in forming a well pickup active region in a PMOS region while simultaneously reducing the region of a sub word line driver, such that the conventional art unavoidably shares well pickup active regions of the other regions.
- Various embodiments of the present disclosure are directed to providing a sub word line driver of a semiconductor memory device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
- An embodiment of the present disclosure relates to a sub word line driver for preventing an increase of the region of a sub word line driver by improving a structure of a sub word line, resulting in formation of a well pickup active region in a PMOS region.
- In accordance with an aspect of the present disclosure, a sub word line driver of a semiconductor memory device includes: a plurality of first active regions arranged in a line shape in a first direction; a plurality of second active regions spaced apart from the plurality of first active regions a predetermined distance in a second direction, and arranged in a line shape in the first direction; a first main word line disposed over the first active regions, and formed in a diagonal direction in the first active regions; a second main word line disposed over the second active regions, and formed in a diagonal direction in the second active regions; and a pickup active region disposed between the first main word line and the second main word line.
- In accordance with another aspect of the present disclosure, a sub word line driver of a semiconductor memory device includes: a first transistor including a first gate located in a first active region and first contacts disposed at both sides of the first gate; a second transistor including a second gate located in a second active region adjacent to the first active region in a first direction, and second contacts located at both sides of the second gate; a third transistor including a third gate located in a third active region adjacent to the first active region in a second direction, and third contacts located at both sides of the third gate; a fourth transistor including a fourth gate located in a fourth active region adjacent to the third active region in the first direction, and fourth contacts located at both sides of the fourth gate; and a pickup active region disposed among the first to fourth active regions.
- It is to be understood that both the foregoing general description and the following detailed description of embodiments are exemplary and explanatory.
- The above and other features and advantages of the present disclosure will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:
-
FIG. 1 is a conceptual diagram illustrating a prior art arrangement structure of cell mats MATs for use in a general semiconductor memory device. -
FIG. 2 is a conceptual diagram illustrating prior art sub word lines SWLs arranged in the cell mats MATs. -
FIG. 3 is a structural diagram illustrating a layout structure of a PMOS region in the sub word line driver according to an embodiment of the present disclosure. -
FIG. 4 is a structural diagram illustrating not only the layout structure ofFIG. 3 , but also sub word lines and metal pads coupled to a pickup contact. - Reference will now be made in detail to certain embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. In the following description, a detailed description of related known configurations or functions incorporated herein will be omitted when it may make the subject matter less clear.
-
FIG. 3 is a structural diagram illustrating a layout structure of a PMOS region of a sub word line driver according to an embodiment of the present disclosure. - Referring to
FIG. 3 , a PMOS region of the sub word line driver includes a plurality of active regions A_TR1 □ A_TR8 in which transistors P11 □ P24 are formed, and a plurality of pickup active regions A_PU1 and A_PU2 in which pickup regions PU1 and PU2 are formed. - The active regions A_TR1 □ A_TR4 (for example, first group of active regions) may be spaced apart from each other a predetermined distance in a first direction (X direction). The active regions A_TR5 □ A_TR8 (for example, second group of active regions) may also be spaced apart from each other a predetermined distance in the first direction, and may be spaced apart from the active regions A_TR1 □ A_TR4 a predetermined distance in a second direction (Y direction).
- The pickup active regions A_PU1 and A_PU2 may be used as pickup regions for applying a bulk bias to an N well in which PMOS transistors P11 □ P24 are formed, in a word line driver, and the pickup active regions A_PU1 and A_PU2 may be coupled to a
contact 26 for receiving a back-bias voltage VBBW or a ground voltage. The pickup active regions A_PU1 and A_PU2 may be spaced apart from each other a predetermined distance in the first direction, and may be enclosed by the active regions A_TR1 □ A_TR8. For example, the pickup active region A_PU1 may be formed in a diamond (or lozenge) shape, and may be enclosed by four active regions A_TR1, A_TR2, A_TR5, and A_TR6. In addition, the pickup active region A_PU2 may also be formed in a diamond shape, and may be enclosed by four active regions A_TR3, A_TR4, A_TR7, and A_TR8. - A
main word line 11 may be disposed over the active regions A_TR1-A_TR4, and amain word line 12 may be disposed over the active regions A_TR5-A_TR8. In themain word lines FIG. 2 . The gates designated by G include all gates including gates G1-G4. - Specifically, the parts (i.e., the gates of the respective PMOS transistors P11-P24) formed to overlap the active regions A_TR1-A_TR8 in the
main word lines main word lines main word lines main word lines FIG. 3 which are denoted by dotted lines for convenience of description and better understanding of the present disclosure, regions of the PMOS transistors P11-P24 are not limited thereto. - As described above, the
main word lines main word lines main word line 11 is formed, but also two adjacent active regions (A_TR5 and A_TR6, A_TR7 and A_TR8) in which themain word line 12 is formed, the pickup active regions A_PU1 and A_PU2 for forming the pickup regions PU1 and PU2 may be formed between every two adjacent active regions. In one example, the pickup active region A_PU1 is disposed between a first active region A_TR1 and a sixth active region A_TR6 and a second active region A_TR2 and a fifth active region A_TRS. - In addition, gates G of the respective PMOS transistors P11 □ P24 are formed in a diagonal direction, such that the length of each gate G can be more freely elongated or shortened and the width of each transistor can be more freely enlarged as compared to the other case in which each gate G is formed in a horizontal or vertical direction.
- In the respective active regions A_TR1 □ A_TR8,
metal contacts 22 for receiving main word line selection signals FX0, FX2, FX4, and FX6 andother metal contacts 24 coupled to sub word lines {circle around (1)}-{circle around (8)} may be respectively located at both sides of the main word lines 11 and 12. - In this case, a diagonal direction of the
metal contacts contacts metal contacts contacts contacts 22A-22D andcontacts 24A-24D. - In the respective PMOS transistors P11-P24, gates G are formed in a direction diagonal to the first direction and the second direction,
metal contacts metal contacts first contacts second contacts metal contacts -
FIG. 4 is a structural diagram illustrating not only the layout structure ofFIG. 3 , but also sub word lines andmetal pads 32 coupled to apickup contact 26. - Referring to
FIG. 4 , the sub word lines {circle around (1)}-{circle around (8)} may be coupled to the active regions A_TR1-A_TR8 through themetal contacts 24, and may be coupled to word lines of each mat (MAT) in which memory cells are formed. The sub word lines □ □ □ may be formed as metal lines MO disposed over the main word lines 11 and 12. - Moreover, the sub word lines □ □ □ may be formed to extend in the diagonal direction at upper portions of the pickup regions PU1 and PU2 in the same manner as in the main word lines 11 and 12, such that a space in which the
metal pad 32 coupled to thecontact 26 can be formed is guaranteed at an upper portion of thecontact 26 of the pickup regions PU1 and PU2. - As is apparent from the above description, the embodiments of the present disclosure can form a well pickup active region in a PMOS region of the sub word line driver without increasing the region of the sub word line driver.
- Embodiments of the present disclosure can have a same distance between a gate and a contact of transistors in a PMOS region of the sub word line driver, such that the corresponding transistors can have the same operation characteristics.
- Those skilled in the art will appreciate that embodiments of the present disclosure may be carried out in other ways than those set forth herein without departing from the spirit and essential characteristics of these embodiments. The above embodiments are therefore to be construed in all aspects as illustrative and not restrictive.
- The above embodiments of the present disclosure are illustrative and not limitative. Various alternatives and equivalents are possible. The above embodiments are not limited by the type of deposition, etching polishing, and patterning steps described herein. Nor is the embodiment limited to any specific type of semiconductor device. For example, the present disclosure may be implemented in a dynamic random access memory (DRAM) device or non volatile memory device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.
Claims (15)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR1020160179757A KR102660230B1 (en) | 2016-12-27 | 2016-12-27 | Sub-wordline driver of semiconductor device |
KR10-2016-0179757 | 2016-12-27 |
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US10008256B1 US10008256B1 (en) | 2018-06-26 |
US20180182448A1 true US20180182448A1 (en) | 2018-06-28 |
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US15/691,945 Active US10008256B1 (en) | 2016-12-27 | 2017-08-31 | Sub word line driver of semiconductor memory device |
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KR20230056119A (en) * | 2021-10-19 | 2023-04-27 | 삼성전자주식회사 | Sub wordline driver and memory device having the same |
US11990175B2 (en) | 2022-04-01 | 2024-05-21 | Micron Technology, Inc. | Apparatuses and methods for controlling word line discharge |
CN117316218A (en) * | 2022-06-24 | 2023-12-29 | 长鑫存储技术有限公司 | Word line driver and memory device |
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