KR20120087665A - Semiconductor memory apparatus - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to reduce an area of a semiconductor chip by reducing areas of a sub hole and a sub word line driver. CONSTITUTION: A plurality of mats(MAT(A),MAT(B)) include a plurality of memory cells. A plurality of bit line sense amplifiers amplify memory cell data. A plurality of sub word line drivers are arranged in a column direction of each mat and selects a sub word line connected to a gate of a memory cell transistor comprising each mat. A plurality of sub holes(S/H(A),S/H(B)) includes a switching device which is arranged in an intersection of a plurality of bit line sense amplifiers and the plurality of the sub word line drivers and switches a segment input and output line connected to the bit line sense amplifier.

Description

Semiconductor memory device {SEMICONDUCTOR MEMORY APPARATUS}

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of increasing the number of semiconductor chips per wafer.

In general, a semiconductor memory device is composed of a plurality of memory cells and a circuit for controlling them. A structure in which a plurality of memory cells of such a general semiconductor memory device are arranged will be described with reference to FIG. 1.

1 is a diagram illustrating a cell array structure of a general semiconductor memory device.

Referring to FIG. 1, a general semiconductor memory device includes a plurality of mats MATs, a plurality of bit line sense amplifiers BLSA and a plurality of mats disposed in a row direction of each mat MAT to amplify cell data. A plurality of sub word line drivers SWD for driving a sub word line (not shown) connected to a gate of a cell transistor (not shown) are disposed in the column direction of the MAT.

In addition, a segment input / output line SIO (not shown) connected to the bit line sense amplifier BLSA is formed at an intersection area where the bit line sense amplifier BLSA and the sub word line driver SWD meet, that is, the sub hole S / H. The switch element which can switch) is arrange | positioned.

However, with the recent increase in the degree of integration of semiconductor memory devices, the number of data input / output lines has increased exponentially. For example, DDR2 devices require two to eight data input / output lines, while DDR3 devices require eight to sixteen data input / output lines. As such, when the number of data input / output lines is increased, the area of the area where the data input / output lines are arranged also increases in proportion to the number. Accordingly, the area of the sub word line driver (SWD) area whose area is determined by the number of data input / output lines is also increased, and there is a limit in increasing the number of semiconductor chips per wafer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of increasing the number of semiconductor chips per wafer by changing the semiconductor cell array structure to reduce the semiconductor chip area.

A semiconductor memory device according to the present invention includes a plurality of mats including a plurality of memory cells, a plurality of bit line sense amplifiers arranged in a row direction of each mat to amplify memory cell data constituting the mats, A plurality of sub word line drivers and a plurality of bit line sense amplifiers and the plurality of sub word line drivers for selecting sub word lines arranged in the column direction of the mat and connected to the memory cell transistor gates forming the mats; A plurality of sub-holes disposed in an area and having a switching element for switching a segment input / output line connected to the bit line sense amplifier, wherein the plurality of sub-holes are disposed adjacent to one of the mats and the one of the mats; Another mat is arranged in contact with each other All.

The semiconductor memory device according to the present invention can reduce the area of the semiconductor chip by reducing the area of the sub word line driver and the sub holes that are disposed between two adjacent mats among the plurality of mats.

Accordingly, the semiconductor memory device according to the present invention can increase the number of semiconductor chips per wafer, thereby improving the cost competitiveness.

1 is a diagram illustrating a cell array structure of a general semiconductor memory device; and
2 to 4 are diagrams illustrating a cell array structure of a semiconductor memory device according to an embodiment of the present invention.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, one embodiment of the present invention may be modified in various forms, and the scope of the present invention should not be construed as being limited due to the embodiments described below. One embodiment of the present invention is provided to more easily explain the present invention to those skilled in the art.

2 is a diagram illustrating a cell array structure of a semiconductor memory device according to an embodiment of the present invention.

2, a semiconductor memory device according to an embodiment of the present invention includes a plurality of mats MAT (A) and MAT (B). At this time, the mat MAT may be composed of a plurality of memory cells (not shown), and the plurality of sub word lines SWL for selecting the plurality of memory cells are spaced apart from each other at a predetermined interval. Extend in the row direction.

In addition, the semiconductor memory device according to the embodiment of the present invention is disposed at both edges parallel to the row direction of each mat MAT (A) and MAT (B) or parallel to the sub word line SWL to amplify the memory cell data. A plurality of bit line sense amplifiers (BLSA (A), BLSA (A '), BLSA (B), BLSA (B')), and the column directions or subs of each mat (MAT (A), MAT (B)). A plurality of sub word line drivers SWD (A) and SWD (B) for selecting a sub word line SWL connected to a gate of a memory cell transistor (not shown) at both edges perpendicular to the word line SWL. And the plurality of bit line sense amplifiers BLSA (A), BLSA (A '), BLSA (B), BLSA (B') and the plurality of sub word line drivers SWD (A) and SWD (B). Sub-holes S / H (A), S / H (A '), S / H (B), and S / H (B') are arranged in the region where is crossed. In this case, one of the mats MAT (A) and MAT (B) is adjacent to the mat MAT (A), hereinafter referred to as “first mat” and the first mat MAT (A). The other mats (MAT (B), hereinafter referred to as 'second mats') are disposed in contact with each other. That is, the sub includes a bit line sense amplifier BLSA disposed between the first mat MAT (A) and the second mat MAT (B) and a switch element SW for switching segment input / output lines. The hole S / H is not arranged.

Accordingly, in one embodiment of the present invention, the sub word lines SWL disposed on the first mat MAT (A) and the second mat MAT (B) are each sub word line driver SWD, that is, It is selected by the first sub word line driver (SWD (A)) and the second sub word line driver (SWD (B)).

In addition, in one embodiment of the present invention, the switch element SW disposed in the sub-hole S / H is disposed in the bit line sense amplifier BLSA region.

As described above, in the semiconductor memory device according to the embodiment, the sub word line driver SWD and the sub hole S disposed between the first mat MAT (A) and the second mat MAT (B). Since there is no need to arrange / H), the area of the area where the existing sub word line driver SWD and the sub hole S / H are disposed can be minimized, thereby increasing the number of semiconductor chips per wafer.

Meanwhile, in the semiconductor memory device according to an embodiment of the present invention, as shown in FIG. 3, a dummy cell is disposed between the first mat MAT (A) and the second mat MAT (B). Can be placed. In this case, the dummy cell may be configured as a redundancy cell, or may be configured as a logic circuit when the redundancy cell is also defective. In this configuration, the sub word lines SWL disposed on the first mat MAT (A) and the second mat MAT (B) are each sub word line driver SWD, that is, the first sub word line. The switch element SW selected by the driver SWD (A) and the second sub word line driver SWD (B) and disposed in the sub-hole S / H is placed in the bit line sense amplifier BLSA region. Is placed.

In addition, as shown in FIG. 4, a semiconductor memory device according to an embodiment of the present invention may include a dummy cell between a first mat MAT (A) and a second mat MAT (B). In this case, the dummy cell may be configured as a redundancy cell, or may be configured as a logic circuit when the redundancy cell is also defective when repaired. A)) and the sub word line SWL disposed on the second mat MAT (B) are each sub word line driver SWD, that is, the first sub word line driver SWD (A) and the second sub. The switch element SW selected by the word line driver SWD (B) and arranged in the sub-hole S / H is arranged in the input / output switch IOSW region, where the input / output switch IOSW region is conventionally It is formed smaller than the area of the sub-holes S / H.

As described above, the semiconductor memory device according to the embodiment may reduce the area of the semiconductor chip by reducing the area of the sub word line driver SWD and the sub hole S / H, thereby increasing the number of semiconductor chips per wafer. .

Claims (6)

A plurality of mats including a plurality of memory cells;
A plurality of bit line sense amplifiers arranged in a row direction of each mat to amplify memory cell data constituting each mat;
A plurality of sub word line drivers arranged in a column direction of each mat to select sub word lines connected to memory cell transistor gates forming the mats; And
And a plurality of sub-holes disposed in an area where the plurality of bit line sense amplifiers and the plurality of sub word line drivers cross each other and having switching elements for switching segment input / output lines connected to the bit line sense amplifiers.
Any one mat of the plurality of mats and another mat disposed adjacent to any one of the mats,
A semiconductor memory device, characterized in that arranged in contact with each other. The method of claim 1,
And a dummy cell disposed at a portion where the mat and the mat are in contact with each other. The method of claim 1,
A dummy cell disposed at a portion where the one mat and the another mat are in contact with each other; And
An input / output switch disposed at a portion where the dummy cell and the bit line sense amplifier cross each other and switching the segment input / output line connected to the bit line sense amplifier;
The semiconductor memory device further comprises. The method of claim 1, wherein the bit line sense amplifier region,
And a switching element for switching the segment input and output lines. The method of claim 2, wherein the dummy cell,
And a redundancy cell. The method of claim 2, wherein the dummy cell,
And a redundancy circuit comprising a logic circuit if the redundancy circuit is defective.

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