WO2024037118A1 - 半导体结构的形成方法及半导体结构 - Google Patents

半导体结构的形成方法及半导体结构 Download PDF

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Publication number
WO2024037118A1
WO2024037118A1 PCT/CN2023/097754 CN2023097754W WO2024037118A1 WO 2024037118 A1 WO2024037118 A1 WO 2024037118A1 CN 2023097754 W CN2023097754 W CN 2023097754W WO 2024037118 A1 WO2024037118 A1 WO 2024037118A1
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WIPO (PCT)
Prior art keywords
layer
trench
forming
bit line
semiconductor structure
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PCT/CN2023/097754
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English (en)
French (fr)
Inventor
郭帅
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长鑫科技集团股份有限公司
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Publication of WO2024037118A1 publication Critical patent/WO2024037118A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Definitions

  • the present disclosure relates to, but is not limited to, a method of forming a semiconductor structure and a semiconductor structure.
  • the present disclosure provides a method for forming a semiconductor structure and a semiconductor structure.
  • a first aspect of the present disclosure provides a method for forming a semiconductor structure.
  • the method for forming a semiconductor structure includes:
  • the stacked structure is located on the surface of the substrate, the stacked structure includes alternately stacked sacrificial layers and support layers;
  • bit lines are formed at positions corresponding to part of the sacrificial layer.
  • the bit lines extend along the second direction, and in the third direction, adjacent bit lines are arranged at intervals;
  • each of the active layers is on the same layer as each of the bit lines, and is formed on the side of each of the bit lines, and a first end of each of the active layers and each of the bit lines are formed on the same layer. the bit line connections;
  • the capacitor structure is formed at the second end of the active layer, and the capacitor structure is connected to each of the active layers;
  • a plurality of word lines are formed, each of the word lines is vertically connected to each of the active layers, and the word lines cover part of the sidewall of each of the active layers.
  • part of the sacrificial layer is removed, including:
  • first trench Forming a first trench, the first trench is located in the middle area of the laminated structure, the first trench extends along the second direction and penetrates the laminated structure; the side walls of the first trench exposing each said sacrificial layer and each said support layer;
  • the material of the sacrificial layer has a high etching selectivity ratio relative to the material of the support layer.
  • multiple bit lines are formed at positions corresponding to the removed part of the sacrificial layer, including:
  • bit line material layer that covers the surface of the barrier layer and fills each of the bit line trenches and the first trench
  • the barrier layer and the bit line material layer in the first trench are removed, and the barrier layer and the bit line material layer located in the same bit line trench are retained to form the bit line.
  • the stacked structure in the first direction, includes a first region close to the bit line and a second region far away from the bit line;
  • Multiple active layers are formed, including:
  • a first etching hole is formed at a position corresponding to the removed sacrificial layer, and in the second direction, the first etching hole penetrates the a second region extends to the first region and exposes the bit line;
  • Conductive material is filled into the first etching holes, part of the filling material is removed, and the active layer is formed in each of the first etching holes located in the first area.
  • removing part of the filling material and forming the active layer in each of the first etching holes located in the first area includes:
  • forming the capacitor structure includes:
  • the capacitor structure includes a plurality of extension structures, each extension structure is located in each first etching hole in the second area, the extension structure extends along the first direction and is connected with each The active layer contacts are connected.
  • the capacitor structure is formed, including:
  • a semiconductor layer is formed, covering the upper electrode layer and filling the third trench and the first etching hole located in the second region.
  • multiple word lines are formed, including:
  • a word line material is formed.
  • the word line material covers the gate oxide layer and fills the word line trench.
  • the word line material located in the same word line trench forms the word line.
  • the method of forming the semiconductor structure further includes:
  • a dielectric layer is formed in the first trench, and the dielectric layer fills the first trench.
  • the bit lines are located on both sides of the dielectric layer and are in contact with the dielectric layer.
  • the method of forming the semiconductor structure further includes:
  • the sacrificial layer and the sidewalls of the bit line form a plurality of bit line steps on the end surface of the stacked step, and the bit line steps include a plurality of bit lines distributed at intervals in the third direction, The lengths of the plurality of bit lines gradually increase along the direction from the top surface to the bottom surface of the substrate.
  • the method of forming the semiconductor structure further includes:
  • An isolation layer is formed, and the isolation layer covers surfaces of a plurality of bit lines and a plurality of word lines.
  • the method of forming the semiconductor structure further includes:
  • bit line contact plugs Forming a plurality of bit line contact plugs, the plurality of bit line contact plugs are respectively connected to the plurality of bit lines in one-to-one correspondence;
  • a plurality of word line contact plugs are formed, and the plurality of word line contact plugs are respectively connected to the plurality of word lines in one-to-one correspondence, wherein the plurality of bit line contact plugs are in contact with the plurality of word lines. Plugs are formed in the isolation layer.
  • the method for forming the semiconductor structure further includes:
  • a substrate isolation layer is formed between the substrate and the stacked structure.
  • a second aspect of the present disclosure provides a semiconductor structure, the semiconductor structure comprising:
  • a plurality of bit lines, each of the bit lines extending along the second direction, and the plurality of bit lines are spaced apart in the third direction;
  • each of the active layers is on the same layer as each of the bit lines and is located on the side of each of the bit lines, and the first end of each of the active layers and each of the bit lines Bit line connection;
  • the capacitor structure is formed at the second end of the active layer, and the capacitor structure is connected to each of the active layers;
  • a plurality of word lines are arranged at intervals in the second direction, each of the word lines is vertically connected to each of the active layers, and the word lines cover part of the sidewall of each of the active layers. .
  • the capacitor structure includes a plurality of extension structures, the extension structures extend along the first direction and are electrically connected to each of the active layers located in the first direction.
  • the semiconductor structure also includes:
  • a plurality of bit line contact plugs are respectively connected to a plurality of bit lines in a one-to-one correspondence; wherein the length of the plurality of bit lines is along the top surface to the bottom surface of the substrate. The direction gradually increases;
  • a plurality of word line contact plugs are connected to a plurality of word lines in a one-to-one correspondence.
  • FIG. 1 is a flowchart of a method of forming a semiconductor structure according to an exemplary embodiment.
  • FIG. 2 is a schematic diagram of a substrate and a stacked structure during formation of a semiconductor structure according to an exemplary embodiment.
  • FIG. 3 is a schematic diagram after forming a first mask layer during the formation of a semiconductor structure according to an exemplary embodiment.
  • FIG. 4 is a schematic diagram illustrating the formation of bit line trenches during the formation of a semiconductor structure according to an exemplary embodiment.
  • FIG. 5 is a cross-sectional view along the A-A section in FIG. 4 .
  • FIG. 6 is a cross-sectional view of the A-A section of the structure shown in FIG. 4 after forming a barrier layer.
  • FIG. 7 illustrates a schematic diagram of forming a bit line material layer during the formation of a semiconductor structure according to an exemplary embodiment.
  • FIG. 8 is a schematic diagram illustrating the removal of the bit line material layer in the first trench during the formation of the semiconductor structure according to an exemplary embodiment.
  • FIG. 9 is a cross-sectional view of the C-C section in FIG. 8 .
  • FIG. 10 is an enlarged view of area A in FIG. 9 .
  • FIG. 11 is a schematic diagram of forming a dielectric layer in a first trench during the formation of a semiconductor structure according to an exemplary embodiment.
  • FIG. 12 is a schematic diagram of forming a second mask layer during the formation of a semiconductor structure according to an exemplary embodiment.
  • FIG. 13 is a schematic diagram of forming a second trench during the formation of a semiconductor structure according to an exemplary embodiment.
  • FIG. 14 is a cross-sectional view of the B-B section of the structure shown in FIG. 13 after forming a filling material layer.
  • FIG. 15 is a schematic diagram of forming a third mask layer during a method for forming a semiconductor structure according to an exemplary embodiment.
  • FIG. 16 is a schematic diagram of forming a third trench during a method of forming a semiconductor structure according to an exemplary embodiment.
  • FIG. 17 is a cross-sectional view of the D-D section of FIG. 16 .
  • FIG. 18 is a schematic diagram of forming a conductive material layer during a method of forming a semiconductor structure according to an exemplary embodiment.
  • FIG. 19 is a schematic diagram after forming an active layer during a method for forming a semiconductor structure according to an exemplary embodiment.
  • FIG. 20 is a cross-sectional view along the E-E section of FIG. 19 .
  • FIG. 21 is a schematic diagram of forming a lower electrode layer during a method for forming a semiconductor structure according to an exemplary embodiment.
  • FIG. 22 is a cross-sectional view along the line E-E of FIG. 21 .
  • FIG. 23 is a schematic diagram of forming a capacitor structure during a method of forming a semiconductor structure according to an exemplary embodiment.
  • FIG. 24 is a partial enlarged view of area B in FIG. 23 .
  • FIG. 25 is a schematic diagram of forming a fourth mask layer during a method for forming a semiconductor structure according to an exemplary embodiment.
  • FIG. 26 is a schematic diagram of forming a word line trench during a method of forming a semiconductor structure according to an exemplary embodiment.
  • Fig. 27 is a cross-sectional view taken along the line F-F in Fig. 26 .
  • FIG. 28 is a partial enlarged view of area C in FIG. 27 .
  • FIG. 29 is a schematic diagram of forming a word line during a method of forming a semiconductor structure according to an exemplary embodiment.
  • FIG. 30 is a schematic diagram of forming a fifth mask layer during a method of forming a semiconductor structure according to an exemplary embodiment.
  • 31 is a schematic diagram of forming stacking steps and bit line steps during a method for forming a semiconductor structure according to an exemplary embodiment.
  • 32 is a schematic diagram of forming bit line contact plugs and word line contact plugs during a method of forming a semiconductor structure according to an exemplary embodiment.
  • Fig. 33 is a cross-sectional view taken along G-G section of Fig. 32.
  • FIG. 34 is a flow chart illustrating a method of forming a semiconductor structure according to an exemplary embodiment.
  • Substrate 110. Substrate isolation layer; 20. First mask layer; 201. First opening pattern; 202. First stacked layer; 203. Second stacked layer; 204. Third stacked layer; 205. The fourth stack; 206, the fifth stack; 200, stack structure; D1, first region; D2, second region; 210, support layer; 220, sacrificial layer; 230, first trench; 240, third Second trench; 250, filling material layer; 260, third trench; 270, first etching hole; 280, stacked ladder; 30, third mask layer; 300, bit line; 301, third opening pattern ; 310. Bit line slot; 320. Barrier layer; 330. Bit line material layer; 340. Bit line contact hole; 350.
  • FIG. 1 shows a flow chart of a method for forming a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • FIG. 2- Figure 33 is a schematic diagram of each stage of a method for forming a semiconductor structure. The method for forming a semiconductor structure will be introduced below with reference to Figures 2-33.
  • This embodiment does not limit the semiconductor structure.
  • the following will take the three-dimensional structure of the semiconductor structure as a dynamic random access memory (Dynamic Random Access Memory, DRAM) as an example.
  • DRAM Dynamic Random Access Memory
  • this embodiment is not limited to this.
  • the semiconductor structure in can also be other structures.
  • a method for forming a semiconductor structure includes the following steps:
  • Step S102 Provide a substrate and a stacked structure.
  • the stacked structure is located on the surface of the substrate.
  • the stacked structure includes alternately stacked sacrificial layers and support layers.
  • the substrate 100 serves as a support component of the memory to support other components located on it.
  • the substrate 100 can be made of a semiconductor material, and the semiconductor material can be silicon, germanium, or silicon germanium. compound and one or more of silicon-carbon compounds.
  • Substrate 100 includes source regions, drain regions, and other interconnect structures.
  • the stacked structure 200 is located above the surface of the substrate 100 (ie, the top surface of the substrate). Based on the orientation shown in FIG. 2 , along the direction from bottom to top, the stacked structure 200 is sequentially
  • the support layer 210 and the sacrificial layer 220 are stacked. Specifically, the bottom layer of the laminated structure 200 is the support layer 210 , and the top layer of the laminated structure 200 is the support layer 210 .
  • the sacrificial layer 220 between two adjacent support layers 210 can be a placeholder for other structures.
  • the sacrificial layer 220 can be an oxide, such as silicon oxide.
  • the etching rate of the material forming the support layer 210 is lower than the etching rate of the material forming the sacrificial layer 220.
  • the support layer 210 is a nitride, such as silicon nitride.
  • a substrate isolation layer 110 is formed on the surface of the substrate 100 , and then a stacked structure 200 is formed on the surface of the substrate isolation layer 110 , so that the substrate isolation layer 110 can be used as an etching stop.
  • a layer such as substrate isolation layer 110 is silicon oxycarbide SiOC.
  • Step S104 Remove part of the sacrificial layer, and form multiple bit lines at positions corresponding to part of the sacrificial layer.
  • the bit lines extend along the second direction Y, and in the third direction, adjacent bit lines are spaced apart.
  • bit lines 300 are formed in place of the sacrificial layer 220 .
  • each bit line 300 is located between two adjacent support layers 210 , and multiple support layers 210 separate the multiple bit lines 300 .
  • each bit line 300 extends along the second direction Y.
  • both the first direction X and the second direction Y are directions parallel to the substrate 100 , where there is a right angle between the first direction direction.
  • the bit line 300 is located in the middle of the stacked structure 200 in the first direction Preparation for three-dimensional stacking of semiconductor devices to improve the integration of semiconductor devices.
  • the thickness of the sacrificial layer can be controlled to control the thickness of the bit line.
  • the bit lines may include doped semiconductor materials, conductive metal nitrides, metals (eg, uncombined metal materials), or metal-semiconductor compounds.
  • bit lines may be accomplished by the following steps:
  • Step S1041 Form a first trench.
  • the first trench is located in the middle area of the stacked structure.
  • the first trench extends along the second direction and penetrates the stacked structure. Sidewalls of the first trench expose each sacrificial layer and each support layer.
  • Step S1042 Etch the exposed sacrificial layer along the first direction to remove part of the sacrificial layer.
  • Step S1043 Form a bit line trench at a position corresponding to the removed portion of the sacrificial layer, and the bit line trench extends along the second direction.
  • Step S1044 Form a barrier layer on the surface of each bit line trench and the first trench, and the barrier layer covers the trench wall of the bit line trench and the side wall of the first trench.
  • Step S1045 Form a bit line material layer, which covers the surface of the barrier layer and fills each bit line trench and the first trench.
  • Step S1046 Remove the barrier layer and bit line material layer in the first trench, and retain the barrier layer and bit line material layer in the same bit line trench to form a bit line.
  • Step 1047 Form a dielectric layer in the first trench.
  • the dielectric layer fills the first trench.
  • the bit lines are located on both sides of the dielectric layer and are in contact with the dielectric layer.
  • a patterned first mask layer 20 is formed above the stacked structure 200 .
  • the first mask layer 20 includes a first opening pattern 201 .
  • the first opening pattern 201 extends along the second direction Y.
  • the stacked structure 200 is etched along the first opening pattern 201 and penetrates the stacked structure 200 along the thickness direction of the stacked structure 200 to form a first trench 230 in the stacked structure 200 .
  • the sidewalls of the first trench 230 expose the sidewalls of each support layer 210 and the sidewalls of each sacrificial layer 220 in the stacked structure 200 .
  • step S1042 as shown in FIG. 4, a portion of the sacrificial layer 220 is etched along the sidewalls of the exposed sacrificial layer 220 in a direction away from the first trench 230 to remove the portions on both sides of the first trench 230.
  • Bit lines 300 are formed at locations other than the sacrificial layer 220 (refer to FIG. 8 ).
  • step S1043 after removing part of the sacrificial layer 220 in the direction away from the first trench 230 on both sides of the first trench 230, the two adjacent support layers An opening is formed between 210.
  • the openings extend along the second direction Y parallel to the substrate 100 , and a bit line trench 310 is formed at a position corresponding to each opening.
  • the first trench 230 separates two bit line trenches 310 in the same layer from each other, so that bit lines 300 are formed on both sides of the first trench 230 in subsequent processes (refer to FIG. 8 ).
  • the material of the sacrificial layer has a high etching selectivity ratio relative to the material of the support layer, so that the etching rate of the support layer is much smaller than the etching rate of the sacrificial layer.
  • an opening with higher flatness is formed to form a bit line with a strip-shaped structure of uniform thickness.
  • a barrier layer 320 can be formed on the surface of each bit line trench 310 and the first trench 230 by physical vapor deposition, chemical vapor deposition, atomic layer deposition or epitaxial growth.
  • the barrier layer 320 continuously covers the top surface of the stacked structure 200 , the sidewalls of the first trench 230 and the surface of the bit line trench 310 .
  • the barrier layer 320 can effectively prevent the material forming the bit line in the subsequent process from penetrating into the stacked structure 200 , illustrative.
  • the material of the barrier layer 320 is, for example, titanium nitride.
  • a bit line material layer 330 is deposited in the unfilled area of the bit line trench 310.
  • the bit line material layer 330 covers the surface of the barrier layer 320 and fills the bit line trench.
  • a bit line material layer 330 is also deposited on the top surface of the stacked structure 200 .
  • the material of the bit line material layer 330 includes tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.
  • step S1046 as shown in FIGS. 6 and 7, part of the barrier layer 320 and part of the bit line material layer 330 are etched back together to remove the barrier layer 320 and the bit line material layer 330 located on the top surface of the stacked structure 200. , as well as the barrier layer 320 and the bit line material layer 330 in the first trench 230. As shown in Figures 8, 9 and 10, the barrier layer 320 and the bit line material layer 330 located in the bit line trench 310 are retained, and the barrier layer 320 and the bit line material layer 330 located in the same bit line trench 310 together form a bit line.
  • Line 300 is a strip-like structure or a line-like structure extending in the second direction Y.
  • a set of bit line groups is located on both sides of the first trench 230 , and each set of bit line groups includes a plurality of bit lines 300 spaced apart from each other in the third direction Z.
  • the dielectric layer 400 is deposited in the first trench 230 .
  • the dielectric layer 400 may also cover the top surface of the stacked structure 200 .
  • the dielectric layer 400 remains in the first trench 230 .
  • the material of the dielectric layer 400 is silicon oxide.
  • Step S106 Form multiple active layers. Each active layer is on the same layer as each bit line and is formed on the side of each bit line. The first end of each active layer is connected to each bit line.
  • an active layer 500 is formed correspondingly to each bit line 300 of each bit line group.
  • Each active layer 500 is formed on the side of each bit line 300 and has The source layer 500 and its corresponding bit line 300 are in the same layer.
  • the first end 501 of each active layer 500 is in contact with a side of each bit line 300 away from the first trench 230 (shown in FIG. 10 ) to form an electrical connection.
  • the formation of multiple active layers on one side of one of the bit line groups is used as an example for explanation.
  • the bit line 300 is located in the middle of the stacked structure 200 .
  • the other areas are marked as the second area D2.
  • the first region D1 is formed by a region close to the bit line 300 and extending along the second direction Y; the second region D2 is located outside the first region D1 and is adjacent to the first region D1 .
  • D2 also extends along the second direction Y.
  • forming multiple active layers may include the following steps:
  • Step S1061 Form a plurality of second trenches in the stacked structure, each second trench extending along the first direction and penetrating the stacked structure.
  • Step S1062 Form a filling material layer in each second trench, and the filling material layer fills the second trench.
  • Step S1063 Form a third trench in the second area, the third trench extends along the second direction and vertically intersects each second trench.
  • Step S1064 Remove part of the sacrificial layer based on the third trench, and form a first etching hole at a position corresponding to the removed sacrificial layer. In the second direction, the first etching hole extends through the second area to the first area and Exposed bit lines.
  • Step S1065 Fill the first etching hole with conductive material to form a conductive material layer.
  • Step S1066 Etch the conductive material layer located in the first etching hole in the second area based on the third trench, and retain part of the conductive material layer located in the first etching hole in the first area to form an active layer.
  • a patterned second mask layer 40 is formed on the surface of the stacked structure 200.
  • the second mask layer 40 includes a plurality of second opening patterns 401.
  • the plurality of second opening patterns 401 are spaced apart from each other in the second direction Y, each second opening pattern 401 extends along the first direction X, and the plurality of second opening patterns 401 are concentrated in the C area of the laminated structure 200, such as As shown in FIG. 12 , area C is a preset area extending along the second direction Y.
  • the length of the second opening pattern 401 is consistent with the length of the stacked structure 200 .
  • the total width of the plurality of second opening patterns 401 in the second direction Y is smaller than the total width of the stacked structure 200 in the second direction Y.
  • the stacked structure 200 is etched based on the second opening pattern 401 and penetrates the stacked structure 200 along the thickness direction of the stacked structure 200 to form a plurality of second trenches 240 .
  • the two trenches 240 expose part of the top surface of the substrate isolation layer 110 .
  • each second groove 240 vertically intersects the support layer 210 .
  • the second trench 240 extends along the first direction X through the first area D1 and the second area D2.
  • the bit lines 300 are not etched during the formation of the second trench 240, and each bit line 300 maintains a continuous strip or line structure in the second direction Y.
  • the second mask layer 40 is removed.
  • step 1062 filling material is then deposited in each second trench 240 until the second trench 240 is filled with filling material to form a filling material layer 250, thereby stacking Structure 200 is filled in preparation for subsequent processes.
  • the filling material layer 250 located in each second trench 240 connects each supporting layer 210 and the sacrificial layer 220 , and part of the sacrificial layer 220 remains between any adjacent filling material layer 250 and any In the space formed by two adjacent support layers 210, and extending along the first direction X.
  • the etching rate can be selected to be greater than that of the sacrificial layer.
  • the material with an etching rate of 220 is used as the filling material.
  • the filling material is silicon nitride, and the filling material can also be selected from the same material as the support layer 210 .
  • a patterned third mask layer 30 may be formed on the top surface of the stacked structure 200 and the top surface of the filling material layer 250.
  • the third mask layer 30 includes a pattern located in the second area.
  • the third opening pattern 301 in D2 extends along the second direction Y.
  • the stacked structure 200 is etched based on the third opening pattern 301 to form a third trench 260 in the second region D2 of the stacked structure 200 .
  • the third trench 260 runs through the stacked structure 200 along the thickness direction of the stacked structure 200 , and the third trench 260 exposes the sidewalls of the sacrificial layer 220 in the C region.
  • step S1064 as shown in FIGS. 16 and 17 , a dry etching process can be used to etch the sacrificial layer 220 located in the C region based on the third trench 260 to remove the sacrificial layer 220 between the two support layers 210 .
  • Layer 220, the first etching hole 270 is formed in the space corresponding to the removed sacrificial layer 220. In the first direction
  • step S1065 as shown in FIGS. 16, 17 and 18, conductive material is deposited into the first etching hole 270 to form the conductive material layer 50 until the first etching hole 270 is filled.
  • the conductive material will also cover the top surface of the stacked structure 200, and the chemical mechanical polishing (CMP, Chemical Mechanical Polishing) process and etching back can be used.
  • CMP Chemical Mechanical Polishing
  • the process processes excess conductive material and retains the conductive material located in the third trench 260 .
  • the conductive material is polysilicon material.
  • step S1066 as shown in FIGS. 18, 19 and 20, the conductive material layer 50 located in the third trench 260 is removed. Finally, the conductive material layer 50 located in the second region D2 in the C region is etched based on the third trench 260 to retain part of the conductive material layer 50 located in the first region D1 in the C region to form multiple active layers 500 .
  • the conductive material layer 50 retained in the first etching hole 270 forms an active layer 500 .
  • a plurality of active layers 500 are spaced apart from each other, and each active layer 500 is The bit lines 300 are in the same layer, the active layer 500 corresponds to the bit lines 300 one-to-one, and the first end 501 of each active layer 500 is electrically connected to the bit line 300 .
  • the first end 501 of the active layer 500 can be used as a source, and the second end 502 of the active layer 500 can be used as a drain to form an electrical connection with other structures, such as the second end of the active layer 500 .
  • Terminal 502 may be electrically connected to capacitor structure 600 (refer to FIG. 27).
  • Step S108 Form a capacitor structure.
  • the capacitor structure is formed at the second end of the active layer, and the capacitor structure is connected to each active layer.
  • a capacitor structure 600 is formed in the second region D2 of the stacked structure 200 .
  • the capacitor structure 600 is formed in the unfilled region of the third trench 260 and the unfilled region of the first etching hole 270 .
  • Capacitor structure 600 is formed on active layer 500 The second end 502 of the capacitor structure 600 is in contact with the second end 502 of the active layer 500 to form an electrical connection between the capacitor structure 600 and the second end 502 of the active layer 500 .
  • the main structure of the capacitor structure 600 is located in the third trench 260 and has a plurality of extension structures 610 on both sides of the third trench 260 .
  • Each extension structure 610 is respectively located in each first etching hole 270 in the second region D2, and each extension structure 610 extends along the first direction X to the second end 502 of the active layer 500.
  • one end of the extension structure 610 located in the same first etching hole 270 is connected to the main structure of the capacitor structure 600 , and the other end of the extension structure 610 is in contact with the second end 502 of the active layer 500 .
  • the plurality of extension structures 610 are spaced apart from each other in the third direction Z.
  • the conductive material layer located in the second region D2 is removed to form the main structure and extension structure of the capacitor structure 600 in the second region D2, thereby increasing the proportion of the capacitor structure in the semiconductor structure and improving Storage capabilities of semiconductor structures.
  • forming the capacitor structure may include the following steps:
  • Step S1081 Form a lower electrode layer to cover the sidewalls of the third trench and the sidewalls of the first etching hole located in the second region.
  • a lower electrode layer 601 is formed on the surface of the first etching hole 270 located in the second region D2 that is not covered by the active layer 500 and on the surface of the third trench 260 . In the first direction not shown).
  • the material of the lower electrode layer includes metal or metal nitride, such as: titanium, tantalum, copper, tungsten, cobalt, aluminum, nickel, platinum, titanium nitride, tantalum nitride, copper nitride, tungsten nitride, One or a combination of one or more of platinum nitride, aluminum nitride, nickel nitride and cobalt nitride.
  • metal or metal nitride such as: titanium, tantalum, copper, tungsten, cobalt, aluminum, nickel, platinum, titanium nitride, tantalum nitride, copper nitride, tungsten nitride, One or a combination of one or more of platinum nitride, aluminum nitride, nickel nitride and cobalt nitride.
  • Step S1082 Form a capacitive dielectric layer to cover the lower electrode layer.
  • a capacitive dielectric layer 602 is formed on the surface of the lower electrode layer 601 , and the capacitive dielectric layer 602 covers the surface of the lower electrode layer 601 .
  • the capacitor dielectric layer 602 is a film structure of a high-K (dielectric constant) dielectric to increase the capacitance of the capacitor structure while reducing leakage between the upper and lower electrode layers of the capacitor.
  • hafnium dioxide can be used as the high-K dielectric. HfO2.
  • Step S1083 Form an upper electrode layer to cover the capacitive dielectric layer.
  • an upper electrode layer 603 is formed on the surface of the capacitive dielectric layer 602.
  • the material of the upper electrode layer 603 includes metal or metal nitride, such as titanium, tantalum, copper, tungsten, cobalt, aluminum, and nickel. , platinum, titanium nitride, tantalum nitride, copper nitride, tungsten nitride, platinum nitride, aluminum nitride, nickel nitride and cobalt nitride.
  • Step S1084 Form a semiconductor layer that covers the upper electrode layer and fills the third trench and the first etching hole located in the second region.
  • a semiconductor layer 604 is formed on the surface of the upper electrode layer 603 .
  • the semiconductor layer 604 fills the unfilled area of the third trench 260 and the unfilled first etching hole 270 (shown in FIG. 20 ). filled area.
  • the material of the semiconductor layer 604 is polysilicon, and the semiconductor layer 604 may also be formed of an epitaxial upper electrode layer 603 .
  • the lower electrode layer 601, the capacitive dielectric layer 602, the upper electrode layer 603 and the semiconductor layer 604 located in the second region D2 together form the capacitive structure 600.
  • the lower electrode layer 601 , the capacitor dielectric layer 602 , the upper electrode layer 603 and the semiconductor layer 604 located in the third trench 260 constitute the main structure of the capacitor structure 600 .
  • the lower electrode layer 601 , the capacitive dielectric layer 602 , the upper electrode layer 603 and the semiconductor layer 604 located in the first etching hole 270 (shown in FIG. 20 ) of the second region D2 constitute the extended structure 610 of the capacitive structure 600 .
  • One end of each extension structure 610 is connected to the main structure, each extension structure 610 and each active layer 500 are in the same layer, and the other end of the extension structure 610 is connected to the drain electrode of the active layer 500 in a one-to-one correspondence.
  • Step S110 Form a plurality of word lines, each word line is vertically connected to each active layer, and the word line covers part of the sidewall of each active layer.
  • a plurality of word lines 700 are formed in the first region D1 in the C region of the stacked structure 200 .
  • Each word line 700 extends along the third direction Z, and each word line 700 is connected to a plurality of word lines 700 .
  • the source layers 500 intersect vertically, thereby forming an electrical connection between the word lines 700 and the active layer 500 .
  • the word line 700 forms an electrical connection with part of the sidewall of each active layer 500 .
  • forming a plurality of word lines may include the following steps:
  • Step S1101 Remove part of the support layer located in the first area to form multiple word line trenches.
  • Each word line trench extends along the third direction and exposes part of the sidewall of each active layer.
  • the multiple word line trenches are Distributed at intervals in the second direction.
  • a patterned fourth mask layer 70 may be formed on the top surface of the stacked structure 200 .
  • the fourth mask layer 70 includes a plurality of third mask layers located in the first region D1 .
  • Four opening patterns 701, a plurality of fourth opening patterns 701 are arranged at intervals along the second direction Y.
  • a portion of the support layer 210 is etched along the plurality of fourth opening patterns 701 until the top surface of the substrate isolation layer 110 is exposed, as shown in FIG. 27 , thereby forming multiple layers in the stacked structure 200 . 710 word line slots.
  • the active layer 500 is selectively not etched.
  • the word line trench 710 vertically intersects each active layer 500 , and each word line trench 710 exposes part of the sidewall of each active layer 500 .
  • the cross-sectional length L1 of each word line trench 710 is greater than the cross-sectional length L2 of the active layer 500 located in the word line trench 710 , wherein the portion located in the word line trench 710 The sidewalls of the active layer 500 are exposed by the word line trenches 710 .
  • Step S1102 Form a gate oxide layer, which covers part of the exposed sidewall of the active layer.
  • the surface of the active layer 500 exposed by the word line trench 710 is thermally oxidized.
  • the surface of the exposed active layer 500 is subjected to ISSG (In-Situ Steam Generation, in-situ steam oxidation method) treatment to form a gate oxide layer 800 on the surface of the active layer 500 .
  • the gate oxide layer 800 covers the sidewalls of part of the active layer 500 exposed by the word line trench 710, which can reduce leakage current and improve the reliability of the semiconductor device.
  • Step S1103 Form a word line material layer.
  • the word line material layer covers the gate oxide layer and fills the word line trench.
  • the word line material layer located in the same word line trench forms a word line.
  • word line material is deposited in each word line trench 710 to form a word line material layer 71 .
  • the word line material layer 71 surrounds the surface of the gate oxide layer 800 and fills the word line trench 710 .
  • the word line material layer 71 located in the same word line trench 710 forms the word line 700.
  • the top surface of the word line 700 is flush with the top surface of the stacked structure 200 .
  • multiple bit lines are formed at the positions of the removed portion of the sacrificial layer in the stacked structure, and two bit lines are formed on both sides of each bit line on the same layer.
  • Source layer one end of each active layer is connected to the bit line, and the other end of each active layer is connected to the capacitor structure, thus providing a three-dimensional stacked structure of DRAM, which can improve DRAM by directly increasing the number of stacked layers.
  • the storage density can form a larger number of memories on the same area of the substrate, overcoming the problem that DRAM storage density is difficult to continue to increase, thus achieving higher storage density and meeting the development needs of high-capacity memory in the semiconductor field. .
  • FIG. 34 is a flow chart illustrating a method of forming a semiconductor structure according to yet another exemplary embodiment. Most of the contents of the semiconductor structure of this embodiment are the same as those of the above embodiment.
  • Figures 2 to 33 are schematic diagrams of various stages of the method of forming the semiconductor structure. The method of forming the semiconductor structure will be introduced below with reference to Figures 2 to 33. As shown in Figure 34, the method provided in this embodiment is based on the method shown in Figure 1.
  • the method for forming a semiconductor structure in this embodiment also includes:
  • Step S202 Form a stacked ladder along the first direction, and the end surface of the stacked ladder exposes the support layer, the sacrificial layer and the sidewalls of the bit lines.
  • a plurality of bit line steps are formed on the end surface of the stacked step, and the bit line steps include a plurality of bit lines distributed at intervals in the third direction. The lengths of the plurality of bit lines gradually increase along the direction from the top surface to the bottom surface of the substrate to form bit lines distributed in a ladder shape in the third direction.
  • a fifth mask layer 60 is formed on the surface of the stacked structure 200 .
  • the fifth mask layer 60 extends in the first direction X and the second direction Y respectively, and continuously covers the stacked structure 200 On the top surface, in the second direction Y, the length L3 of the fifth mask layer 60 is smaller than the length L4 of the stacked structure 200 and larger than the width of the C region (shown in FIG. 29 ).
  • the description takes the interconnected support layer 210 and the sacrificial layer 220 as a set of stacked layers as an example.
  • the stacked layer located at the top of the stacked structure 200 is marked as the first stacked layer 202
  • the adjacent stacked layer located under the first stacked layer 202 is marked as the second stacked layer 203, and so on. They are the third stack 204 , the fourth stack 205 , and the fifth stack 206 .
  • the fifth mask layer 60 is etched. As shown in FIG.
  • a portion of the first stacked layer 202 is etched along the first direction
  • the top part of the support layer 210, part of the sacrificial layer 220, part of the dielectric layer 400 and part of the bit line 300 forms a step at each end of the stacked structure 200 in the second direction Y; then, the mask layer can be used to After forming the first step, the stacked structure 200 is covered to expose the top surface of the second stacked layer 203, and the second stacked layer 203 is etched based on the mask layer to form the second step; the above steps can be performed in a loop, in sequence
  • the third stacked layer 204 is etched to form a third step
  • the fourth stacked layer 205 is etched to form a fourth step
  • the fifth stacked layer 206 is etched to form a fifth step; respectively formed at both ends of the stacked structure 200
  • a set of laminated steps 280, the laminated steps 280 are composed of a plurality of steps. For example, this embodiment shows that the steps formed by five
  • each stack in the stack step 280 gradually increases as the distance from the top surface of the substrate 100 decreases. Finally, the fifth mask layer 60 is removed.
  • the stacking step 280 is located in the area outside the C area, and the end surface of the stacking step 280 exposes the sidewalls of the support layer 210 , the sidewalls of the sacrificial layer 220 and the end surface of the bit line 300 .
  • a plurality of bit line steps 360 are formed on the end surface of the stacked step 280. As shown in FIG. 31, the bit line steps 360 are located on both sides of the dielectric layer 400.
  • Each bit line step 360 is composed of a plurality of bit lines 300 spaced apart in the third direction Z, and in the second direction Y, there are a plurality of bit lines 300. The length of the bit lines 300 gradually increases from the top surface to the bottom surface of the substrate 100 .
  • Step S204 Form an isolation layer covering the surfaces of the plurality of bit lines and the plurality of word lines.
  • the top surface of the stacked structure 200 exposes the end surfaces of multiple word lines 700
  • the stacked steps 280 exposes the end surfaces of multiple bit lines 300 .
  • the end surfaces of the exposed bit lines 300 and An isolation layer 900 is formed on the end surface of the word line 700 to change This solves the problem of oxidation of the surface of the word line 700 and the surface of the bit line 300 that are exposed to the air.
  • the semiconductor structure can be filled with an isolation layer 900 , and the isolation layer 900 completely covers the surface of the stacked structure 200 .
  • the material of the isolation layer 900 includes oxide, nitride or a combination thereof, such as silicon oxide.
  • Step S206 Form a plurality of bit line contact plugs and a plurality of word line contact plugs. Multiple word line contact plugs are respectively connected to multiple word lines in one-to-one correspondence. The plurality of bit line contact plugs are respectively connected to the plurality of bit lines in one-to-one correspondence.
  • each word line contact hole 720 exposes a portion of the surface of a word line 700 .
  • Each bit line contact hole 340 exposes a portion of the surface of one bit line 300 .
  • the sixth mask layer is removed.
  • metal materials can be formed in multiple word line contact holes 720 and multiple bit line contact holes 340 at the same time.
  • the metal material located in the word line contact holes 720 forms word line contact plugs 730 located in the bit line contact holes 720 .
  • the metallic material of line contact holes 340 forms bit line contact plugs 350 .
  • Each word line contact plug 730 is electrically connected to each word line 700
  • each bit line contact plug 350 is electrically connected to each bit line 300 .
  • the metal material forming the word line contact plug 730 is the same as or different from the metal material forming the bit line contact plug 350.
  • the metal material includes: tungsten, titanium, tantalum, copper, aluminum, titanium nitride, and tantalum nitride.
  • word line contact plugs and bit line contact plugs are formed at positions corresponding to the word line and bit line, so that the word line can be led out and connected to other electronic devices or circuits through the word line contact plugs, and The bit lines are led out and connected to other electronic devices or circuits through the bit line contact plugs.
  • an exemplary embodiment of the present disclosure provides a semiconductor structure.
  • the semiconductor structure includes a substrate 100, a plurality of bit lines 300, a plurality of active layers 500, a capacitor structure 600 and a plurality of word lines. 700.
  • Each bit line 300 extends along the second direction Y, and the plurality of bit lines 300 are spaced apart in the third direction Z.
  • Each active layer 500 is on the same layer as each bit line 300 and is located on the side of each bit line 300.
  • the first end 501 of each active layer 500 is connected to each bit line 300.
  • the capacitor structure 600 is formed on the second end 502 of the active layer 500, and the capacitor structure 600 is connected to each active layer 500.
  • a plurality of word lines 700 are arranged at intervals in the second direction Y, each word line 700 is vertically connected to each active layer 500 , and the word lines 700 cover part of the sidewall of each active layer 500 .
  • the semiconductor structure in this embodiment is prepared using the method for forming the semiconductor structure in the above embodiment, and the method for forming the semiconductor structure will not be described in detail here.
  • the number of stacked layers of the memory in the formed semiconductor structure can be controlled by adjusting the number of stacked layers of the stacked structure in the manufacturing method, so that the semiconductor structure has an ever-increasing storage density and can be used on a substrate of the same area.
  • a larger number of memories are formed on the bottom, which overcomes the problem that the storage density of semiconductor chips is difficult to continue to increase due to the shrinkage of semiconductor chips, and meets the development needs of high-capacity memories in the semiconductor field.
  • the capacitive structure 600 includes a plurality of extension structures 610 .
  • the extension structure 610 extends along the first direction X and is electrically connected to each active layer 500 located in the first direction X.
  • an exemplary embodiment of the present disclosure provides a semiconductor structure. Most of the semiconductor structure of this embodiment is the same as the above-mentioned embodiment. The differences between this embodiment and the above-mentioned embodiment are
  • the semiconductor structure further includes a plurality of bit line contact plugs 350 and a plurality of word line contact plugs 730 .
  • the plurality of bit line contact plugs 350 are connected to the plurality of bit lines 300 in one-to-one correspondence.
  • the lengths of the plurality of bit lines 300 gradually increase from the top surface to the bottom surface of the substrate 100 .
  • the plurality of word line contact plugs 730 are connected to the plurality of word lines 700 in one-to-one correspondence.
  • multiple bit lines are formed at the positions of the removed portion of the sacrificial layer in the stacked structure, and two bit lines are formed on both sides of each bit line on the same layer.
  • One end of each active layer is connected to the bit line, and the other end of each active layer is connected to the capacitor structure, thus providing a three-dimensional stacked structure of DRAM that can increase the number of stacked layers directly on the substrate.
  • This method improves the storage density of DRAM, overcomes the problem that the storage density is difficult to continue to increase due to the shrinkage of semiconductor chips, and achieves higher storage density.

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Abstract

公开了一种半导体结构的形成方法及半导体结构，其中，半导体结构的形成方法，包括提供衬底和叠层结构，叠层结构位于衬底的表面，叠层结构包括交替堆叠的牺牲层和支撑层。去除部分牺牲层，在部分牺牲层对应的位置形成多条位线。形成多个有源层，每个有源层与每条位线处于同层，且形成于每条位线的侧面，每个有源层的第一端和每条位线连接。形成电容结构，电容结构和每个有源层连接。形成多条字线，每条字线垂直连接每个有源层，字线覆盖每个有源层的部分侧壁。

Description

半导体结构的形成方法及半导体结构
本公开基于申请号为202210971308.5、申请日为2022年08月15日、申请名称为“半导体结构的形成方法及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构的形成方法及半导体结构。
背景技术
随着半导体芯片的不断发展，其关键尺寸也在不断减小，但由于光刻机的工艺条件的限制，半导体芯片的尺寸缩小存在极限，因此如何在晶圆上做出更高存储密度的芯片，实现更高的存储密度，成为亟待解决的问题。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种半导体结构的形成方法及半导体结构。
本公开的第一方面提供了一种半导体结构的形成方法，所述半导体结构的形成方法包括：
提供衬底和叠层结构，所述叠层结构位于所述衬底的表面，所述叠层结构包括交替堆叠的牺牲层和支撑层；
去除部分所述牺牲层，在部分所述牺牲层对应的位置形成多条位线，所述位线沿第二方向延伸，在第三方向上，相邻的所述位线间隔设置；
形成多个有源层，每个所述有源层与每条所述位线处于同层，且形成于每条所述位线的侧面，每个所述有源层的第一端和每条所述位线连接；
形成电容结构，所述电容结构形成于所述有源层的第二端，所述电容结构和每个所述有源层连接；
形成多条字线，每条所述字线垂直连接每个所述有源层，所述字线覆盖每个所述有源层的部分侧壁。
其中，去除部分所述牺牲层，包括：
形成第一沟槽，所述第一沟槽位于所述叠层结构的中间区域，所述第一沟槽沿第二方向延伸并贯穿所述叠层结构；所述第一沟槽的侧壁暴露出每个所述牺牲层和每个所述支撑层；
沿第一方向刻蚀被暴露的所述牺牲层，去除部分所述牺牲层，在被去除的部分所述牺牲层对应的位置形成位线槽，所述位线槽沿所述第二方向延伸。
其中，刻蚀被暴露出的所述牺牲层的过程中，所述牺牲层的材料相对所述支撑层的材料具有高刻蚀选择比。
其中，在被去除的部分所述牺牲层对应的位置形成多条位线，包括：
在每个所述位线槽以及所述第一沟槽的表面形成阻挡层，所述阻挡层覆盖所述位线槽的槽壁和所述第一沟槽的侧壁；
形成位线材料层，所述位线材料层覆盖所述阻挡层的表面，并填满每个所述位线槽和所述第一沟槽；
去除所述第一沟槽内的所述阻挡层和所述位线材料层，保留位于同一所述位线槽中的所述阻挡层和所述位线材料层，形成所述位线。
其中，在所述第一方向上，所述叠层结构包括靠近所述位线的第一区域和远离所述位线的第二区域；
形成多个有源层，包括：
在所述叠层结构内形成多个第二沟槽，每个所述第二沟槽沿所述第一方向延伸，并贯穿所述叠层结构；
在每个所述第二沟槽内形成填充材料，所述填充材料填满所述第二沟槽；
在所述第二区域内形成第三沟槽，所述第三沟槽沿所述第二方向延伸，并与每个所述第二沟槽垂直相交；
基于所述第三沟槽去除部分所述牺牲层，在被去除的所述牺牲层对应的位置形成第一刻蚀孔，在所述第二方向上，所述第一刻蚀孔贯穿所述第二区域延伸至所述第一区域并暴露所述位线；
向所述第一刻蚀孔中填充导电材料，去除部分所述填充材料，在位于所述第一区域的每个所述第一刻蚀孔中形成所述有源层。
其中，去除部分所述填充材料，在位于所述第一区域的每个所述第一刻蚀孔中形成所述有源层，包括：
基于所述第三沟槽刻蚀位于所述第二区域的所述第一刻蚀孔中的所述导电材料，保留位于所述第一区域的所述第一刻蚀孔中的所述导电材料形成所述有源层。
其中，形成电容结构包括：
所述电容结构包括多个延伸结构，每个所述延伸结构位于所述第二区域的每个所述第一刻蚀孔中，所述延伸结构沿所述第一方向延伸，且与每个所述有源层接触连接。
其中，形成电容结构，包括：
形成下电极层，覆盖所述第三沟槽的侧壁以及位于所述第二区域的所述第一刻蚀孔的侧壁；
形成电容介质层，覆盖所述下电极层；
形成上电极层，覆盖所述电容介质层；
形成半导体层，所述半导体层覆盖所述上电极层，并填满所述第三沟槽以及位于所述第二区域的所述第一刻蚀孔。
其中，形成多条字线，包括：
去除位于所述第一区域的部分所述支撑层，形成多个字线槽，每个所述字线槽沿所述第三方向延伸，且暴露出每个所述有源层的部分侧壁，多个所述字线槽在所述第二方向上间隔分布；
形成栅氧层，所述栅氧层覆盖暴露出来的所述有源层的部分侧壁；
形成字线材料，所述字线材料覆盖所述栅氧层，并填满所述字线槽，位于同一所述字线槽中的所述字线材料形成所述字线。
其中，所述半导体结构的形成方法还包括：
在所述第一沟槽内形成介质层，所述介质层填满所述第一沟槽，所述位线位于所述介质层的两侧，且与所述介质层接触连接。
其中，所述半导体结构的形成方法还包括：
沿所述第一方向去除部分所述支撑层、部分所述牺牲层、部分所述介质层和部分所述位线，形成叠层阶梯，所述叠层阶梯的端面暴露所述支撑层、所述牺牲层和所述位线的侧壁，在所述叠层阶梯的端面形成多个位线台阶，所述位线台阶包括在所述第三方向间隔分分布的多条所述位线，多条所述位线的长度沿所述衬底的顶面至底面的方向逐渐增加。
其中，所述半导体结构的形成方法还包括：
形成隔离层，所述隔离层覆盖多条所述位线和多条所述字线的表面。
其中，所述半导体结构的形成方法还包括：
形成多个位线接触插塞，多个所述位线接触插塞分别和多条所述位线一一对应连接；
形成多个字线接触插塞，多个所述字线接触插塞分别和多条所述字线一一对应连接，其中，多个所述位线接触插塞和多个所述字线接触插塞形成于所述隔离层中。
其中，其特征在于，所述半导体结构的形成方法还包括：
在所述衬底和所述叠层结构之间形成衬底隔离层。
本公开的第二方面提供了一种半导体结构，所述半导体结构包括：
衬底；
多条位线，每条所述位线沿第二方向延伸，多条所述位线在第三方向间隔设置；
多个有源层，每个所述有源层与每条所述位线处于同层，且位于每条所述位线的侧面，每个所述有源层的第一端和每条所述位线连接；
电容结构，所述电容结构形成于所述有源层的第二端，所述电容结构和每个所述有源层连接；
多条字线，多条所述字线在第二方向间隔设置，每条所述字线垂直连接每个所述有源层，所述字线覆盖每个所述有源层的部分侧壁。
其中，所述电容结构包括多个延伸结构，所述延伸结构沿第一方向延伸，并电性连接位于所述第一方向上的每个所述有源层。
其中，所述半导体结构还包括：
多个位线接触插塞，多个所述位线接触插塞分别和多条所述位线一一对应连接；其中，多条所述位线的长度沿所述衬底的顶面至底面的方向逐渐增加；
多个字线接触插塞，多个所述字线接触插塞分别和多条所述字线一一对应连接。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用 于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的半导体结构的形成方法的流程图。
图2是根据一示例性实施例示出的半导体结构形成过程中衬底和叠层结构的示意图。
图3是根据一示例性实施例示出的半导体结构形成过程中形成第一掩膜层后的示意图。
图4是根据一示例性实施例示出的半导体结构形成过程中形成位线槽的示意图。
图5是图4中A-A截面的剖面图。
图6是图4所示的结构形成阻挡层后的A-A截面的剖面图。
图7根据一示例性实施例示出的半导体结构形成过程中形成位线材料层的示意图。
图8根据一示例性实施例示出的半导体结构形成过程中去除第一沟槽内的位线材料层的示意图。
图9是图8中C-C截面的剖面图。
图10是图9的A区域的放大图。
图11是根据一示例性实施例示出的半导体结构形成过程中在第一沟槽内形成介质层的示意图。
图12是根据一示例性实施例示出的半导体结构形成过程中形成第二掩膜层的示意图。
图13是根据一示例性实施例示出的半导体结构形成过程中形成第二沟槽的示意图。
图14是图13所示的结构形成填充材料层后的B-B截面的剖面图。
图15是根据一示例性实施例示出的半导体结构的形成方法过程中形成第三掩膜层的示意图。
图16是根据一示例性实施例示出的半导体结构的形成方法过程中形成第三沟槽的示意图。
图17是图16的D-D截面的剖面图。
图18是根据一示例性实施例示出的半导体结构的形成方法过程中形成导电材料层的示意图。
图19是根据一示例性实施例示出的半导体结构的形成方法过程中形成有源层后的示意图。
图20是图19的E-E截面的剖面图。
图21是根据一示例性实施例示出的半导体结构的形成方法过程中形成下电极层的示意图。
图22是图21的E-E截面的剖面图。
图23是根据一示例性实施例示出的半导体结构的形成方法过程中形成电容结构的示意图。
图24是图23的B区域的局部放大图。
图25是根据一示例性实施例示出的半导体结构的形成方法过程中形成第四掩膜层的示意图。
图26是根据一示例性实施例示出的半导体结构的形成方法过程中形成字线槽的示意图。
图27是图26的F-F截面的剖面图。
图28是图27的C区域的局部放大图。
图29是根据一示例性实施例示出的半导体结构的形成方法过程中形成字线的示意图。
图30是根据一示例性实施例示出的半导体结构的形成方法过程中形成第五掩膜层的示意图。
图31是根据一示例性实施例示出的半导体结构的形成方法过程中形成叠层阶梯和位线台阶的示意图。
图32是根据一示例性实施例示出的半导体结构的形成方法过程中形成位线接触插塞和字线接触插塞的示意图。
图33是图32的G-G截面的剖面图。
图34是根据一示例性实施例示出的一种半导体结构的形成方法的流程图。
附图标记：
100、衬底；110、衬底隔离层；20、第一掩膜层；201、第一开口图案；202、第一叠层；203、第二叠层；204、第三叠层、205、第四叠层；206、第五叠层；200、叠层结构；D1、第一区域；D2、第二区域；210、支撑层；220、牺牲层；230、第一沟槽；240、第二沟槽；250、填充材料层；260、第三沟槽；270、第一刻蚀孔；280、叠层阶梯；30、第三掩膜层；300、位线；301、第三开口图案；310、位线槽；320、阻挡层；330、位线材料层；340、位线接触孔；350、位线接触插塞；360、位线台阶；40、第二掩膜层；400、介质层；401、第二开口图案；50、导电材料层；500、有源层；501、有源层的第一端；502、有源层的第二端；60、第五掩膜层；600、电容结构；601、下电极层；602、电容介质层；603、上电极层；604、半导体层；610、延伸结构；70、第四掩膜层；71、字线材料层；700、字线；701、第四开口图案；710、字线槽；720、字线接触孔；730、字线接触插塞；800、栅氧层；900、隔离层。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开示例性的实施例中提供了一种半导体结构的形成方法，如图1所示，图1示出了根据本公开一示例性的实施例提供的半导体结构的形成方法的流程图，图2-图33为半导体结构的形成方法的各个阶段的示意图，下面结合图2-图33对半导体结构的形成方法进行介绍。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存取存储器(Dynamic Random Access Memory，DRAM)的三维结构为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
如图1所示，本公开一示例性的实施例提供的半导体结构的形成方法，包括如下的步骤：
步骤S102：提供衬底和叠层结构，叠层结构位于衬底的表面，叠层结构包括交替堆叠的牺牲层和支撑层。
示例性的，如图2所示，衬底100作为存储器的支撑部件，用于支撑设在其上的其他部件，衬底100可以由半导体材料制成，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种。衬底100包括源区、漏区以及其他互连结构。
如图2所述，叠层结构200位于衬底100的表面的上方(即衬底的顶面)，以图2中所示方位为准，沿由下至上的方向，叠层结构200由依次层叠设置的支撑层210和牺牲层220构成。具体的，叠层结构200的最底层为支撑层210，叠层结构200的最顶层为支撑层210。相邻的两个支撑层210之间的牺牲层220可以为其他结构的占位物，示例性的，牺牲层220可以为氧化物，例如氧化硅。形成支撑层210的材料的刻蚀速率小于形成牺牲层220的材料的刻蚀速率，示例性的，支撑层210为氮化物，例如为氮化硅。
示例性的，如图2所示，在衬底100的表面形成衬底隔离层110，然后在衬底隔离层110的表面形成叠层结构200，从而可以以衬底隔离层110作为刻蚀停止层，例如衬底隔离层110为碳氧化硅SiOC。
步骤S104：去除部分牺牲层，在部分牺牲层对应的位置形成多条位线，位线沿第二方向Y延伸，在第三方向上，相邻的位线间隔设置。
如图4所示，可以通过湿法刻蚀或干法刻蚀的方法，在垂直于衬底100的顶面的第三方向Z上，在叠层结构200的中间位置，去除相邻的两个支撑层210之间的部分牺牲层220，再通过物理气相沉积(PhysicalVapor Deposition，PVD)、化学气相沉积(Chemical Vapor Deposition，CVD)或原子层沉积(Atomicl Lyer Deposition，ALD)等方式，在去除牺牲层220的位置处形成位线300。如图9所示，在第三方向Z上，每条位线300位于相邻的两个支撑层210之间，多个支撑层210将多条位线300间隔开。如图8所示，每条位线300沿第二方向Y延伸。示例性的，第一方向X和第二方向Y均是平行于衬底100的方向，其中，第一方向X和第二方向Y之间呈直角，第三方向Z为垂直于衬底100的方向。
在该实施例中，如图9所示，在第一方向X上，位线300位于叠层结构200的中间位置，以在后续工艺中在位线300两侧的叠层结构200中均形成三维堆叠半导体器件做准备，提高半导体器件的集成度。
示例性的，可以控制牺牲层的厚度来控制位线的厚度。位线可以包括掺杂的半导体材料、导电金属氮化物、金属(例如，非化合的金属材料)或金属半导体化合物。
在一些示例性实施例中，形成位线可以通过以下步骤实现：
步骤S1041：形成第一沟槽，第一沟槽位于叠层结构的中间区域，第一沟槽沿第二向延伸并贯穿叠层结构。第一沟槽的侧壁暴露出每个牺牲层和每个支撑层。
步骤S1042：沿第一方向刻蚀被暴露的牺牲层，去除部分牺牲层。
步骤S1043：在被去除的部分牺牲层对应的位置形成位线槽，位线槽沿第二方向延伸。
步骤S1044：在每个位线槽以及第一沟槽的表面形成阻挡层，阻挡层覆盖位线槽的槽壁和第一沟槽的侧壁。
步骤S1045：形成位线材料层，位线材料层覆盖阻挡层的表面，并填满每个位线槽和第一沟槽。
步骤S1046：去除第一沟槽内的阻挡层和位线材料层，保留位于同一位线槽中的阻挡层和位线材料层，形成位线。
步骤1047：在第一沟槽内形成介质层，介质层填满第一沟槽，位线位于介质层的两侧，且与介质层接触连接。
在步骤S1041中，如图3和图4所示，在叠层结构200的上方形成图形化的第一掩膜层20，第一掩膜层20包括第一开口图案201，第一开口图案201沿第二方向Y延伸。沿第一开口图案201刻蚀叠层结构200，并沿叠层结构200的厚度方向贯穿叠层结构200，以在叠层结构200中形成第一沟槽230。第一沟槽230的侧壁暴露出叠层结构200中的每个支撑层210的侧壁以及每个牺牲层220的侧壁。
在步骤S1042中，如图4所示，沿暴露的牺牲层220的侧壁沿远离第一沟槽230的方向刻蚀部分牺牲层220，以在第一沟槽230的两侧被去除的部分除牺牲层220的位置处分别形成位线300(参考图8)。
在步骤S1043中，如图4和图5所示，在第一沟槽230的两侧，分别沿着远离第一沟槽230的方向去除部分牺牲层220后，在相邻的两个支撑层210之间形成了开口。该开口沿着平行于衬底100的第二方向Y方向延伸，每个开口对应的位置形成位线槽310。第一沟槽230将处于同层的两个位线槽310彼此间隔开，以在后续工艺中在第一沟槽230的两侧分别形成位线300(参考图8)。
示例性的，在刻蚀被暴露出的牺牲层的过程中，牺牲层的材料相对支撑层的材料具有高刻蚀选择比，使得支撑层的刻蚀速率远远小于牺牲层的刻蚀速率，以减少支撑层的损耗，从而形成平整度较高的开口，以形成厚度均匀的条状结构的位线。
在步骤S1044中，如图6所示，可以通过物理气相沉积、化学气相沉积、原子层沉积或外延生长等方式，在每个位线槽310以及第一沟槽230的表面形成阻挡层320。阻挡层320连续覆盖在叠层结构200的顶面、第一沟槽230的侧壁以及位线槽310的表面，阻挡层320可以有效阻挡后续工艺中形成位线的材料渗透到叠层结构200中，示例性的。阻挡层320的材料例如为氮化钛。
在步骤S1045中，如图6和图7所示，在位线槽310未填充的区域内沉积位线材料层330，位线材料层330覆盖在阻挡层320的表面，并填满位线槽310未填充的区域以及第一沟槽230未填充的区域，位线材料层330还沉积在叠层结构200的顶面上。示例性的，位线材料层330的材料包括钨(W)、钴(Co)、铜(Cu)、铝(Al)、多晶硅、掺杂硅、硅化物或其任何组合。
在步骤S1046中，如图6和图7所示，对部分阻挡层320以及部分位线材料层330一起进行回刻处理，去除位于叠层结构200顶面的阻挡层320和位线材料层330，以及第一沟槽230内的阻挡层320和位线材料层330。如图8、图9和图10所示，保留位于位线槽310内的阻挡层320和位线材料层330，位于同一位线槽310中的阻挡层320和位线材料层330共同构成位线300。示例性的，如图8所示，位线300为在第二方向Y上延伸的条状结构或线状结构。
在步骤S1047中，如图9和图10所示，位于第一沟槽230两侧各有一组位线组，每组位线组包括在第三方向Z彼此间隔开的多条位线300。结合图8和图11所示，在第一沟槽230内沉积介质层400，介质层400还可能会覆盖叠层结构200的顶面，可以对介质层400进行平坦化工艺后，保留位于第一沟槽230内的介质层400。如图11所示，在第一方向X上，在处于同层的两个位线300之间的介质层400起到隔离的作用，将处于同层的两个位线300进行隔离。示例性的，介质层400的材料例如为氧化硅。
步骤S106：形成多个有源层，每个有源层与每条位线处于同层，且形成于每条位线的侧面，每个有源层的第一端和每个位线连接。
如图20所示，在形成位线组后，针对每个位线组的每条位线300对应形成有源层500，每个有源层500形成于每个位线300的侧面，且有源层500和与其对应的位线300处于同层。每个有源层500的第一端501与每个位线300的远离第一沟槽230(在图10中示出)的一侧接触连接，以形成电性连接。
在一些示例性实施例中，以在其中一组位线组的一侧形成多个有源层为例进行说明。如图12所示，位线300位于叠层结构200的中部，在第一方向X上，将叠层结构200靠近位线300的预设区域记为第一区域D1，将远离位线300的其他区域记为第二区域D2。如图12所示，第一区域D1由靠近位线300且沿第二方向Y延伸的区域形成；第二区域D2位于第一区域D1以外，且与第一区域D1相邻设置，第二区域D2也沿第二方向Y延伸。
示例性的，形成多个有源层可以包括如下步骤：
步骤S1061：在叠层结构内形成多个第二沟槽，每个第二沟槽沿第一方向延伸，并贯穿叠层结构。
步骤S1062：在每个第二沟槽内形成填充材料层，填充材料层填满第二沟槽。
步骤S1063：在第二区域内形成第三沟槽，第三沟槽沿第二方向延伸，并与每个第二沟槽垂直相交。
步骤S1064：基于第三沟槽去除部分牺牲层，在被去除的牺牲层对应的位置形成第一刻蚀孔，在第二方向上，第一刻蚀孔贯穿第二区域延伸至第一区域并暴露位线。
步骤S1065：向第一刻蚀孔中填充导电材料，形成导电材料层。
步骤S1066：基于第三沟槽刻蚀位于第二区域的第一刻蚀孔中的导电材料层，保留位于第一区域的第一刻蚀孔中的部分导电材料层形成有源层。
在步骤S1061中，如图12所示，在叠层结构200的表面形成图形化的第二掩膜层40，第二掩膜层40包括多个第二开口图案401。多个第二开口图案401在第二方向Y上彼此间隔，每个第二开口图案401沿第一方向X方向延伸，多个第二开口图案401集中在叠层结构200的C区域内，如图12所示，C区域为沿第二方向Y延伸的预设区域。
示例性的，如图12所示，在第一方向X上，第二开口图案401的长度与叠层结构200的长度一致。多个第二开口图案401在第二方向Y上的总宽度小于叠层结构200在第二方向Y上的总宽度。如图12和图13所示，基于第二开口图案401刻蚀叠层结构200，并沿叠层结构200的厚度方向贯穿叠层结构200，以形成多个第二沟槽240，每个第二沟槽240暴露衬底隔离层110的部分顶面。如图13所示，在第三方向Z上，每个第二沟槽240与支撑层210垂直相交。第二沟槽240沿第一方向X延伸贯穿第一区域D1和第二区域D2。其中，在形成第二沟槽240的过程中不对位线300进行刻蚀，每条位线300在第二方向Y上保持连续的条形或者线状结构。最后，在叠层结构200内形成多个第二沟槽240后，去除第二掩膜层40。
在步骤1062中，如图13和图14所示，接着在每个第二沟槽240内沉积填充材料，直至第二沟槽240中填满填充材料，形成填充材料层250，从而将叠层结构200填平以为后续工艺做准备。如图13和图14所示，位于每个第二沟槽240中的填充材料层250连接每个支撑层210以及牺牲层220，部分牺牲层220保留在任意相邻的填充材料层250与任意相邻的两个支撑层210形成的空间内，并沿着第一方向X延伸。
如图14所示，为了便于去除位于C区内的牺牲层220，以在位线300(参考图20)的一侧形成有源层500(参考图20)，可以选择刻蚀速率大于牺牲层220的材料的刻蚀速率的材料作为填充材料。示例性的，填充材料例如为氮化硅，填充材料还可以选择与支撑层210相同的材质。
在步骤S1063中，如图15所示，可以在叠层结构200的顶面以及填充材料层250的顶面形成图形化的第三掩膜层30，第三掩膜层30包括位于第二区域D2内的第三开口图案301，第三开口图案301沿第二方向Y延伸。结合图15和图16所示，基于第三开口图案301刻蚀叠层结构200，以在叠层结构200的第二区域D2内形成第三沟槽260。第三沟槽260沿叠层结构200的厚度方向贯穿叠层结构200，第三沟槽260暴露出C区内的牺牲层220的侧壁。
在步骤S1064中，如图16和图17所示，可以利用干法刻蚀工艺，基于第三沟槽260刻蚀位于C区内的牺牲层220，去除在两个支撑层210之间的牺牲层220，被除去的牺牲层220对应的空间形成第一刻蚀孔270。在第一方向X上，第一刻蚀孔270贯穿第二区域D2的宽度，并向第一区域D1延伸直至暴露出位线300的部分侧面。
在步骤S1065中，如图16、图17和图18所示，向第一刻蚀孔270中沉积导电材料，形成导电材料层50，直至将第一刻蚀孔270填满。在向第一刻蚀孔270沉积导电材料形成导电材料层50的过程中，导电材料还会覆盖在叠层结构200的顶面，可以利用化学机械抛光(CMP，Chemical Mechanical Polishing)工艺以及回刻工艺对多余的导电材料进行处理，保留位于第三沟槽260中的导电材料。示例性的，导电材料例如为多晶硅材料。
在步骤S1066中，如图18、图19和图20所示，去除位于第三沟槽260内的导电材料层50。最后，基于第三沟槽260刻蚀C区内位于第二区域D2的导电材料层50，以保留C区内位于第一区域D1的部分导电材料层50，形成多个有源层500。
如图20所示，保留在第一刻蚀孔270内的导电材料层50形成有源层500，在第三方向Z上，多个有源层500彼此间隔设置，每个有源层500与位线300处于同层，有源层500与位线300一一对应，每个有源层500的第一端501与位线300形成电性连接。示例性的，有源层500的第一端501可以作为源极，有源层500的第二端502可以作为漏极，用于与其他结构形成电性连接，例如有源层500的第二端502可以与电容结构600(参考图27)形成电性连接。
步骤S108：形成电容结构，电容结构形成于有源层的第二端，电容结构和每个有源层连接。
如图27所示，在叠层结构200的第二区域D2内形成电容结构600，电容结构600形成于第三沟槽260未被填充的区域以及第一刻蚀孔270未被填充的区域，电容结构600形成于有源层500 的第二端502，电容结构600与有源层500的第二端502接触连接，以在电容结构600与有源层500的第二端502之间形成电性连接。
如图27所示，电容结构600的主体结构位于第三沟槽260中，并在第三沟槽260的两侧具有多个延伸结构610。每个延伸结构610分别位于第二区域D2的每个第一刻蚀孔270中，每个延伸结构610沿第一方向X延伸，延伸至有源层500的第二端502。如图27所示，位于同一第一刻蚀孔270内的延伸结构610的一端与电容结构600的主体结构连接，延伸结构610的另一端与有源层500的第二端502接触连接，以形成电性连接。其中，多个延伸结构610在第三方向Z上彼此间隔设置。在该实施例中，去除位于第二区域D2中的导电材料层，以在第二区域D2中形成电容结构600的主体结构以及延伸结构，从而增加了半导体结构中电容结构的占比，提高了半导体结构的存储能力。
在一些示例性实施例中，形成电容结构可以包括如下步骤：
步骤S1081：形成下电极层，覆盖第三沟槽的侧壁以及位于第二区域的第一刻蚀孔的侧壁。
如图20、图21和图22所示，在位于第二区域D2的第一刻蚀孔270未被有源层500覆盖的表面，以及第三沟槽260的表面形成下电极层601。在第一方向X上，位于同一第一刻蚀孔270的下电极层601与有源层500的第二端502接触连接，下电极层601还可以覆盖在叠层结构200的顶面(图中未示出)。
示例性的，下电极层的材料包括金属或金属氮化物，例如：钛、钽、铜、钨、钴、铝、镍、铂、氮化钛、氮化钽、氮化铜、氮化钨、氮化铂、氮化铝、氮化镍和氮化钴中的一种或多种的组合。
步骤S1082：形成电容介质层，覆盖下电极层。
如图22、图23和图24所示，在下电极层601的表面形成电容介质层602，电容介质层602覆盖在下电极层601的表面。示例性的，电容介质层602为高K(介电常数)介质的膜层结构，以提高电容结构的电容的同时，减少电容器上下电极层之间的漏电，例如高K介质可以选用二氧化铪HfO2。
步骤S1083：形成上电极层，覆盖电容介质层。
如图24所示，在电容介质层602的表面形成上电极层603，示例性的，上电极层603的材料包括金属或金属氮化物，例如钛、钽、铜、钨、钴、铝、镍、铂、氮化钛、氮化钽、氮化铜、氮化钨、氮化铂、氮化铝、氮化镍和氮化钴中的一种或多种的组合。
步骤S1084：形成半导体层，半导体层覆盖上电极层，并填满第三沟槽以及位于第二区域的第一刻蚀孔。
如图23和图24所示，在上电极层603的表面形成半导体层604，半导体层604填满第三沟槽260未填充的区域以及第一刻蚀孔270(图20中示出)未填充的区域。示例性的，半导体层604的材料例如为多晶硅，半导体层604还可以由外延的上电极层603形成。其中位于第二区域D2内的下电极层601、电容介质层602、上电极层603以及半导体层604共同形成电容结构600。具体的，位于第三沟槽260内的下电极层601、电容介质层602、上电极层603以及半导体层604构成电容结构600的主体结构。位于第二区域D2的第一刻蚀孔270(图20中示出)中的下电极层601、电容介质层602、上电极层603以及半导体层604构成电容结构600的延伸结构610。每个延伸结构610的一端与主体结构连接，每个延伸结构610和每个有源层500处于同层，延伸结构610的另一端与有源层500的漏极一一对应接触连接。
步骤S110：形成多条字线，每条字线垂直连接每个有源层，字线覆盖每个有源层的部分侧壁。
如图29所示，在叠层结构200的C区内的第一区域D1中形成多条字线700，每条字线700沿第三方向Z延伸，每条字线700分别与多个有源层500垂直相交，从而在字线700与有源层500之间形成电性连接。如图29所示，在第三方向Z上，字线700与每个有源层500的部分侧壁形成电性连接。
在一些示例性实施例中，形成多条字线可以包括以下步骤：
步骤S1101：去除位于第一区域的部分支撑层，形成多个字线槽，每个字线槽沿第三方向延伸，且暴露出每个有源层的部分侧壁，多个字线槽在第二方向上间隔分布。
如图25、图26和图27所示，可以在叠层结构200的顶面上形成图形化的第四掩膜层70，第四掩膜层70包括位于第一区域D1内的多个第四开口图案701，多个第四开口图案701沿第二方向Y间隔设置。以第四掩膜层70为掩膜，沿多个第四开口图案701刻蚀部分支撑层210直至暴露衬底隔离层110的顶面，如图27所示从而在叠层结构200中形成多个字线槽710。
示例性的，如图27所示，在刻蚀支撑层210的过程中，选择性地对有源层500不进行刻蚀， 在第三方向Z上，字线槽710与每个有源层500垂直相交，每个字线槽710均暴露出各个有源层500的部分侧壁。
如图28所示，在第二方向Y上，每个字线槽710的截面长度L1大于位于字线槽710内的有源层500的截面长度L2，其中，位于字线槽710中的部分有源层500的侧壁被字线槽710暴露出来。
步骤S1102：形成栅氧层，栅氧层覆盖暴露出来的有源层的部分侧壁。
如图28所示，对被字线槽710暴露出的有源层500的表面进行热氧化处理。例如，对被暴露的有源层500的表面进行ISSG(In-Situ Steam Generation，原位水蒸汽氧化方法)处理，以在有源层500的表面形成栅氧层800。栅氧层800覆盖在被字线槽710暴露出的部分有源层500的侧壁上，能够降低漏电流，提高半导体器件的可靠性。
步骤S1103：形成字线材料层，字线材料层覆盖栅氧层，并填满字线槽，位于同一字线槽中的字线材料层形成字线。
如图28和图29所示，在每个字线槽710内沉积字线材料形成字线材料层71，字线材料层71包围在栅氧层800的表面上，并填满字线槽710，位于同一字线槽710中的字线材料层71形成字线700。示例性的，字线700的顶面与叠层结构200的顶面齐平。
本公开实施例所提供的半导体结构的形成方法中，通过在叠层结构中的被去除的部分牺牲层的位置处形成多条位线，并在同一层的每条位线两侧分别形成有源层，每个有源层的一端与位线连接，每个有源层的另一端连接电容结构，从而提供了一种DRAM的三维叠层结构，可通过直接增加堆叠层数的方式提升DRAM的存储密度，以在相同面积的衬底上形成更多数量的存储器，克服了DRAM存储密度难以继续增加的问题，从而实现了更高的存储密度，满足了半导体领域对高容量存储器的发展需求。
如图34是根据又一示例性实施例示出的一种半导体结构的形成方法的流程图。本实施例的半导体结构的大部分内容和上述实施例相同，图2-图33为半导体结构的形成方法的各个阶段的示意图，下面结合图2-图33对半导体结构的形成方法进行介绍。如图34所示，本实施例提供的方法在图1所示方法的基础上，本实施例的半导体结构的形成方法还包括：
步骤S202：沿第一方向，形成叠层阶梯，叠层阶梯的端面暴露支撑层、牺牲层和位线的侧壁。在叠层阶梯的端面形成多个位线台阶，位线台阶包括在第三方向间隔分分布的多条位线。多条位线的长度沿衬底的顶面至底面的方向逐渐增加，以在第三方向上形成呈阶梯状分布的位线。
如图30所示，在叠层结构200的表面形成第五掩膜层60，第五掩膜层60分别在第一方向X和第二方向Y方向上延伸，并连续覆盖在叠层结构200的顶面，在第二方向上Y，第五掩膜层60长度L3小于叠层结构200的长度L4，且大于C区(图29中示出)的宽度。以互相连接的支撑层210和牺牲层220作为一组叠层为例进行说明。如图30所示，位于叠层结构200顶部的叠层记为第一叠层202，位于第一叠层202下的相邻的叠层记为第二叠层203，以此类推，分别记为第三叠层204、第四叠层205、第五叠层206。以第五掩膜层60为掩膜，刻蚀第一叠层202，如图31所示，沿着第一方向X延伸刻蚀部分第一叠层202，也即是去除位于叠层结构200顶部的部分支撑层210、部分牺牲层220、部分介质层400和部分位线300，从而在叠层结构200的第二方向Y上的两端各形成一个台阶；然后，可以利用掩膜层对形成第一个台阶后的叠层结构200进行覆盖，暴露出第二叠层203的顶面，基于掩膜层刻蚀第二叠层203，形成第二个台阶；可以循环执行上述步骤，依次刻蚀第三叠层204形成第三个台阶，刻蚀第四叠层205形成第四个台阶，刻蚀第五叠层206形成第五个台阶；分别在叠层结构200的两端各形成一组叠层阶梯280，叠层阶梯280由多个台阶构成。示例性的，本实施例中示出了由五个叠层形成的台阶构成叠层阶梯280，在其他实施例中，叠层阶梯280中的台阶数量可以根据实际需要进行设置，在此不做具体限制。
如图31所示，第二方向Y上，叠层阶梯280中的每个叠层随着距离衬底100顶面的距离的减小而逐渐增加。最后，去除第五掩膜层60。
如图31所示，叠层阶梯280位于C区以外的区域，叠层阶梯280的端面暴露出支撑层210的侧壁、牺牲层220的侧壁以及位线300的端面。叠层阶梯280端面形成有多个位线台阶360。如图31所示，位线台阶360位于介质层400的两侧，每个位线台阶360由在第三方向Z间隔分分布的多条位线300构成，且在第二方向Y上，多条位线300的长度沿衬底100的顶面至底面的方向逐渐增加。
步骤S204：形成隔离层，隔离层覆盖多条位线和多条字线的表面。
如图31和图32所示，叠层结构200的顶面暴露出多条字线700的端面，叠层阶梯280暴露出多条位线300的端面，可以在暴露的位线300的端面和字线700的端面形成隔离层900，来改 善被暴露在空气中的字线700的表面和位线300的表面被氧化的问题。为了能够为后续工艺做准备，可以利用隔离层900将半导体结构填平，隔离层900完全覆盖叠层结构200的表面。示例性的，隔离层900的材料包括氧化物、氮化物或其组合，例如为氧化硅。
步骤S206：形成多个位线接触插塞和多条字线接触插塞。多个字线接触插分别和多条字线一一对应连接。多个位线接触插塞分别和多条位线一一对应连接。
如图32所示，可以利用曝光、显影等工艺，在隔离层900的顶面形成图形化的第六掩膜层。基于第六掩膜层刻蚀隔离层900，以在隔离层900中形成多个条字线接触孔720和多个位线接触孔340。结合图32和图33所示，每个字线接触孔720分别对应暴露一条字线700的部分表面。每个位线接触孔340分别对应暴露一条位线300的部分表面。最后去除第六掩膜层。
如图33所示，可以同时分别在多个字线接触孔720和多个位线接触孔340中形成金属材料，位于字线接触孔720中的金属材料形成字线接触插塞730，位于位线接触孔340的金属材料形成位线接触插塞350。每个字线接触插塞730与每条字线700形成电性连接，每个位线接触插塞350与每条位线300形成电性连接。示例性的，形成字线接触插塞730的金属材料和形成位线接触插塞350的金属材料相同或者不同，金属材料包括：钨、钛、钽、铜、铝、氮化钛、氮化钽、氮化钨中的一种或多种组合。在本实施例中，在对应字线和位线的位置分布形成字线接触插塞和位线接触插塞，以便通过字线接触插塞将字线引出和其它的电子器件或电路连接，以及通过位线接触插塞将位线引出和其它的电子器件或电路连接。
如图29所示，本公开一示例性的实施例提供的一种半导体结构，该半导体结构包括衬底100、多条位线300，多个有源层500、电容结构600和多条字线700。每条位线300沿第二方向Y延伸，多条位线300在第三方向Z间隔设置。每个有源层500与每条位线300处于同层，且位于每条位线300的侧面，每个有源层500的第一端501和每条位线300连接。电容结构600形成于有源层500的第二端502，电容结构600和每个有源层500连接。多条字线700在第二方向Y间隔设置，每条字线700垂直连接每个有源层500，字线700覆盖每个有源层500的部分侧壁。
该实施例中的半导体结构采用上述实施例中的半导体结构的形成方法制备而成，半导体结构的形成方法在此不再赘述。本实施例的半导体结构，可以通过调整制作方法中叠层结构的堆叠层数控制形成的半导体结构中存储器的堆叠层数，以使半导体结构具有可不断增加的存储密度，能够在相同面积的衬底上形成更多数量的存储器，克服了半导体芯片因尺寸微缩导致存储密度难以继续增加的问题，满足了半导体领域对高容量存储器的发展需求。
在一些示例性实施例中，如图29所示，电容结构600包括多个延伸结构610。延伸结构610沿第一方向X延伸，并电性连接位于第一方向X上的每个有源层500。
如图33所示，本公开一示例性的实施例提供的一种半导体结构，本实施例的半导体结构的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，该半导体结构还包括多个位线接触插塞350和多个字线接触插塞730。多个位线接触插塞350分别和多条位线300一一对应连接。多条位线300的长度沿衬底100的顶面至底面的方向逐渐增加。多个字线接触插塞730分别和多条字线700一一对应连接。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处 理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开提供的半导体结构的形成方法及半导体结构中，通过在叠层结构中的被去除的部分牺牲层的位置处形成多条位线，并在同一层的每条位线两侧分别形成有源层，每个有源层的一端与位线连接，每个有源层的另一端连接电容结构，从而提供了一种DRAM的三维叠层结构，可通过直接在衬底上增加堆叠层数的方式提升DRAM的存储密度，克服了半导体芯片因尺寸微缩导致存储密度难以继续增加的问题，实现了更高的存储密度。

Claims (17)

  1. 一种半导体结构的形成方法，包括：
    提供衬底(100)和叠层结构(200)，所述叠层结构(200)位于所述衬底(100)的表面，所述叠层结构(200)包括交替堆叠的牺牲层(220)和支撑层(210)；
    去除部分所述牺牲层(220)，在部分所述牺牲层(220)对应的位置形成多条位线(300)，所述位线(300)沿第二方向延伸，在第三方向上，相邻的所述位线(300)间隔设置；
    形成多个有源层(500)，每个所述有源层(500)与每条所述位线(300)处于同层，且形成于每条所述位线(300)的侧面，每个所述有源层的第一端(501)和每条所述位线(300)连接；
    形成电容结构(600)，所述电容结构(600)形成于所述有源层的第二端(502)，所述电容结构(600)和每个所述有源层(500)连接；
    形成多条字线(700)，每条所述字线(700)垂直连接每个所述有源层(500)，所述字线(700)覆盖每个所述有源层(500)的部分侧壁。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，去除部分所述牺牲层(220)，包括：
    形成第一沟槽(230)，所述第一沟槽(230)位于所述叠层结构(200)的中间区域，所述第一沟槽(230)沿所述第二方向延伸并贯穿所述叠层结构(200)；所述第一沟槽(230)的侧壁暴露出每个所述牺牲层(220)和每个所述支撑层(210)；
    沿第一方向刻蚀被暴露的所述牺牲层(220)，去除部分所述牺牲层(220)，在被去除的部分所述牺牲层(220)对应的位置形成位线槽(310)，所述位线槽(310)沿所述第二方向延伸。
  3. 根据权利要求1或2所述的半导体结构的形成方法，其中，刻蚀被暴露出的所述牺牲层(220)的过程中，所述牺牲层(220)的材料相对所述支撑层(210)的材料具有高刻蚀选择比。
  4. 根据权利要求2所述的半导体结构的形成方法，其中，在被去除的部分所述牺牲层(220)对应的位置形成多条位线(300)，包括：
    在每个所述位线槽(310)以及所述第一沟槽(230)的表面形成阻挡层(320)，所述阻挡层(320)覆盖所述位线槽(310)的槽壁和所述第一沟槽(230)的侧壁；
    形成位线材料层(330)，所述位线材料层(330)覆盖所述阻挡层(320)的表面，并填满每个所述位线槽(310)和所述第一沟槽(230)；
    去除所述第一沟槽(230)内的所述阻挡层(320)和所述位线材料层(330)，保留位于同一所述位线槽(310)中的所述阻挡层(320)和所述位线材料层(330)，形成所述位线(300)。
  5. 根据权利要求2所述的半导体结构的形成方法，其中，在所述第一方向上，所述叠层结构(200)包括靠近所述位线(300)的第一区域(D1)和远离所述位线(300)的第二区域(D2)；
    形成多个有源层(500)，包括：
    在所述叠层结构(200)内形成多个第二沟槽(240)，每个所述第二沟槽(240)沿所述第一方向延伸，并贯穿所述叠层结构(200)；
    在每个所述第二沟槽(240)内形成填充材料层(250)，所述填充材料层(250)填满所述第二沟槽(240)；
    在所述第二区域(D2)内形成第三沟槽(260)，所述第三沟槽(260)沿所述第二方向延伸，并与每个所述第二沟槽(240)垂直相交；
    基于所述第三沟槽(260)去除部分所述牺牲层(220)，在被去除的所述牺牲层(220)对应的位置形成第一刻蚀孔(270)，在所述第二方向上，所述第一刻蚀孔(270)贯穿所述第二区域(D2)延伸至所述第一区域(D1)并暴露所述位线(300)；
    向所述第一刻蚀孔(270)中填充导电材料形成导电材料层(50)，去除部分所述导电材料 层(50)，在位于所述第一区域(D1)的每个所述第一刻蚀孔(270)中形成所述有源层(500)。
  6. 根据权利要求5所述的半导体结构的形成方法，其中，去除部分所述导电材料层(50)，在位于所述第一区域(D1)的每个所述第一刻蚀孔(270)中形成所述有源层(500)，包括：
    基于所述第三沟槽(260)刻蚀位于所述第二区域(D2)的所述第一刻蚀孔(270)中的所述导电材料层(50)，保留位于所述第一区域(D1)的所述第一刻蚀孔(270)中的所述导电材料层(50)，形成所述有源层(500)。
  7. 根据权利要求5或6所述的半导体结构的形成方法，其中，形成电容结构(600)包括：
    所述电容结构(600)包括多个延伸结构(610)，每个所述延伸结构(610)位于所述第二区域(D2)的每个所述第一刻蚀孔(270)中，所述延伸结构(610)沿所述第一方向延伸，且与每个所述有源层(500)接触连接。
  8. 根据权利要求7所述的半导体结构的形成方法，其中，形成电容结构(600)，包括：
    形成下电极层(601)，覆盖所述第三沟槽(260)的侧壁以及位于所述第二区域(D2)的所述第一刻蚀孔(270)的侧壁；
    形成电容介质层(602)，覆盖所述下电极层(601)；
    形成上电极层(603)，覆盖所述电容介质层(602)；
    形成半导体层(604)，所述半导体层(604)覆盖所述上电极层(603)，并填满所述第三沟槽(260)以及位于所述第二区域(D2)的所述第一刻蚀孔(270)。
  9. 根据权利要求8所述的半导体结构的形成方法，其中，形成多条字线(700)，包括：
    去除位于所述第一区域(D1)的部分所述支撑层(210)，形成多个字线槽(710)，每个所述字线槽(710)沿所述第三方向延伸，且暴露出每个所述有源层(500)的部分侧壁，多个所述字线槽(710)在所述第二方向上间隔分布；
    形成栅氧层(800)，所述栅氧层(800)覆盖暴露出来的所述有源层(500)的部分侧壁；
    形成字线材料层(71)，所述字线材料层(71)覆盖所述栅氧层(800)，并填满所述字线槽(710)，位于同一所述字线槽(710)中的所述字线材料层(71)形成所述字线(700)。
  10. 根据权利要求4-9中任一项所述的半导体结构的形成方法，其中，所述半导体结构的形成方法还包括：
    在所述第一沟槽(230)内形成介质层(400)，所述介质层(400)填满所述第一沟槽(230)，所述位线(300)位于所述介质层(400)的两侧，且与所述介质层(400)接触连接。
  11. 根据权利要求10所述的半导体结构的形成方法，其中，所述半导体结构的形成方法还包括：
    沿所述第一方向去除部分所述支撑层(210)、部分所述牺牲层(220)、部分所述介质层(400)和部分所述位线(300)，形成叠层阶梯(280)，所述叠层阶梯(280)的端面暴露所述支撑层(210)、所述牺牲层(220)和所述位线(300)的侧壁，在所述叠层阶梯(280)的端面形成多个位线台阶(360)，所述位线台阶(360)包括在所述第三方向间隔分布的多条所述位线(300)，多条所述位线(300)的长度沿所述衬底(100)的顶面至底面的方向逐渐增加。
  12. 根据权利要求11所述的半导体结构的形成方法，其中，所述半导体结构的形成方法还包括：
    形成隔离层(900)，所述隔离层(900)覆盖多条所述位线(300)和多条所述字线(700)的表面。
  13. 根据权利要求12所述的半导体结构的形成方法，其中，所述半导体结构的形成方法还包括：
    形成多个位线接触插塞(350)，多个所述位线接触插塞(350)分别和多条所述位线(300)一一对应连接；
    形成多个字线接触插塞(730)，多个所述字线接触插塞(730)分别和多条所述字线(700)一一对应连接，其中，多个所述位线接触插塞(350)和多个所述字线接触插塞(730)形成于所述隔离层(900)中。
  14. 根据权利要求1至13任一项所述的半导体结构的形成方法，其中，所述半导体结构的形成方法还包括：
    在所述衬底(100)和所述叠层结构(200)之间形成衬底隔离层(110)。
  15. 一种半导体结构，包括：
    衬底(100)；
    多条位线(300)，每条所述位线(300)沿第二方向延伸，多条所述位线(300)在第三方向间隔设置；
    多个有源层(500)，每个所述有源层(500)与每条所述位线(300)处于同层，且位于每条所述位线(300)的侧面，每个所述有源层的第一端(501)和每条所述位线(300)连接；
    电容结构(600)，所述电容结构(600)形成于所述有源层的第二端(502)，所述电容结构(600)和每个所述有源层(500)连接；
    多条字线(700)，多条所述字线(700)在第二方向间隔设置，每条所述字线(700)垂直连接每个所述有源层(500)，所述字线(700)覆盖每个所述有源层(500)的部分侧壁。
  16. 根据权利要求15所述的半导体结构，其中，所述电容结构(600)包括多个延伸结构(610)，所述延伸结构(610)沿第一方向延伸，并电性连接位于所述第一方向上的每个所述有源层(500)。
  17. 根据权利要求16所述的半导体结构，其中，所述半导体结构还包括：
    多个位线接触插塞(350)，多个所述位线接触插塞(350)分别和多条所述位线(300)一一对应连接；其中，多条所述位线(300)的长度沿所述衬底(100)的顶面至底面的方向逐渐增加；
    多个字线接触插塞(730)，多个所述字线接触插塞(730)分别和多条所述字线(700)一一对应连接。
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