WO2024021538A1 - 高低电平转换电路 - Google Patents

高低电平转换电路 Download PDF

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Publication number
WO2024021538A1
WO2024021538A1 PCT/CN2023/072064 CN2023072064W WO2024021538A1 WO 2024021538 A1 WO2024021538 A1 WO 2024021538A1 CN 2023072064 W CN2023072064 W CN 2023072064W WO 2024021538 A1 WO2024021538 A1 WO 2024021538A1
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voltage
unit
output
low
switch
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PCT/CN2023/072064
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English (en)
French (fr)
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严波
李建伟
王悦
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普源精电科技股份有限公司
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Publication of WO2024021538A1 publication Critical patent/WO2024021538A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

Definitions

  • This application relates to level conversion technology, for example, to a high and low level conversion circuit.
  • high-voltage processes are usually required, such as in high-low level conversion circuits using inverters and metal-oxide semiconductor field-effect transistors (MOS).
  • MOS metal-oxide semiconductor field-effect transistors
  • Devices and MOS tubes need to use high-voltage processes, but high-voltage processes will affect the normal operation of MOS tubes.
  • level conversion is difficult to achieve due to the safe operating area of the transistors.
  • This application provides a high-low level conversion circuit to ensure the reliability of level conversion.
  • This application provides a high-low level conversion circuit, including: a high-voltage to low-voltage module, a low-voltage to high-voltage module, a first target chip and a second target chip;
  • the low-voltage to high-voltage module includes a switch unit and a level shift unit.
  • the input end of the level shift unit is configured to receive the level signal of the second target chip.
  • the output end of the level shift unit is electrically connected to the control end of the switch unit.
  • the two input terminals of the switch unit are configured to be input with different voltages, and the level shifting unit is configured to control the path state of the two input terminals and the output terminal of the switch unit;
  • the first target chip is electrically connected to the input terminal of the high-voltage to low-voltage converter module, and is electrically connected to the output terminal of the switch unit;
  • the second target chip is communicatively connected to the first target chip and is electrically connected to the output end of the high-voltage to low-voltage module;
  • the voltage that the first target chip can withstand is greater than the voltage that the second target chip can withstand
  • the high-voltage to low-voltage conversion module is configured to convert the level output by the first target chip and transmit the converted level to output to the second target chip
  • the low-voltage to high-voltage module is configured to convert the level output by the second target chip, and transmit the converted level to the first target chip, so that the first target chip and the second target chip Normal communication.
  • Figure 1 is a schematic structural diagram of a high-low level conversion circuit provided by an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of a low-voltage to high-voltage module provided by an embodiment of the present application
  • Figure 3 is a schematic diagram of a low-voltage to high-voltage input and output provided by an embodiment of the present application
  • Figure 4 is a schematic structural diagram of a MOS transistor circuit provided by an embodiment of the present application.
  • Figure 5 is a schematic structural diagram of a high-voltage to low-voltage module provided by an embodiment of the present application.
  • Figure 6 is a schematic diagram of a high-voltage to low-voltage input and output provided by an embodiment of the present application.
  • Figure 1 is a structural block diagram of a high-low level conversion circuit provided by an embodiment of the present application.
  • the high-low level conversion circuit includes: a first target chip 10 , a second target chip 20 , a high-voltage to low-voltage module 30 and a low-voltage to high-voltage module 40 .
  • the low-voltage to high-voltage module 40 includes a switch unit 41 and a level shift unit 42.
  • the input end of the level shift unit 42 is input with the level signal of the second target chip 20.
  • the output end of the level shift unit 42 is connected to the control unit 41. terminals are electrically connected, the two input terminals A and B of the switch unit 41 are input with different voltages, and the level shifting unit 42 is configured to control the path state of the two input terminals and the output terminal of the switch unit; the first target chip 10 is configured to convert high voltage to low voltage.
  • the input terminal of the module 30 is electrically connected and electrically connected with the output terminal of the switch unit 41; the second target chip 20 is communicatively connected with the first target chip 10 and is electrically connected with the output terminal of the high-voltage to low-voltage module 30 and is connected to the level level.
  • the input terminal of the moving module 42 is electrically connected.
  • the voltage that the first target chip 10 can withstand is greater than the voltage that the second target chip 20 can withstand.
  • the high voltage to low voltage conversion module 30 is configured to convert the level output by the first target chip 10 and transmit the converted level to the third target chip 10 .
  • the second target chip 20; the low voltage to high voltage module 40 is configured to convert the level output by the second target chip 20, and transmit the converted level to the first target chip 10, so that the first target chip 10 and the second target chip 10 can communicate with each other.
  • the target chip 20 communicates normally.
  • the voltage that the first target chip 10 can withstand is 0V-3.3V
  • the voltage that the second target chip 20 can withstand is -3.3V-0V.
  • the voltage signal output by the first target chip 10 is converted from high voltage to low voltage through the high voltage to low voltage module 30.
  • the output voltage is lower than the input voltage, making the transmission
  • the voltage to the second target chip 20 is lower than the second target
  • the maximum voltage that the chip 20 can withstand ensures that the second target chip 20 can normally receive the voltage signal.
  • the voltage signal output by the second target chip 20 is transmitted to the level shifting unit 42 of the low voltage to high voltage module 40.
  • the level shifting unit 42 adjusts the input voltage signal according to the input voltage signal.
  • the corresponding voltage magnitude controls the working state of the switch unit 41 .
  • the switch unit 41 is controlled to be connected to the path transmitting the 0V voltage.
  • the switch unit 41 is controlled to be connected to the path transmitting the 3.3V voltage.
  • the path is turned on, thereby realizing the transformation from low voltage to high voltage, so that the voltage transmitted to the first target chip 10 is higher than the minimum voltage that the first target chip 10 can withstand, ensuring that the first target chip 10 can normally receive the voltage signal, thereby realizing the second target chip 10. Normal communication between the first target chip 10 and the second target chip 20 .
  • first target chip 10 and the second target chip 20 may also be two target modules, which are schematically illustrated here without limitation.
  • the high-low level conversion circuit includes: a high-voltage to low-voltage module, a low-voltage to high-voltage module, a first target chip, and a second target chip; the low-voltage to high-voltage module includes a switch unit and a level shifting unit.
  • the level shifting unit The level signal of the second target chip is input to the input end of Control the path status of the two input terminals and the output terminal of the switch unit; the first target chip is electrically connected to the input terminal of the high-voltage to low-voltage module, and is electrically connected to the output terminal of the switch unit; the second target chip is communicatively connected to the first target chip , and is electrically connected to the output end of the high-voltage to low-voltage module; wherein the voltage that the first target chip can withstand is greater than the voltage that the second target chip can withstand, and the high-voltage to low-voltage module is configured to convert the level output by the first target chip , and transmit the converted level to the second target chip; the low-voltage to high-voltage conversion module is configured to convert the level output by the second target chip, and transmit the converted level to the first target chip, so that the second target chip One target chip communicates normally with the second target chip.
  • the high-low level conversion circuit provided in this embodiment performs high-voltage to low-voltage conversion through the high-voltage to low-voltage module, and controls the working state of the switch unit through the level translation unit of the low-voltage to high-voltage module to realize low-voltage to high-voltage conversion and ensure the level. Conversion reliability.
  • FIG. 2 is a schematic structural diagram of a low-voltage to high-voltage module provided by an embodiment of the present application.
  • the level shifting unit 42 includes a first level shifting subunit 421 and a second level shifting subunit 422.
  • the input terminal of the level shift sub-unit 421 and the input terminal of the second level shift sub-unit 422 are both used as the input terminals of the level shift unit 42.
  • the two power terminals of the first level shift sub-unit 421 are connected to the first power supply respectively. and the second power supply.
  • the two power supply terminals of the second level shift subunit 422 are electrically connected to the first power supply and the second power supply respectively.
  • the output terminal of the first level shift subunit 421 and the second level shifter is electrically connected to the two control terminals of the switch unit 41 respectively, and the two input terminals of the switch unit 41 are electrically connected to the first power supply and the second power supply respectively.
  • FIG. 3 is a schematic diagram of a low-voltage to high-voltage input and output provided by an embodiment of the present application.
  • the first level shift subunit 421 and the second level shift subunit 422 can control the on/off of the switch unit 41 .
  • the voltage V1 input by the first level shift subunit 421 is a ground (GND) voltage
  • a high level is output
  • the path connecting the switch unit 41 and the first power supply is turned on, and the switch unit 41 outputs the first power transmission voltage (the voltage transmitted by the first power supply may be a voltage greater than zero).
  • the voltage V2 input by the second level shift subunit 422 is the voltage of the second power supply (the voltage transmitted by the second power supply may be a voltage less than zero), it outputs a high level, the switch unit 41 is connected to the ground path, and the switch Unit 41 outputs the GND voltage, thereby realizing low voltage conversion to high voltage.
  • first level shift subunit 421 and the second level shift subunit 422 have the same structure, and both the first level shift subunit 421 and the second level shift subunit 422 are MOS tube circuits.
  • FIG. 4 is a schematic structural diagram of a MOS transistor circuit provided by an embodiment of the present application.
  • the MOS transistor circuit shown in FIG. 4 is the circuit of the first level shift subunit 421 and the circuit of the second level shift subunit 422.
  • the output level can also be different to realize the control of the switch unit 41.
  • the working process of the MOS tube circuit can be referred to related technologies and will not be described in detail here.
  • the switch unit 41 includes a first switch T1 and a second switch T2.
  • the first terminal of the first switch T1 is used as an input terminal of the switch unit 41 and the first terminal of the second switch T2 is used as an input terminal.
  • the other input terminal of the switch unit 41, the second terminal of the first switch T1 is electrically connected to the second terminal of the second switch T2.
  • the control terminal of the first switch T1 is used as a control terminal of the switch unit 41, and the second terminal of the second switch T2
  • the control end of is used as the other control end of the switch unit 41 , and the second end of the first switch T1 and the second end of the second switch T2 are both used as the output end of the switch unit 41 .
  • the first level shift subunit 421 and the second level shift subunit 422 may control the on/off of the first switch T1 and the second switch T2 respectively. For example, when the level output by the first level shift subunit 421 to the control terminal of the first switch T1 is low, the first switch T1 is turned on. When the level output by the second level shift subunit 422 to the control terminal of the second switch T2 is low level, the second switch T2 is turned on.
  • the switch unit 41 When the first switch T1 is turned on and the second switch T2 is turned off, the switch unit 41 outputs the voltage of the first power supply; when the first switch T1 is turned off and the second switch T2 is turned on, the switch unit 41 outputs the GND voltage, so that Realize the control that the output is the voltage of the first power supply or the GND voltage.
  • the voltage output by the first power supply is a positive voltage
  • the voltage output by the second power supply is a negative voltage
  • the voltage difference between the positive voltage and the negative voltage is greater than the preset voltage value
  • the positive voltage may be 3.3V and the negative voltage may be -3.3V.
  • the output of the switch unit 41 when the input of the first level shift subunit 421 is the GND voltage, the output of the switch unit 41 is 3.3V, and when the input of the second level shift subunit 422 is -3.3V, the output of the switch unit 41 is the GND voltage, thereby achieving When the input is -3.3V-0V, the output is 0V-3.3V.
  • the high-voltage conversion module 30 can achieve an output of -3.3V-0V when the input is 0V-3.3V.
  • the above preset voltage values, positive voltage and negative voltage values can be set according to the actual needs of the circuit. This is not limited.
  • the first switch T1 and the second switch T2 are both turned off, and the output of the switch unit 41 is in a high impedance state.
  • the level shifting unit 42 can be used to control both the first switch T1 and the second switch T2 to be turned off, so that the high-impedance state can be achieved.
  • FIG. 5 is a schematic structural diagram of a high-voltage to low-voltage module provided by an embodiment of the present application.
  • the high-voltage to low-voltage module 30 includes an amplifier 31 and a buffer.
  • the first terminal VIP of the input stage of the amplifier 31 is used as the input terminal of the high-voltage to low-voltage module 30 .
  • the second terminal VIN of the input stage of the amplifier 31 is input to the preset reference voltage. VREF, the two power terminals of the input stage of the amplifier 31 are electrically connected to the first power supply and the second power supply respectively, the first terminal of the output stage of the amplifier 31 is set to ground GND, and the second terminal of the output stage of the amplifier 31 is connected to the second power supply.
  • the power supply is electrically connected.
  • the third terminal of the output stage of the amplifier 31 is electrically connected to the input terminal of the buffer buffer.
  • the two power terminals of the buffer buffer are electrically connected to the second power supply and ground respectively.
  • the output terminal of the buffer buffer is used as a high voltage. to the output of the low-voltage module.
  • the voltage output by the output stage is determined based on the magnitude of the input voltage and the preset reference voltage VREF. If the voltage input to the first terminal VIP of the input stage of the amplifier 31 is greater than the preset reference voltage VREF input to the second terminal VIN of the input stage of the amplifier 31, the voltage output by the output stage of the amplifier 31 is the GND voltage, and the amplifier 31 When the voltage input to the first terminal VIP of the input stage is greater than the preset reference voltage VREF input to the second terminal VIN of the input stage of the amplifier 31, the voltage output by the output stage of the amplifier 31 is output through the buffer, and the buffer buffer buffer The voltage Vo output by the output terminal is the voltage of the second power supply (less than GND), thereby realizing high voltage conversion to low voltage.
  • the high voltage to low voltage module 30 also includes a reference voltage unit 32.
  • the second terminal VIN of the input stage of the amplifier 31 is electrically connected to the output terminal of the reference voltage unit 32.
  • the input terminal of the reference voltage unit 32 is connected to the output stage of the amplifier 31.
  • the third terminal is electrically connected, and the output terminal of the reference voltage unit 32 outputs the preset reference voltage VREF.
  • FIG. 6 is a schematic diagram of a high-voltage to low-voltage input and output provided by an embodiment of the present application.
  • the input voltage of amplifier 31 starts to rise from GND.
  • the voltage of the output stage of amplifier 31 will rise.
  • the rise of the output stage voltage of amplifier 31 will reduce the predetermined voltage.
  • the reference voltage VREF the preset reference voltage VREF drops to VREF-dV
  • the differential input amplitude of the input stage of the amplifier 31 increases, the rising speed of the output stage voltage will increase, the output stage voltage can reach the GND voltage faster, and the input voltage will increase from the
  • the voltage of a power supply (greater than GND) begins to drop.
  • the voltage of the output stage of the amplifier 31 will decrease, and the differential input amplitude of the input stage of the amplifier 31 will increase to achieve positive feedback.
  • the voltage drop rate of the output stage of the amplifier 31 will increase, thereby increasing the Quickly drops to the voltage of the second power supply (less than GND).
  • the preset reference voltage is negatively related to the voltage output by the third terminal of the output stage of the amplifier, The voltage output by the third terminal of the amplifier's output stage increases and the preset reference voltage decreases.
  • the increase in the output stage voltage of the amplifier 31 can control the preset reference voltage VREF output by the reference voltage unit 32 to decrease. This setting can achieve positive feedback. The process is as described in the previous paragraph and will not be repeated here.
  • the voltage output by the first power supply is a positive voltage
  • the preset reference voltage is any voltage value between 0V and the positive voltage
  • the positive voltage may be 3.3V
  • the preset reference voltage is a voltage value between 0-3.3V.
  • the output is the GND voltage, which can realize level conversion from high voltage to low voltage.
  • the input of the low voltage to high voltage module 40 is the GND voltage
  • the output is 3.3V, which can realize level conversion from low voltage to high voltage.

Abstract

本申请提供了一种高低电平转换电路。该电路包括：高压转低压模块、低压转高压模块、第一目标芯片以及第二目标芯片；低压转高压模块，包括开关单元和电平平移单元，电平平移单元的输入端设置为被输入第二目标芯片的电平信号，电平平移单元的输出端与开关单元的控制端电连接，开关单元的两个输入端设置为被输入不同电压，电平平移单元设置为控制开关单元的两个输入端与输出端的通路状态；第一目标芯片，与高压转低压模块的输入端电连接，并与开关单元的输出端电连接；第二目标芯片，与第一目标芯片通信连接，并与高压转低压模块的输出端电连接；其中，第一目标芯片可承受的电压大于第二目标芯片可承受的电压。

Description

高低电平转换电路
本申请要求在2022年07月29日提交中国专利局、申请号为202210907553.X的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及电平转换技术，例如涉及一种高低电平转换电路。
背景技术
对于需要通信的两个设备或模块，当两者的电压规格不同时，无法直接相连，此时就需要进行电平转换。如在电源领域的复杂电路中，被控制的高低电平不一致，需要进行高低电平转换。
高低电平转换电路中，通常需要使用高压工艺，如使用反相器和金属-氧化物半导体场效应晶体管(金属-氧化物半导体场效应晶体管，MOS)管的高低电平转换电路中，反相器和MOS管需要使用高压工艺，但高压工艺会影响MOS管的正常工作，而在低压工艺中，由于晶体管的安全工作区问题，电平转换很难实现。
发明内容
本申请提供了一种高低电平转换电路，以保证电平转换的可靠性。
本申请提供了一种高低电平转换电路，包括：高压转低压模块、低压转高压模块、第一目标芯片以及第二目标芯片；
低压转高压模块，包括开关单元和电平平移单元，电平平移单元的输入端设置为被输入第二目标芯片的电平信号，电平平移单元的输出端与开关单元的控制端电连接，开关单元的两个输入端设置为被输入不同电压，电平平移单元设置为控制开关单元的两个输入端与输出端的通路状态；
第一目标芯片，与高压转低压模块的输入端电连接，并与开关单元的输出端电连接；
第二目标芯片，与第一目标芯片通信连接，并与高压转低压模块的输出端电连接；
其中，第一目标芯片可承受的电压大于第二目标芯片可承受的电压，高压转低压模块设置为对第一目标芯片输出的电平进行转换，并将转换后的电平传 输至第二目标芯片；低压转高压模块设置为对第二目标芯片输出的电平进行转换，并将转换后的电平传输至第一目标芯片，以使第一目标芯片与第二目标芯片正常通信。
附图说明
图1是本申请实施例提供的一种高低电平转换电路的结构示意图；
图2是本申请实施例提供的一种低压转高压模块的结构示意图；
图3是本申请实施例提供的一种低压转高压输入输出的示意图；
图4是本申请实施例提供的一种MOS管电路的结构示意图；
图5是本申请实施例提供的一种高压转低压模块的结构示意图；
图6是本申请实施例提供的一种高压转低压输入输出的示意图。
具体实施方式
下面结合附图和实施例对本申请进行说明。此处所描述的具体实施例仅仅用于解释本申请。为了便于描述，附图中仅示出了与本申请相关的部分。
图1是本申请实施例提供的一种高低电平转换电路的结构框图。参考图1，高低电平转换电路包括：第一目标芯片10、第二目标芯片20、高压转低压模块30和低压转高压模块40。
低压转高压模块40包括开关单元41和电平平移单元42，电平平移单元42的输入端被输入第二目标芯片20的电平信号，电平平移单元42的输出端与开关单元41的控制端电连接，开关单元41的两个输入端A和B被输入不同电压，电平平移单元42设置为控制开关单元的两个输入端与输出端的通路状态；第一目标芯片10与高压转低压模块30的输入端电连接，并与开关单元41的输出端电连接；第二目标芯片20与第一目标芯片10通信连接，且与高压转低压模块30的输出端电连接，并与电平平移模块42的输入端电连接。第一目标芯片10可承受的电压大于第二目标芯片20可承受的电压，高压转低压模块30设置为对第一目标芯片10输出的电平进行转换，并将转换后的电平传输至第二目标芯片20；低压转高压模块40设置为对第二目标芯片20输出的电平进行转换，并将转换后的电平传输至第一目标芯片10，以使第一目标芯片10与第二目标芯片20正常通信。
示例性地，第一目标芯片10可承受的电压为0V-3.3V，第二目标芯片20可承受的电压为-3.3V-0V。第一目标芯片10需向第二目标芯片20传输电压信号时，第一目标芯片10输出的电压信号通过高压转低压模块30进行高压转低压的变换，输出的电压低于输入的电压，使得传输至第二目标芯片20的电压低于第二目标 芯片20可承受的最大电压，保证第二目标芯片20能够正常接收电压信号。第二目标芯片20需向第一目标芯片10传输电压信号时，第二目标芯片20输出的电压信号传输至低压转高压模块40的电平平移单元42，电平平移单元42根据输入的电压信号对应的电压大小，控制开关单元41的工作状态。如电平平移单元42输入的电压为-3.3V时，控制开关单元41与传输0V电压的通路导通，电平平移单元42输入的电压为0V时，控制开关单元41与传输3.3V电压的通路导通，从而实现低压转高压的变换，使得传输至第一目标芯片10的电压高于第一目标芯片10可承受的最小电压，保证第一目标芯片10能够正常接收电压信号，从而实现第一目标芯片10与第二目标芯片20的正常通信。
另外，第一目标芯片10与第二目标芯片20也可以是两个目标模块，在此示意性说明，不做限定。
本实施例提供的高低电平转换电路，包括：高压转低压模块、低压转高压模块、第一目标芯片和第二目标芯片；低压转高压模块包括开关单元和电平平移单元，电平平移单元的输入端被输入第二目标芯片的电平信号，电平平移单元的输出端与开关单元的控制端电连接，开关单元的两个输入端设置为被输入不同电压，电平平移单元设置为控制开关单元的两个输入端与输出端的通路状态；第一目标芯片与高压转低压模块的输入端电连接，并与开关单元的输出端电连接；第二目标芯片与第一目标芯片通信连接，并与高压转低压模块的输出端电连接；其中，第一目标芯片可承受的电压大于第二目标芯片可承受的电压，高压转低压模块设置为对第一目标芯片输出的电平进行转换，并将转换后的电平传输至第二目标芯片；低压转高压模块设置为对第二目标芯片输出的电平进行转换，并将转换后的电平传输至第一目标芯片，以使第一目标芯片与第二目标芯片正常通信。本实施例提供的高低电平转换电路，通过高压转低压模块进行高压转低压的变换，通过低压转高压模块的电平平移单元控制开关单元的工作状态，实现低压转高压的变换，保证电平转换的可靠性。
示例性地，图2是本申请实施例提供的一种低压转高压模块的结构示意图，电平平移单元42包括第一电平平移子单元421和第二电平平移子单元422，第一电平平移子单元421的输入端和第二电平平移子单元422的输入端均被作为电平平移单元42的输入端，第一电平平移子单元421的两个电源端分别与第一电源和第二电源电连接，第二电平平移子单元422的两个电源端分别与第一电源和第二电源电连接，第一电平平移子单元421的输出端和第二电平平移子单元422的输出端分别与开关单元41的两个控制端电连接，开关单元41的两个输入端分别与第一电源和第二电源电连接。
示例性地，图3是本申请实施例提供的一种低压转高压输入输出的示意图。 结合图2和图3，第一电平平移子单元421和第二电平平移子单元422可控制开关单元41的通断。例如，第一电平平移子单元421输入的电压V1为接地(Ground，GND)电压时，输出高电平，开关单元41与第一电源连接的通路导通，开关单元41输出第一电源传输的电压(第一电源传输的电压可以是大于零的电压)。第二电平平移子单元422输入的电压V2为第二电源的电压(第二电源传输的电压可以是小于零的电压)时，输出高电平，开关单元41与接地的通路导通，开关单元41输出GND电压，从而实现低压转高压。
示例性地，第一电平平移子单元421和第二电平平移子单元422的结构相同，第一电平平移子单元421和第二电平平移子单元422均为MOS管电路。
示例性地，图4是本申请实施例提供的一种MOS管电路的结构示意图。图4所示的MOS管电路即为第一电平平移子单元421的电路，也是第二电平平移子单元422的电路。MOS管电路的输入电平不同时输出电平也可不同，以实现对开关单元41的控制，MOS管电路的工作过程可参考相关技术，在此不再赘述。
示例性地，参考图2，开关单元41包括第一开关T1和第二开关T2，第一开关T1的第一端被作为开关单元41的一个输入端，第二开关T2的第一端被作为开关单元41的另一个输入端，第一开关T1的第二端与第二开关T2的第二端电连接，第一开关T1的控制端被作为开关单元41的一个控制端，第二开关T2的控制端被作为开关单元41的另一个控制端，第一开关T1的第二端与第二开关T2的第二端均被作为开关单元41的输出端。
示例性地，参考图2和图3，第一电平平移子单元421和第二电平平移子单元422可分别控制第一开关T1和第二开关T2的通断。例如，第一电平平移子单元421输出至第一开关T1的控制端的电平为低电平时，第一开关T1导通。第二电平平移子单元422输出至第二开关T2的控制端的电平为低电平时，第二开关T2导通。当第一开关T1导通，第二开关T2关断时，开关单元41输出第一电源的电压；当第一开关T1关断，第二开关T2导通时，开关单元41输出GND电压，从而实现输出为第一电源的电压或GND电压的控制。
示例性地，第一电源输出的电压为正电压，第二电源输出的电压为负电压，正电压和负电压的电压差大于预设电压值。
示例性地，正电压可以是3.3V，负电压可以是-3.3V。例如，第一电平平移子单元421输入为GND电压时，开关单元41输出为3.3V，第二电平平移子单元422输入为-3.3V时，开关单元41输出为GND电压，从而实现在输入-3.3V-0V时，输出为0V-3.3V。同样，高压转电压模块30可实现在输入0V-3.3V时，输出为-3.3V-0V。
上述预设电压值、正电压和负电压的数值可根据电路的实际需求设定，在 此不做限定。
示例性地，第一开关T1和第二开关T2均断开，开关单元41的输出为高阻态。当需要开关单元41的输出为高阻态时，可通过电平平移单元42控制第一开关T1和第二开关T2均断开，即可实现高阻态。
示例性地，图5是本申请实施例提供的一种高压转低压模块的结构示意图。高压转低压模块30包括放大器31和缓冲器Buffer，放大器31的输入级的第一端VIP被作为高压转低压模块30的输入端，放大器31的输入级的第二端VIN被输入预设参考电压VREF，放大器31的输入级的两个电源端分别与第一电源和第二电源电连接，放大器31的输出级的第一端设置为接地GND，放大器31的输出级的第二端与第二电源电连接，放大器31的输出级的第三端与缓冲器buffer的输入端电连接，缓冲器buffer的两个电源端分别与第二电源以及地电连接，缓冲器buffer的输出端被作为高压转低压模块的输出端。
示例性地，参考图5，放大器31的输入级的第一端VIP被输入电压时，根据被输入的电压与预设参考电压VREF的大小，确定输出级输出的电压大小。如放大器31的输入级的第一端VIP被输入的电压大于放大器31的输入级的第二端VIN被输入的预设参考电压VREF时，放大器31的输出级输出的电压为GND电压，放大器31的输入级的第一端VIP被输入的电压大于放大器31的输入级的第二端VIN被输入的预设参考电压VREF时，放大器31的输出级输出的电压经过缓冲器输出，缓冲器buffer的输出端输出的电压Vo为第二电源的电压(小于GND)，从而实现高压转低压。
示例性地，高压转低压模块30还包括参考电压单元32，放大器31的输入级的第二端VIN与参考电压单元32的输出端电连接，参考电压单元32的输入端与放大器31的输出级的第三端电连接，参考电压单元32的输出端输出预设参考电压VREF。
示例性地，图6是本申请实施例提供的一种高压转低压输入输出的示意图。参考图5和图6，放大器31被输入的电压从GND开始升高，当被输入的电压大于VREF时，放大器31的输出级的电压会升高，放大器31的输出级电压升高会降低预设参考电压VREF，预设参考电压VREF下降到VREF-dV，放大器31的输入级差分输入幅度增加，输出级电压上升速度会升高，输出级电压能够更快的达到GND电压，输入电压从第一电源的电压(大于GND)开始下降。当放大器31输入的电压小于VREF-dV时，放大器31的输出级的电压会降低，放大器31的输入级差分输入幅度增加，实现正反馈，放大器31的输出级电压下降速度会升高，从而更快的降到第二电源的电压(小于GND)。
示例性地，预设参考电压与放大器的输出级的第三端输出的电压负相关， 放大器的输出级的第三端输出的电压升高，预设参考电压降低。
放大器31的输出级电压升高可控制参考电压单元32输出的预设参考电压VREF降低，这样设置可实现正反馈，过程如上一段描述，在此不再赘述。
示例性地，第一电源输出的电压为正电压，预设参考电压为0V至正电压之间的任意电压值。
示例性地，正电压可以是3.3V，预设参考电压为0-3.3V之间的一个电压值。高压转低压模块30的输入为3.3V时，输出为GND电压，可实现高压转低压的电平转换。低压转高压模块40的输入为GND电压时，输出为3.3V，可实现低压转高压的电平转换。

Claims (10)

  1. 一种高低电平转换电路，包括：高压转低压模块、低压转高压模块、第一目标芯片以及第二目标芯片；
    所述低压转高压模块，包括开关单元和电平平移单元，所述电平平移单元的输入端设置为被输入所述第二目标芯片的电平信号，所述电平平移单元的输出端与所述开关单元的控制端电连接，所述开关单元的两个输入端设置为被输入不同电压，所述电平平移单元设置为控制所述开关单元的两个输入端与输出端的通路状态；
    所述第一目标芯片，与所述高压转低压模块的输入端电连接，并与所述开关单元的输出端电连接；
    所述第二目标芯片，与所述第一目标芯片通信连接，并与所述高压转低压模块的输出端电连接；
    其中，所述第一目标芯片可承受的电压大于所述第二目标芯片可承受的电压，所述高压转低压模块设置为对所述第一目标芯片输出的电平进行转换，并将转换后的电平传输至所述第二目标芯片；所述低压转高压模块设置为对所述第二目标芯片输出的电平进行转换，并将转换后的电平传输至所述第一目标芯片，以使所述第一目标芯片与所述第二目标芯片正常通信。
  2. 根据权利要求1所述的高低电平转换电路，其中，所述电平平移单元包括第一电平平移子单元和第二电平平移子单元，所述第一电平平移子单元的输入端和所述第二电平平移子单元的输入端均被作为所述电平平移单元的输入端，所述第一电平平移子单元的两个电源端分别与第一电源和第二电源电连接，所述第二电平平移子单元的两个电源端分别与所述第一电源和所述第二电源电连接，所述第一电平平移子单元的输出端和所述第二电平平移子单元的输出端分别与所述开关单元的两个控制端电连接，所述开关单元的两个输入端分别与所述第一电源和所述第二电源电连接。
  3. 根据权利要求2所述的高低电平转换电路，其中，所述第一电平平移子单元和所述第二电平平移子单元的结构相同，所述第一电平平移子单元和所述第二电平平移子单元均为金属-氧化物半导体场效应晶体管MOS管电路。
  4. 根据权利要求2所述的高低电平转换电路，其中，所述开关单元包括第一开关和第二开关，所述第一开关的第一端被作为所述开关单元的一个输入端，所述第二开关的第一端被作为所述开关单元的另一个输入端，所述第一开关的第二端与所述第二开关的第二端电连接，所述第一开关的控制端被作为所述开关单元的一个控制端，所述第二开关的控制端被作为所述开关单元的另一个控制端，所述第一开关的第二端与所述第二开关的第二端均被作为所述开关单元 的输出端。
  5. 根据权利要求2所述的高低电平转换电路，其中，所述第一电源输出的电压为正电压，所述第二电源输出的电压为负电压，所述正电压和所述负电压的电压差大于预设电压值。
  6. 根据权利要求4所述的高低电平转换电路，其中，所述第一开关和所述第二开关均断开，所述开关单元的输出为高阻态。
  7. 根据权利要求1所述的高低电平转换电路，其中，所述高压转低压模块包括放大器和缓冲器，所述放大器的输入级的第一端被作为所述高压转低压模块的输入端，所述放大器的输入级的第二端设置为被输入预设参考电压，所述放大器的输入级的两个电源端分别与第一电源和第二电源电连接，所述放大器的输出级的第一端设置为接地，所述放大器的输出级的第二端与所述第二电源电连接，所述放大器的输出级的第三端与所述缓冲器的输入端电连接，所述缓冲器的两个电源端分别与第二电源以及地电连接，所述缓冲器的输出端被作为作为所述高压转低压模块的输出端。
  8. 根据权利要求7所述的高低电平转换电路，其中，所述高压转低压模块还包括参考电压单元，所述放大器的输入级的第二端与所述参考电压单元的输出端电连接，所述参考电压单元的输入端与所述放大器的输出级的第三端电连接，所述参考电压单元的输出端设置为输出所述预设参考电压。
  9. 根据权利要求7所述的高低电平转换电路，其中，所述第一电源输出的电压为正电压，所述预设参考电压为0V至所述正电压之间的电压值。
  10. 根据权利要求8所述的高低电平转换电路，其中，所述预设参考电压与所述放大器的输出级的第三端输出的电压负相关，所述放大器的输出级的第三端输出的电压升高，所述预设参考电压降低。
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