WO2020047722A1 - 数据接口、芯片和芯片系统 - Google Patents

数据接口、芯片和芯片系统 Download PDF

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Publication number
WO2020047722A1
WO2020047722A1 PCT/CN2018/103841 CN2018103841W WO2020047722A1 WO 2020047722 A1 WO2020047722 A1 WO 2020047722A1 CN 2018103841 W CN2018103841 W CN 2018103841W WO 2020047722 A1 WO2020047722 A1 WO 2020047722A1
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WO
WIPO (PCT)
Prior art keywords
circuit
data interface
current
mos tube
mos transistor
Prior art date
Application number
PCT/CN2018/103841
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English (en)
French (fr)
Inventor
杨博新
张孟文
易律凡
詹昶
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to CN201880001283.8A priority Critical patent/CN109314515A/zh
Priority to PCT/CN2018/103841 priority patent/WO2020047722A1/zh
Publication of WO2020047722A1 publication Critical patent/WO2020047722A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

Definitions

  • the embodiments of the present application relate to the field of electronic technology, and more specifically, to a data interface, a chip, and a chip system.
  • MCUs microcontroller units
  • current, voltage, or charge can be used as a carrier for transmitting signals.
  • current voltage as a carrier for transmitting signals as an example, data is usually transmitted between the chips using a loop circuit.
  • a data interface, chip and chip system which can reduce costs.
  • a data interface is provided, where the data interface is applied to a transmitting end or half-duplex communication, and the data interface includes:
  • the first transmitting circuit is configured to receive an input signal and output a first current to a first receiving circuit of a counterpart interface connected to the data interface according to the input signal, or from the peer terminal according to the input signal.
  • the first receiving circuit of the interface receives a first current to generate a first voltage signal corresponding to the input signal at the opposite interface.
  • the first sending circuit includes:
  • the current control circuit is controlled by the input signal to control a source of the first MOS tube to output or receive the first current.
  • the first sending circuit further includes:
  • a first bias circuit the first bias circuit is connected to the first MOS transistor through the current control circuit, and the first bias circuit is configured to provide a bias current to the current control circuit.
  • the current control circuit includes:
  • One end of the first switch is used to receive a power supply voltage, the other end of the first switch is connected to one end of the second switch through the first MOS tube, and the other end of the second switch is connected to ground.
  • the current control circuit further includes:
  • the source of the second MOS tube is used to receive the power supply voltage, and the drain of the second MOS tube is connected to one end of the first resistor through the third MOS tube. One end is connected to the ground, and the gate of the third MOS tube is connected to the gate of the first MOS tube.
  • the first bias circuit includes:
  • the source of the fourth MOS tube is used to receive a power supply voltage, the gate of the fourth MOS tube is connected to the drain of the fourth MOS tube, and the drain of the fourth MOS tube passes through the first
  • the current source is connected to the ground, and the gate of the fourth MOS transistor is connected to the gate of the second MOS transistor.
  • the data interface further includes:
  • the first transmitting circuit is connected to one end of a binding line through the electrostatic protection circuit, and the other end of the binding line is used to connect to the first receiving circuit.
  • the data interface is applied to half-duplex communication, and the data interface further includes:
  • the second receiving circuit is connected to one end of the bonding wire through the electrostatic protection circuit, and the other end of the bonding wire is used to connect the second transmitting circuit of the opposite interface;
  • the second receiving circuit is configured to receive a second current from the second transmitting circuit or output a second current to the second transmitting circuit through the binding line and the electrostatic protection circuit, and according to the second The current generates a second voltage signal.
  • the data interface further includes:
  • the first transmitting circuit is connected to the electrostatic protection circuit through the third switch, and the second receiving circuit is connected to the electrostatic protection circuit through the fourth switch.
  • the second receiving circuit includes:
  • the second bias circuit is configured to provide a bias current for the voltage comparison circuit.
  • the voltage comparison circuit is configured to receive or output the second current, and generate the second voltage signal according to the second current. .
  • the voltage comparison circuit includes:
  • the source of the fifth MOS tube is used to receive the power supply voltage
  • the drain of the fifth MOS tube is connected to the drain of the sixth MOS tube
  • the source of the sixth MOS tube is used to receive or output
  • the second current the source of the seventh MOS transistor is used to receive the power supply voltage
  • the drain of the seventh MOS transistor is connected to the drain of the eighth MOS transistor
  • the source of the eighth MOS transistor The electrode is connected to the ground through the second resistor
  • the gate of the fifth MOS transistor is connected to the gate of the seventh MOS transistor
  • the gate of the sixth MOS transistor is connected to the eighth MOS transistor.
  • the gate, and the drain of the eighth MOS transistor is connected to the gate of the eighth MOS transistor.
  • the voltage comparison circuit further includes:
  • the drain of the sixth MOS transistor is connected to the second inverter through the first inverter.
  • the voltage comparison circuit further includes:
  • the source of the sixth MOS transistor is connected to the ground through the third resistor.
  • the voltage comparison circuit further includes:
  • the source of the eighth MOS transistor is connected to one end of the third resistor, the other end of the third resistor is connected to ground through the fourth resistor, and one end of the fourth resistor is connected to the fifth switch. Connected to the other end of the fourth resistor, a signal output by the first inverter is used to control the fifth switch to be turned on or off.
  • the voltage comparison circuit further includes:
  • One end of the sixth switch is used to receive a power supply voltage, and the other end of the sixth switch is connected to a gate of the fifth MOS transistor.
  • the second bias circuit includes:
  • the ninth MOS tube and the second current source are The ninth MOS tube and the second current source.
  • the source of the ninth MOS tube is used to receive a power supply voltage, the gate of the ninth MOS tube is connected to the gate of the fifth MOS tube, and the drain of the ninth MOS tube passes through the second
  • the current source is connected to ground.
  • a data interface is provided.
  • the data interface is applied to a receiving end.
  • the data interface includes:
  • the second receiving circuit is configured to receive a second current from a second sending circuit of a peer interface connected to the data interface, or output a second current to the second sending circuit of the peer interface, and according to The second current generates a second voltage signal.
  • the data interface further includes:
  • the second receiving circuit is connected to one end of a binding line through the electrostatic protection circuit, and the other end of the binding line is used to connect to the second transmitting circuit.
  • the second receiving circuit includes:
  • the second bias circuit is configured to provide a bias current for the voltage comparison circuit.
  • the voltage comparison circuit is configured to receive or output the second current, and generate the second voltage signal according to the second current. .
  • the voltage comparison circuit includes:
  • the source of the fifth MOS tube is used to receive the power supply voltage
  • the drain of the fifth MOS tube is connected to the drain of the sixth MOS tube
  • the source of the sixth MOS tube is used to receive or output
  • the second current the source of the seventh MOS transistor is used to receive the power supply voltage
  • the drain of the seventh MOS transistor is connected to the drain of the eighth MOS transistor
  • the source of the eighth MOS transistor The electrode is connected to the ground through the second resistor
  • the gate of the fifth MOS transistor is connected to the gate of the seventh MOS transistor
  • the gate of the sixth MOS transistor is connected to the eighth MOS transistor.
  • the gate, and the drain of the eighth MOS transistor is connected to the gate of the eighth MOS transistor.
  • the voltage comparison circuit further includes:
  • the drain of the sixth MOS transistor is connected to the second inverter through the first inverter.
  • the voltage comparison circuit further includes:
  • the third resistor of the source of the sixth MOS transistor is connected to the ground through the third resistor.
  • the voltage comparison circuit further includes:
  • the source of the eighth MOS transistor is connected to one end of the second resistor, the other end of the second resistor is connected to the ground through the fourth resistor, and one end of the second resistor is connected to the fifth switch. Connected to the other end of the second resistor, the signal output by the first inverter is used to control the fifth switch to be turned on or off.
  • the voltage comparison circuit further includes:
  • One end of the sixth switch is used to receive a power supply voltage, and the other end of the sixth switch is connected to a gate of the fifth MOS transistor.
  • the second bias circuit includes:
  • the ninth MOS tube and the second current source are The ninth MOS tube and the second current source.
  • the source of the ninth MOS tube is used to receive a power supply voltage, the gate of the ninth MOS tube is connected to the gate of the fifth MOS tube, and the drain of the ninth MOS tube passes through the second
  • the current source is connected to ground.
  • a chip including:
  • a chip system including:
  • a plurality of chips in which the chip and the second chip are connected by at least one of the following data interfaces:
  • the data interface, chip, and chip system provided in the embodiments of the present application use current as a carrier for transmitting signals, and perform data transmission through single-ended output, which avoids data transmission using a circuit design of a loop, which can effectively reduce the data interface cost.
  • the source end of the MOS tube is used as the output end of the first sending circuit of the data interface, which can provide a larger slew rate for the transmission signal during the establishment of the transmission signal, and thus can Improve the establishment speed of the transmission signal, and then realize the high-speed transmission of data.
  • the transmission level of the signal amount can be effectively reduced, thereby reducing the power consumption of the data interface.
  • the use of a common-gate amplifier circuit in the voltage comparison circuit can effectively increase the establishment speed of the voltage signal, thereby achieving high-speed transmission of data.
  • FIG. 1 is a schematic diagram of a chip system according to an embodiment of the present invention.
  • FIG. 2 is a schematic block diagram of a data interface as a transmitting end according to an embodiment of the present application.
  • FIG. 3 is an example of a circuit diagram of a first transmission circuit shown in FIG. 2.
  • FIG. 4 is another example of a circuit diagram of the first transmission circuit shown in FIG. 2.
  • FIG. 5 is a schematic block diagram of a data interface as a receiving end according to an embodiment of the present application.
  • FIG. 6 is an example of a circuit diagram of a second receiving circuit shown in FIG. 5.
  • FIG. 7 is another example of a circuit diagram of the second receiving circuit shown in FIG. 5.
  • FIG. 8 is another example of a circuit diagram of the second receiving circuit shown in FIG. 5.
  • FIG. 9 is an example of a circuit diagram of a chip system according to an embodiment of the present application.
  • the data interface, chip, and chip system of the embodiments of the present invention are applicable to any occasion requiring data communication, and particularly applicable to occasions with high-speed and low-power communication interconnection.
  • the data interface is particularly suitable for data communication between chips. For example, data communication between internal chips of a chip system.
  • each chip needs to be provided with multiple pins, which is too costly.
  • the data interface uses current as a carrier for transmitting signals and performs data transmission through single-ended output, which can effectively reduce the cost of the data interface.
  • FIG. 1 is a schematic block diagram of a chip system 100 according to an embodiment of the present invention.
  • the chip system 100 may include:
  • the data interface 110 the binding line 120, and the data interface 130.
  • the data interface 110 can be regarded as the local data interface
  • the data interface 130 can be regarded as the opposite data interface.
  • the local and the opposite ends are mutually communicating ends, and can be regarded as two in a multi-chip system. Interconnected chips.
  • the data interface 110 may include:
  • the transmitting circuit 111 is connected to one end of the electrostatic protection circuit 113 through the switch 112, and the other end of the electrostatic protection circuit 113 is connected to the data interface 130 through the bonding wire 120.
  • the protection circuit 113 is also connected to the receiving circuit 115 through the switch 114.
  • the data interface 130 may include:
  • the transmitting circuit 135 is connected to one end of the electrostatic protection circuit 133 through the switch 134, and the other end of the electrostatic protection circuit 133 is connected to the data interface 110 through the bonding wire 120.
  • the protection circuit 133 is also connected to the receiving circuit 131 through the switch 132.
  • both the data interface 110 and the data interface 130 may include a set of receiving circuits and transmitting circuits having the same function, so that the data interface 110 and the data interface 130 can implement a half-duplex communication function.
  • the data interface 110 may switch the work between the transmitting circuit 111 and the receiving circuit 115 through the switch 112 and the switch 114, and the data interface 130 may use the switch 132 and the The switch 134 realizes the work switching between the receiving circuit 131 and the transmitting circuit 135.
  • the switches 112 and 132 are closed, the switches 114 and 134 are opened, and the transmitting circuit 111 and the receiving circuit 131 form a transmitting-receiving path.
  • the data interface 110 may be used as a transmitting end, and the data interface 130 may be used as a receiving end.
  • both the data interface 110 and the data interface 130 may include a set of receiving circuits and transmitting circuits having the same function, the specific implementing circuits and / or using processes of the receiving circuits and the transmitting circuits may be different.
  • both the electrostatic protection circuit 113 and the electrostatic protection circuit 133 may be used to prevent static electricity from damaging the device.
  • the embodiment of the present application does not limit the specific implementation of the electrostatic protection circuit.
  • the electrostatic protection circuit 113 or the electrostatic protection circuit 133 may be integrated on the pad (PAD), or may be separately provided from the PAD.
  • the electrostatic protection circuit 113 and / or the electrostatic protection circuit 133 only need to meet the requirements of a Charged Device Model (CDM).
  • CDM Charged Device Model
  • the receiving circuit and the transmitting circuit in the data interface 110 or the data interface 130 may share one electrostatic protection circuit as shown in FIG. 1, or may correspond to one electrostatic protection circuit respectively. This embodiment of the present application does not specifically limit this.
  • the bonding line 120 is a connection line for interconnection between chips.
  • chip system 100 shown in FIG. 1 is only an example, but the embodiment itself is not limited thereto.
  • the data interface 110 or the data interface 130 may be used for simplex communication only.
  • the four switches and some devices shown in Figure 1 are optional.
  • the data interface 110 may include only a transmitting circuit 111 and an electrostatic protection circuit 113, or the data interface 110 may include only a receiving circuit 115 and an electrostatic protection circuit 113.
  • the four switches shown in FIG. 1 are not necessarily real physical switches.
  • switching between the transmitting circuit and the receiving circuit may be implemented by multiplexing signals in the transmitting circuit and / or the receiving circuit.
  • FIG. 2 is a schematic block diagram of a data interface 210 according to an embodiment of the present application.
  • the data interface 210 may include:
  • a first sending circuit 220 for receiving an input signal and outputting a first current to or receiving a first current from the first receiving circuit according to the input signal;
  • the circuit generates a first voltage signal according to the first current.
  • the first sending circuit 220 is configured to receive an input signal and output a first current to a first receiving circuit of a peer interface connected to the data interface according to the input signal, or from the input signal to the first receiving circuit according to the input signal.
  • the first receiving circuit of the opposite end interface receives a first current to generate a first voltage signal corresponding to the input signal at the opposite end interface.
  • the input signal may be a signal generated by a function module of a chip where the data interface 210 is located, or may be a signal generated by a function module connected to the data interface 210.
  • the first receiving circuit may be a receiving circuit in a peer data interface connected to the data interface 210.
  • the first sending circuit 220 may be the sending circuit 111 shown in FIG. 1, and the first receiving circuit may be shown in FIG. 1.
  • the input signal is used to control the first sending circuit 220 to output the first current to the first receiving circuit, or the input signal is used to control the first sending circuit 220 to receive The first current output by the first receiving circuit.
  • the input signal is used to control the first transmitting circuit 220 to inject the first current into the first receiving circuit, or the input signal is used to control the first transmitting circuit 220 from the first receiving circuit.
  • a receiving circuit draws the first current. That is, the first sending circuit 220 in the embodiment of the present application may inject the first current into the first receiving circuit or extract the first current value from the first receiving circuit. Manner, controlling the current value of the first receiving circuit, so that the first receiving circuit generates the first voltage signal.
  • the data interface 210 may further include:
  • the first transmitting circuit 220 is connected to one end of the electrostatic protection circuit 230, and the other end of the electrostatic protection circuit 230 is used to connect to the first receiving circuit.
  • the data interface 210 is used for half-duplex communication.
  • the data interface 210 may be the data interface 110 shown in FIG. 1
  • the first sending circuit 220 may be the sending circuit 111 shown in FIG. 1
  • the electrostatic protection circuit 230 may be shown in FIG. 1.
  • the electrostatic protection circuit 113, the first receiving circuit may be the receiving circuit 131 shown in FIG. 1
  • the binding line 240 may be the binding line 120 shown in FIG.
  • the data interface 210 may also be the data interface 130 shown in FIG. 1.
  • the first sending circuit may be the sending circuit 135 shown in FIG. 1
  • the electrostatic protection circuit 230 may be As shown in the electrostatic protection circuit 133 shown in FIG. 1
  • the first receiving circuit may be the receiving circuit 113 shown in FIG. 1.
  • the embodiments of the present application are not limited to this.
  • the data interface 310 may also be used for simplex communication.
  • the data interface 210 uses the first current as a carrier for transmitting a signal, and outputs or receives the first receiving circuit to the first receiving circuit through the binding line 240 in a single-ended output manner.
  • a current can not only achieve data transmission, but also effectively reduce the cost of the data interface.
  • the data interface 210 shown in FIG. 1 only includes an example of the first sending circuit 220 and the electrostatic protection circuit 230.
  • the embodiments of the present application are not limited to this.
  • the data interface 210 may further include a signal receiving conversion circuit for receiving a digital signal of a processor connected to the data interface 210 and converting the data A digital signal is converted into the input signal.
  • a signal receiving conversion circuit for receiving a digital signal of a processor connected to the data interface 210 and converting the data A digital signal is converted into the input signal.
  • the data interface 210 may not include the electrostatic protection circuit 230.
  • the first sending circuit 220 according to the embodiment of the present application will be described below with reference to FIGS. 3 and 4.
  • FIG. 3 is an example of a circuit design of the first transmission circuit 220 shown in FIG. 2.
  • the first sending circuit 220 may include:
  • the current control circuit 212 is controlled by the input signal to control the source of the first MOS transistor 208 to output or receive the first current.
  • the current control circuit 212 is configured to receive the input signal Vin, and control the source of the first MOS tube 208 to output or receive the first current according to the input signal Vin.
  • the first sending circuit 220 may further include:
  • the first bias circuit 211 is connected to the first MOS transistor 208 through the current control circuit 212, and the first bias circuit 211 is configured to provide a bias current for the current control circuit 212.
  • the current control circuit 212 when the input signal is at a high level, the current control circuit 212 is configured to control a source of the first MOS transistor 208 to output the first current Iout, so When the input signal is at a low level, the current control circuit 212 is configured to control a source of the first MOS transistor 208 to receive the first current Iout output from a peer data interface connected to the data interface 210.
  • the current control circuit 212 may include:
  • First switch 205 and second switch 207 are identical to First switch 205 and second switch 207.
  • one end of the first switch 205 is used to receive a power voltage, and the other end of the first switch 205 is connected to one end of the second switch 207 through the first MOS tube 208.
  • the second switch The other end of 207 is connected to ground.
  • the input signal is used to control the on or off of the first switch 205 and the second switch 207, and the source of the first MOS tube 208 is the output terminal of the current control circuit 212.
  • the control signal controls the first switch 205 to be turned on and the second switch 207 to be turned off
  • the source of the first MOS tube 208 goes to the first receiving The circuit outputs the first current.
  • the control signal controls the first switch 205 to be turned off and the second switch 207 to be turned on
  • the source of the first MOS tube 208 receives the first current from the first receiving circuit.
  • the gate of the first MOS transistor 208 may be connected to the first bias circuit 211, and the first bias circuit is configured to provide a bias current for the first MOS transistor 208.
  • the source direction of the first MOS tube 208 can be controlled.
  • the peer data interface connected to the data interface 210 outputs the first current, or controls the source of the first MOS transistor 208 to receive the first current output from the peer data interface connected to the data interface 210.
  • the first switch 205 and the second switch 207 are used to control the source output of the first MOS tube 208 or receive the first current, thereby avoiding the data interface 210 and the opposite end.
  • the data interface adopts a loop circuit design for data transmission, so that the output end of the data interface 210 is single-ended, which can effectively reduce the cost of the data interface.
  • the source of the first MOS tube 208 is used as the output terminal of the first sending circuit 220, which can be used during the establishment of a transmission signal. Providing a larger slew rate for the transmission signal will be described in detail.
  • the current control circuit 212 may further include:
  • the second MOS transistor 202 The second MOS transistor 202, the third MOS transistor 203, and the first resistor 206.
  • the source of the second MOS tube 202 is used to receive a power supply voltage, and the drain of the second MOS tube 202 is connected to one end of the first resistor 206 through the third MOS tube 203.
  • the other end of the first resistor 206 is connected to the ground, and the gate of the third MOS transistor 203 is connected to the gate of the first MOS transistor 208.
  • the voltage of the source of the first MOS tube 208 increases from 0.
  • the first The ratio between the current of the source of the MOS tube 208 and the current of the source of the third MOS tube 203 is:
  • I OUT represents the current of the source of the first MOS tube 208
  • I 3 represents the current of the source of the third MOS tube 203
  • (W / L) 4 represents the first A width-to-length ratio of a MOS tube 208
  • the (W / L) 3 represents the width-to-length ratio of the third MOS tube 203
  • V GS4 represents between the gate and the source of the first MOS tube 208
  • the V GS3 represents the voltage between the gate and the source of the third MOS transistor 203
  • the V TH represents the threshold voltage
  • the threshold voltage is also referred to as the turn-on voltage.
  • the V TH may represent a threshold voltage of the first MOS transistor 208, and specifically, may be a gate voltage required for starting a conductive channel between a source and a drain of the first MOS transistor 208. .
  • the first current is generated by a current mirror composed of the first MOS tube 208 and the third MOS tube 203.
  • the source voltage of the first MOS transistor 208 provides a larger slew rate, thereby increasing the establishment speed and transmission rate of the transmission signal.
  • the source of the first MOS tube 208 is used as the output terminal of the first transmitting circuit 220, which can be used during the establishment of the transmission signal (that is, the first current).
  • the transmission signal provides a large slew rate, which can further increase the establishment speed of the transmission signal, thereby achieving high-speed transmission of data between data interfaces.
  • the first bias circuit 211 may include:
  • the fourth MOS transistor 201 and the first current source 204 are connected to The fourth MOS transistor 201 and the first current source 204.
  • the source of the fourth MOS transistor 201 is used to receive a power supply voltage, and the gate of the fourth MOS transistor 201 is connected to the drain of the fourth MOS transistor 201.
  • the drain is connected to the ground through the first current source 204, and the gate of the fourth MOS transistor 201 is connected to the gate of the second MOS transistor 202.
  • a current mirror composed of the fourth MOS tube 201 and the second MOS tube 202 is used to provide a bias current for the current control circuit 212.
  • first bias circuit 211 shown in FIG. 3 is merely an example, and the first bias circuit 211 in the embodiment of the present invention is intended to provide a bias current to the current control circuit 212.
  • the embodiment of the present invention does not limit the specific circuit structure and use process of the first bias circuit 211.
  • the circuit structure shown in FIG. 3 is only an example of the first sending circuit 220 in the embodiment of the present application, and the embodiment of the present application is not limited thereto.
  • the power supply circuit of the first current may also be a constant current source.
  • a functional module in the chip such as a processor, sends data or a command (signal to be transmitted) to another chip (ie, the opposite chip) connected to it, it can send an input signal Vin corresponding to the signal to be transmitted to Interface circuit, a pair of switches 205 and 207 in the interface circuit are controlled by Vin to form a combined state, so that the source of the MOS tube 208 generates the effect of sinking current Iout or extracting current Iout to the data interface of the opposite chip, so that The opposite end “receives” different signals, that is, it implements “sending” different signals to the opposite end, and realizes the transmission of input signals.
  • FIG. 4 is an example of another circuit configuration of the first transmission circuit 220 shown in FIG. 2.
  • the first sending circuit 220 may include:
  • the switch 221, the current source 222, the current source 223, and the switch 224 are connected to the switch 221, the current source 222, the current source 223, and the switch 224.
  • one end of the switch 221 is connected to a power supply voltage
  • the other end of the switch 221 is connected to one end of a current source 223 through a current source 222
  • the other end of the current source 223 is connected to ground through the switch 224.
  • the input signal Vin is used to control the on or off of the switch 221 and the switch 224, and a port connected between the current source 222 and the current source 223 is used as the first transmitting circuit 220.
  • An output terminal, the output terminal is configured to receive or output the first current.
  • the output terminal when the input signal Vin controls the switch 221 to be turned on and the switch 224 to be turned off, the output terminal outputs the first current to the first receiving circuit, and the The magnitude is equal to the current output by the current source 222.
  • the input signal Vin controls the switch 221 to be off and the switch 224 to be on, the output terminal receives the first current from the first receiving circuit, and the magnitude of the first current is equal to the The current output by the current source 223.
  • the data interface 210 including the first sending circuit 220 according to the embodiment of the present application is described in conjunction with FIG. 2 to FIG. 4 above, and the data interface having the function of receiving data according to the embodiment of the present application is exemplified below with reference to FIGS. 5 to 7. Sexual description.
  • FIG. 5 is a schematic block diagram of another data interface 310 according to an embodiment of the present application.
  • the data interface 310 may include:
  • a second receiving circuit 330 configured to receive a second current from a second transmitting circuit of a peer interface connected to the data interface 310, or send the second current to the second interface of the peer interface
  • the circuit outputs a second current, and a second voltage signal can be generated according to the second current.
  • the second sending circuit may be a sending circuit in a peer data interface connected to the data interface 310.
  • the second receiving circuit 330 may be the receiving circuit 115 shown in FIG. 1
  • the second sending circuit may be the one shown in FIG. 1.
  • a peer data interface connected to the data interface 310 is configured to inject the second current into the second receiving circuit 330 or to extract the second current from the data interface 310. , Transmitting a signal to the data interface 310.
  • the second receiving circuit 330 may generate the second voltage signal according to the magnitude of the current value of the second current that is sinked or extracted.
  • the data interface 310 may further include:
  • An electrostatic protection circuit 320 An electrostatic protection circuit 320.
  • the second receiving circuit 330 is connected to one end of a binding line 340 through the electrostatic protection circuit 320, and the other end of the binding line 340 is used to connect to the second transmitting circuit.
  • the data interface 310 is used for half-duplex communication.
  • the data interface 310 may be the data interface 110 shown in FIG. 1
  • the second receiving circuit 330 may be the receiving circuit 115 shown in FIG. 1
  • the electrostatic protection circuit 320 may be shown in FIG. 1.
  • the binding line 340 may be the binding line 120 shown in FIG. 1
  • the second sending circuit may be the sending circuit 135 shown in FIG. 1.
  • the data interface 310 may also be the data interface 130 shown in FIG. 1, and accordingly, the second receiving circuit may be the receiving circuit 131 shown in FIG. 1, and the second sending circuit may be As shown in the transmitting circuit 111 shown in FIG. 1, the electrostatic protection circuit may be an electrostatic protection circuit 133 shown in FIG. 1.
  • the data interface 310 may be used for simplex communication.
  • FIG. 5 is an example in which the data interface 310 includes only the second receiving circuit 330 and the electrostatic protection circuit 320.
  • the embodiments of the present application are not limited to this.
  • the data interface 310 when used for half-duplex communication, it may further include a switch for implementing half-duplex communication.
  • the data interface 310 may not include the electrostatic protection circuit 320.
  • the second receiving circuit 330 may be implemented by a common-gate amplifier circuit.
  • FIG. 6 is an example in which a common-gate amplifier circuit is used as the second receiving circuit 330 according to an embodiment of the present application.
  • the second receiving circuit 330 may include:
  • the MOS tube 301, the resistor 302, the parasitic capacitor 303, the parasitic capacitor 304, and the load resistor 305 are connected to the MOS tube 301, the resistor 302, the parasitic capacitor 303, the parasitic capacitor 304, and the load resistor 305.
  • the resistor 302 may be an input resistor, which is used as an equivalent resistance of the input circuit.
  • the source of the MOS transistor 301 is connected to the transmitting circuit of the opposite data interface through the resistor 302, for example, the second receiving circuit 330 is located.
  • the transmitting circuit in the opposite data interface connected to the data interface, and the source of the MOS tube 301 is connected to the ground through a parasitic capacitor 303, the drain of the MOS tube 301 is connected to the ground through a parasitic capacitor 304, and the MOS
  • the drain of the tube 301 is connected to the power supply voltage through the load resistor 305, and the drain of the MOS tube 301 is used as an output terminal of the second receiving circuit 330 to output the second voltage signal.
  • the source of the MOS tube 301 is used to receive or output the second current, and the amount of information carried by the second current can form the transmission level VIN through the resistor 302. Further, the drain of the MOS transistor 301 converts the transmission level VIN into the second voltage signal and outputs the second voltage signal.
  • the input and output of the second receiving circuit 330 can be considered to be isolated from each other, that is, the second receiving circuit 330 has no parasitic capacitance across the input and output. Therefore, the Miller effect of the parasitic capacitance can be avoided, and the bandwidth of the second receiving circuit 330 can be increased.
  • using a common-gate amplifier circuit as the second receiving circuit 330 can reduce the setup time of the output signal (ie, the second voltage signal) of the second receiving circuit 330, thereby further improving A transmission rate of the data interface 310.
  • the second receiving circuit 330 shown in FIG. 6 is merely an example, but the embodiment of the present application is not limited thereto.
  • the resistor 302 is the internal resistance of the signal source
  • the resistor 305 is the internal resistance of the current source (assuming that the resistor 305 is connected to the current source to receive the power supply voltage).
  • the resistor 302 and the resistor 305 may be equivalent to other equivalent devices or equivalent elements.
  • FIG. 7 is an example of a specific circuit design of the second receiving circuit 330 shown in FIG. 6.
  • FIG. 6 can be regarded as a small signal model diagram corresponding to the circuit of FIG. 7.
  • the second receiving circuit 330 may include:
  • the voltage comparison circuit 350 and the second bias circuit 360 are The voltage comparison circuit 350 and the second bias circuit 360.
  • the second bias circuit 360 is configured to provide a bias current to the voltage comparison circuit 350.
  • the voltage comparison circuit 350 is configured to receive a second current from the second transmitting circuit or output a second current to the second transmitting circuit, and generate a second voltage signal according to the second current.
  • the second current carries an amount of information to be received by the second receiving circuit 330
  • the second receiving circuit 330 is configured to convert the amount of information carried by the second current into the first Two voltage signals, and sending the second voltage signal to a processor connected to the data interface 310.
  • the voltage comparison circuit 350 may include:
  • the fifth MOS transistor 321, the sixth MOS transistor 325, the seventh MOS transistor 322, the eighth MOS transistor 324, and the second resistor 326 are the fifth MOS transistor 321, the sixth MOS transistor 325, the seventh MOS transistor 322, the eighth MOS transistor 324, and the second resistor 326.
  • a source of the fifth MOS transistor 321 is used to receive a power supply voltage, and a drain of the fifth MOS transistor 321 is connected to a drain of the sixth MOS transistor 325, and the sixth MOS transistor 325
  • the source of is used to receive or output the second current
  • the source of the seventh MOS transistor 322 is used to receive the power supply voltage
  • the source of the eighth MOS transistor 324 is connected to the ground through the second resistor 326
  • the gate of the fifth MOS transistor 321 is connected to the gate of the seventh MOS transistor 322.
  • the gate of the six MOS tube 325 is connected to the gate of the eighth MOS tube 324, and the drain of the eighth MOS tube 324 is connected to the gate of the eighth MOS tube 324.
  • the voltage comparison circuit 350 may further include:
  • the source of the sixth MOS transistor 325 is connected to the ground through the third resistor 327.
  • the third resistor 327 may be an external resistor.
  • the third resistor 327 is configured to convert the signal amount (ie, the voltage at the B terminal) carried by the second current into a transmission level VIN, so that the voltage comparison circuit 350 can transmit the signal according to the transmission level.
  • VIN outputs the second voltage signal.
  • the second voltage signal may be a logical digital signal.
  • the fifth MOS transistor 321, the sixth MOS transistor 325, the seventh MOS transistor 322, the eighth MOS transistor 324, and the second resistor 326 may constitute the voltage comparison.
  • An access terminal (C terminal shown in the figure) of the amplifier circuit is the source of the eighth MOS transistor 324, and the level of the C terminal is the source current of the eighth MOS transistor 324 and the source current of the eighth MOS transistor 324.
  • the product of the second resistor 326 is a fixed level.
  • the other access terminal of the amplifying circuit (terminal B shown in the figure) is configured to receive the second current, and the level of terminal B is a signal amount carried by the second current passing through the third circuit 327 The level formed by the transition.
  • the D terminal of the second receiving circuit 330 It outputs a high level, and when VIN ⁇ V r , the D terminal of the second receiving circuit 330 outputs a low level.
  • the determination criterion of the signal amount carried by the second current is the flip threshold level V r of the voltage comparison circuit 350.
  • C represents the total parasitic capacitance of the data interface
  • V represents the amplitude of the transmission level (ie, VIN)
  • f represents the transmission rate
  • the transmission level VIN does not need to be flipped with a full swing. That is, when the voltage comparison circuit 350 adopts the circuit design shown in FIG. 7, the amplitude V of the transmission level VIN can be effectively reduced, thereby reducing the power consumption of the data interface 310.
  • a general input output GPIO
  • the transmission level of the GPIO is the power supply voltage. It is assumed that the transmission level of the data interface in the embodiment of the present application is set to one tenth of the power supply voltage. , Under the same conditions, the transmission loss of the data interface 310 in the embodiment of the present application is only one-tenth of the transmission loss of the GPIO.
  • the flip threshold level V r can be adjusted by changing the ratio of the ninth MOS transistor 311 and the seventh MOS transistor 322, or by setting the second resistor 326 Adjust the resistance value.
  • the second bias circuit 360 may include:
  • the source of the ninth MOS transistor 311 is used to receive a power supply voltage.
  • the gate of the ninth MOS transistor 311 is connected to the gate of the fifth MOS transistor 321.
  • the drain is connected to the ground through the second current source 312.
  • the circuit structure of the second bias circuit 360 shown in FIG. 7 is merely an example, and the second bias circuit 360 in the embodiment of the present invention is intended to provide a bias current for the voltage comparison circuit 350.
  • the embodiment of the present invention does not limit the specific circuit structure and use process of the second bias circuit 360.
  • the voltage comparison circuit 350 may further include:
  • the first inverter 331 and the second inverter 332 are identical to each other.
  • the drain of the sixth MOS transistor 325 is connected to the second inverter 332 through the first inverter 331.
  • the first inverter 331 and the second inverter 332 are used to shape the level of the D terminal, so that the second voltage signal output by the voltage comparison circuit 350 is processed.
  • the voltage comparison circuit 350 further includes:
  • one end of the sixth switch 323 is used to receive a power supply voltage, and the other end of the sixth switch 323 is connected to the gate of the fifth MOS transistor 321.
  • the ninth MOS transistor 311, the fifth MOS transistor 321, and the seventh MOS transistor 322 are in an off state. Therefore, when the data interface 310 in the embodiment of the present application does not need to receive data, the receiving function of the data interface 310 can be turned off by turning on the sixth switch 323, which can effectively reduce power consumption, and further The cost of the data interface 310 is reduced.
  • the channel is susceptible to interference, if the signal amount (that is, the transmission level VIN) carried by the second current bounces near the inversion threshold level V r of the voltage comparison circuit 350, the voltage comparison The output of the circuit 350 is prone to errors.
  • the flip threshold level V r may include a hysteresis amount, that is, a noise margin, to enhance the anti-interference capability of the voltage comparison circuit 350.
  • FIG. 8 is an example of a voltage comparison circuit 350 with a hysteresis function according to an embodiment of the present application.
  • the voltage comparison circuit 350 may further include:
  • the source of the eighth MOS transistor 324 is connected to one end of the third resistor 326, and the other end of the third resistor 326 is connected to the ground through the fourth resistor 328, and the fourth resistor 328 One end is connected to the other end of the fourth resistor 328 through the fifth switch 329, and the signal output by the first inverter 311 is used to control the on or off of the fifth switch 329.
  • the transmission level VIN rises from 0, as shown in FIG. 8, the voltage at point A is high, and the fifth switch 329 is in an off state, so
  • the inversion threshold level of the voltage comparison circuit 350 is:
  • V r + I ⁇ (R 1 + R 2 ) (4)
  • I represents the current on the third resistor 326 and the fourth resistor 328
  • the R 2 represents the resistance of the third circuit 326
  • the R 1 represents the resistance of the fourth resistor 328 .
  • the transmission level VIN continues to rise and exceeds the inversion threshold level V r + , the voltage at point A changes from a high level to a low level, the fifth switch 329 is in an on state, and the fourth resistor 328 Is short-circuited, in this case, the rollover threshold level of the voltage comparison circuit 350 is:
  • V r- I ⁇ R 2 (5)
  • An embodiment of the present invention further provides a chip or a chip system, where the chip may be configured with at least one of the above-mentioned data interfaces, or the first chip and the second chip in the chip system adopt the above-mentioned method. At least one data interface connection.
  • FIG. 9 is an example of a circuit design of a chip system 400 according to an embodiment of the present application.
  • the chip system 400 may include:
  • a chip 410 and a chip 420 may include a first sending circuit 220 shown in FIG. 3, and the chip 420 may include a second receiving circuit 330 shown in FIG. 7.
  • the chip 410 and the chip 420 communicate with each other through the first transmitting circuit 220 and the second receiving circuit 330.
  • the switches 205 and 207 are controlled by an input signal.
  • the first transmitting circuit 220 in the chip 410 outputs a current to the second receiving circuit 330 in the chip 420 That is, the current flows from point A to point B, and the voltage at point B rises rapidly.
  • the voltage at point B exceeds the voltage at point C
  • the voltage at point D rises and reaches the threshold voltage of the inverter 331, and finally the inverter 332 outputs a high level. So far, the second receiving circuit 330 has successfully received the high-level signal sent by the first transmitting circuit 220.
  • the first transmitting circuit 220 in the chip 410 receives the current output by the second receiving circuit 330 in the chip 420, that is, the current is from B
  • the voltage at point B decreases rapidly.
  • the voltage at point D decreases and reaches the threshold level of the inverter 311, and finally the inverter 332 outputs a high level. So far, the second receiving circuit 330 has successfully received the low-level signal sent by the first transmitting circuit 220.
  • the chip 410, chip 420, and chip system 400 provided in the embodiments of the present application use current as a carrier for transmitting signals, and perform data transmission through single-ended output, avoiding data transmission by using a circuit design of a loop. , Can effectively reduce the cost of the data interface.
  • the source end of the MOS tube 208 is used as the output end of the first sending circuit 220 of the data interface, which can provide a larger swing for the transmission signal during the transmission signal establishment process Rate, which can further increase the establishment speed of the transmission signal, thereby achieving high-speed transmission of data.
  • the chip 420 is used as a receiving end, on the one hand, by adjusting the flip threshold level of the voltage comparison circuit in the data interface, the transmission level of the signal amount can be effectively reduced, thereby reducing the power consumption of the data interface.
  • the use of a common-gate amplifier circuit in the voltage comparison circuit can effectively increase the establishment speed of the voltage signal, thereby achieving high-speed transmission of data. It should be understood that, in order to avoid repetition, specific structures of the first sending circuit 220 and the second receiving circuit 330 are not described herein again.
  • MOS transistors can be divided into “N-type” MOS transistors (NMOSFET) and “P-type” MOS transistors (PMOSFET) according to the polarity of the "channel" (working carrier).
  • NMOSFET N-type MOS transistors
  • PMOSFET P-type MOS transistors
  • NMOSFET NMOSFET
  • its source and drain The electrode is connected to the N-type semiconductor, the high voltage is connected to the drain terminal, and the low voltage is connected to the source terminal.
  • the actual current direction is flowing into the drain.
  • PMOSFET its source and drain are connected to a P-type semiconductor, high voltage is used as the source terminal, and low voltage is used as the drain terminal.
  • the actual current direction is the outflow drain. Taking the second bias circuit 360 shown in FIG.
  • the second bias circuit 360 includes a ninth MOS tube 311, and the MOS tube 311 is a "P-type" MOS tube.
  • the embodiment of the present invention is not limited thereto.
  • the MOS transistor 311 may be designed as an “N-type” MOS transistor, and some devices in the voltage comparison circuit 350 are adaptively improved, so that the second bias circuit 360 can provide a bias current for the voltage comparison circuit 350.

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Abstract

提供了一种数据接口、芯片和芯片系统，能够降低成本。所述数据接口，所述数据接口应用于发送端或者半双工通信，所述数据接口包括：第一发送电路；所述第一发送电路用于接收输入信号，并根据所述输入信号向与所述数据接口相连的对端接口的第一接收电路输出第一电流，或者根据所述输入信号从所述对端接口的所述第一接收电路接收第一电流，以在对端接口产生与所述输入信号对应的第一电压信号。本申请实施例提供的数据接口、芯片和芯片系统，采用电流作为传输信号的载体，并通过单端输出的方式进行数据传输，能够有效降低数据接口的成本。

Description

数据接口、芯片和芯片系统 技术领域
本申请实施例涉及电子技术领域，并且更具体地，涉及数据接口、芯片和芯片系统。
背景技术
在多芯片，比如多个微控制单元(Microcontroller Unit，MCU)的封装中，多个芯片之间不可避免的需要数据通信。
多个芯片之间进行数据通信时，可以将电流、电压或者电荷作为传输信号的载体。以电流作为传输信号的载体为例，芯片之间通常采用回路电路的方式进行数据传输。
但是，采用回路传输的方式进行数据传输通常需要两组引脚，增加了互联成本和制造成本。
因此，如何降低数据接口的成本是本领域中一项急需解决的问题。
发明内容
提供了一种数据接口、芯片和芯片系统，能够降低成本。
第一方面，提供了一种数据接口，所述数据接口应用于发送端或者半双工通信，所述数据接口包括：
第一发送电路；
所述第一发送电路用于接收输入信号，并根据所述输入信号向与所述数据接口相连的对端接口的第一接收电路输出第一电流，或者根据所述输入信号从所述对端接口的所述第一接收电路接收第一电流，以在对端接口产生与所述输入信号对应的第一电压信号。
在一些可能的实现方式中，所述第一发送电路包括：
第一MOS管和电流控制电路；
所述电流控制电路受控于所述输入信号，以控制所述第一MOS管的源极输出或接收所述第一电流。
在一些可能的实现方式中，所述第一发送电路进一步包括：
第一偏置电路，所述第一偏置电路通过所述电流控制电路连接至所述第 一MOS管，所述第一偏置电路用于为所述电流控制电路提供偏置电流。
在一些可能的实现方式中，所述电流控制电路包括：
第一开关和第二开关；
所述第一开关的一端用于接收电源电压，所述第一开关的另一端通过所述第一MOS管连接至所述第二开关的一端，所述第二开关的另一端连接至地。
在一些可能的实现方式中，所述电流控制电路还包括：
第二MOS管、第三MOS管和第一电阻；
所述第二MOS管的源极用于接收所述电源电压，所述第二MOS管的漏极通过所述第三MOS管连接至所述第一电阻的一端，所述第一电阻的另一端连接至地，所述第三MOS管的栅极与所述第一MOS管的栅极相连。
在一些可能的实现方式中，所述第一偏置电路包括：
第四MOS管和第一电流源；
所述第四MOS管的源极用于接收电源电压，所述第四MOS管的栅极与所述第四MOS管的漏极相连，所述第四MOS管的漏极通过所述第一电流源连接至地，所述第四MOS管的栅极与所述第二MOS管的栅极相连。
在一些可能的实现方式中，所述数据接口还包括：
静电保护电路，所述第一发送电路通过所述静电保护电路连接至绑定线的一端，所述绑定线的另一端用于连接所述第一接收电路。
在一些可能的实现方式中，所述数据接口应用于半双工通信，所述数据接口还包括：
第二接收电路；
所述第二接收电路通过所述静电保护电路连接至所述绑定线的一端，所述绑定线的另一端用于连接所述对端接口的第二发送电路；
所述第二接收电路用于通过所述绑定线和所述静电保护电路从所述第二发送电路接收第二电流或向所述第二发送电路输出第二电流，并根据所述第二电流生成第二电压信号。
在一些可能的实现方式中，所述数据接口还包括：
第三开关和第四开关；
所述第一发送电路通过所述第三开关连接至所述静电保护电路，所述第二接收电路通过所述第四开关连接至所述静电保护电路。
在一些可能的实现方式中，所述第二接收电路包括：
电压比较电路和第二偏置电路；
所述第二偏置电路用于为所述电压比较电路提供偏置电流，所述电压比较电路用于接收或输出所述第二电流，并根据所述第二电流生成所述第二电压信号。
在一些可能的实现方式中，所述电压比较电路包括：
第五MOS管、第六MOS管、第七MOS管、第八MOS管和第二电阻；
所述第五MOS管的源极用于接收电源电压，所述第五MOS管的漏极与所述第六MOS管的漏极连接，所述第六MOS管的源极用于接收或者输出所述第二电流，所述第七MOS管的源极用于接收电源电压，所述第七MOS管的漏极与所述第八MOS管的漏极相连，所述第八MOS管的源极通过所述第二电阻连接至地，所述第五MOS管的栅极与所述第七MOS管的栅极连接，所述第六MOS管的栅极连接至所述第八MOS管的栅极，所述第八MOS管的漏极与所述第八MOS管的栅极相连。
在一些可能的实现方式中，所述电压比较电路还包括：
第一反相器和第二反相器；
所述第六MOS管的漏极通过所述第一反相器连接至所述第二反相器。
在一些可能的实现方式中，所述电压比较电路还包括：
第三电阻；
所述第六MOS管的源极通过所述第三电阻连接至地。
在一些可能的实现方式中，所述电压比较电路还包括：
第四电阻和第五开关；
所述第八MOS管的源极与所述第三电阻的一端相连，所述第三电阻的另一端通过所述第四电阻连接至地，所述第四电阻的一端通过所述第五开关连接至所述第四电阻的另一端，所述第一反相器输出的信号用于控制所述第五开关的导通或者断开。
在一些可能的实现方式中，所述电压比较电路还包括：
第六开关；
所述第六开关的一端用于接收电源电压，所述第六开关的另一端与所述第五MOS管的栅极相连。
在一些可能的实现方式中，所述第二偏置电路包括：
第九MOS管和第二电流源；
所述第九MOS管的源极用于接收电源电压，所述第九MOS管的栅极与所述第五MOS管的栅极相连，所述第九MOS管的漏极通过所述第二电流源连接至地。
第二方面，提供了一种数据接口，所述数据接口应用于接收端，所述数据接口包括：
第二接收电路；
所述第二接收电路用于从与所述数据接口相连的对端接口的第二发送电路接收第二电流，或者向所述对端接口的所述第二发送电路输出第二电流，并根据所述第二电流生成第二电压信号。
在一些可能的实现方式中，所述数据接口还包括：
静电保护电路；
所述第二接收电路通过所述静电保护电路连接至绑定线的一端，所述绑定线的另一端用于连接所述第二发送电路。
在一些可能的实现方式中，所述第二接收电路包括：
电压比较电路和第二偏置电路；
所述第二偏置电路用于为所述电压比较电路提供偏置电流，所述电压比较电路用于接收或输出所述第二电流，并根据所述第二电流生成所述第二电压信号。
在一些可能的实现方式中，所述电压比较电路包括：
第五MOS管、第六MOS管、第七MOS管、第八MOS管和第二电阻；
所述第五MOS管的源极用于接收电源电压，所述第五MOS管的漏极与所述第六MOS管的漏极连接，所述第六MOS管的源极用于接收或者输出所述第二电流，所述第七MOS管的源极用于接收电源电压，所述第七MOS管的漏极与所述第八MOS管的漏极相连，所述第八MOS管的源极通过所述第二电阻连接至地，所述第五MOS管的栅极与所述第七MOS管的栅极连接，所述第六MOS管的栅极连接至所述第八MOS管的栅极，所述第八MOS管的漏极与所述第八MOS管的栅极相连。
在一些可能的实现方式中，所述电压比较电路还包括：
第一反相器和第二反相器；
所述第六MOS管的漏极通过所述第一反相器连接至所述第二反相器。
在一些可能的实现方式中，所述电压比较电路还包括：
第三电阻；
所述第六MOS管的源极第三电阻通过所述第三电阻连接至地。
在一些可能的实现方式中，所述电压比较电路还包括：
第四电阻和第五开关；
所述第八MOS管的源极与所述第二电阻的一端相连，所述第二电阻的另一端通过所述第四电阻连接至地，所述第二电阻的一端通过所述第五开关连接至所述第二电阻的另一端，所述第一反相器输出的信号用于控制所述第五开关的导通或者断开。
在一些可能的实现方式中，所述电压比较电路还包括：
第六开关；
所述第六开关的一端用于接收电源电压，所述第六开关的另一端与所述第五MOS管的栅极相连。
在一些可能的实现方式中，所述第二偏置电路包括：
第九MOS管和第二电流源；
所述第九MOS管的源极用于接收电源电压，所述第九MOS管的栅极与所述第五MOS管的栅极相连，所述第九MOS管的漏极通过所述第二电流源连接至地。
第三方面，提供了一种芯片，包括：
第一方面及第一方面中任一可能实现方式中的所述的数据接口，和/或，第二方面及第二方面中任一可能实现方式中所述的数据接口。
第四方面，提供了一种芯片系统，包括：
多个芯片，所述多个芯片中的芯片和第二芯片之间采用以下至少一种数据接口连接：
第一方面及第一方面中任一可能实现方式中的所述的数据接口，和/或，第二方面及第二方面中任一可能实现方式中所述的数据接口。
本申请实施例提供的数据接口、芯片和芯片系统，采用电流作为传输信号的载体，并通过单端输出的方式进行数据传输，避免了采用回路的电路设计进行数据传输，能够有效降低数据接口的成本。
所述数据接口作为发射端时，将MOS管的源端作为所述数据接口的第一发送电路的输出端，能够在传输信号建立过程中为所述传输信号提供较大 的摆率，进而能够提高传输信号的建立速度，进而实现数据的高速传输。
所述数据接口作为接收端时，一方面，通过调整所述数据接口中电压比较电路的翻转阈值电平，能够有效降低信号量的传输电平，进而降低所述数据接口的功耗。另一方面，所述电压比较电路中采用共栅放大电路能够有效提高所述电压信号的建立速度，进而实现数据的高速传输。
附图说明
图1是本发明实施例的芯片系统的示意图。
图2是本申请实施例的数据接口作为发射端的示意性框图。
图3是图2所示的第一发送电路的电路图的示例。
图4是图2所示的第一发送电路的电路图的另一示例。
图5是本申请实施例的数据接口作为接收端的示意性框图。
图6是图5所示的第二接收电路的电路图的示例。
图7是图5所示的第二接收电路的电路图的另一示例。
图8是图5所示的第二接收电路的电路图的另一示例。
图9是本申请实施例的芯片系统的电路图的示例。
具体实施方式
下面将结合附图，对本发明实施例中的技术方案进行描述。应理解，本发明实施例的数据接口、芯片和芯片系统适用于任何需要数据通信的场合，尤其适用于高速低功耗通信互联的场合。其中，数据接口尤其适用于芯片之间的数据通信。例如，芯片系统的内部芯片之间的数据通信。
本发明实施例中，考虑到多芯片间通信信道不对外可见，且基于电路回路进行数据传输时，每个芯片均需要设置多个引脚，成本过高。
为了解决上述问题，本发明实施例中提供了一种新的数据接口，所述数据接口采用电流作为传输信号的载体，并通过单端输出的方式进行数据传输，能够有效降低数据接口的成本。
图1是本发明实施例的芯片系统100的示意性框图。
如图1所示，所述芯片系统100可以包括：
数据接口110、绑定线120和数据接口130。其中，为便于理解，数据接口110可视为本端数据接口，数据接口130可视为对端数据接口，本端与 对端是相互通信的两端，在多芯片系统中可视为两个相互连通的芯片。
所述数据接口110可以包括：
发送电路111、开关112、静电保护电路113、开关114和接收电路115。其中，所述发送电路111通过所述开关112连接至所述静电保护电路113的一端，所述静电保护电路113的另一端通过所述绑定线120连接至所述数据接口130，所述静电保护电路113还通过所述开关114连接至所述接收电路115。
相应的，所述数据接口130可以包括：
接收电路131、开关132、静电保护电路133、开关134以及发送电路135。其中，所述发送电路135通过所述开关134连接至所述静电保护电路133的一端，所述静电保护电路133的另一端通过所述绑定线120连接至所述数据接口110，所述静电保护电路133还通过所述开关132连接至所述接收电路131。
换句话说，所述数据接口110和所述数据接口130都可以包括一套功能相同的接收电路和发送电路，使得所述数据接口110和所述数据接口130能够实现半双工通信功能。
具体地，所述数据接口110可以通过所述开关112和所述开关114实现所述发送电路111和所述接收电路115之间的工作切换，所述数据接口130可以通过所述开关132和所述开关134实现所述接收电路131和所述发送电路135之间的工作切换。
可选地，在本申请的一个实施例中，当控制信号en1＝0且en2＝1时，开关112、132闭合，开关114、134断开，发送电路111与接收电路131形成发射-接收通路，所述数据接口110可以作为发射端，所述数据接口130作为接收端。当控制信号en1＝1且en2＝0时，所述数据接口110可以作为接收端，所述数据接口130作为发射端。
应当理解，虽然，所述数据接口110和数据接口130都可以包括一套功能相同的接收电路和发送电路，但是，其接收电路和发送电路的具体实现电路和/或使用工艺可以不同。
在图1所示的芯片系统中，所述静电保护电路113和所述静电保护电路133均可以用于防止静电对器件的破坏。本申请实施例对静电保护电路的具体实现方式不做限定。例如，在一些实施例中，所述静电保护电路113或者 所述静电保护电路133可集成设置在焊盘(PAD)上，也可以与PAD分离设置。
可选地，在本申请的一个实施例中，所述静电保护电路113和/或所述静电保护电路133只需要满足充电器件模型(Charged Device Model，CDM)的需求。
本申请实施例中，由于多芯片系统内的多个芯片一般会整合成一个整体，比如进行一个整体封装，假设系统内的芯片A使用数据接口110，而系统内芯片B使用数据接口130，所述数据接口110和数据接口130之间的通信信道并不是暴露在整个芯片系统100的外部，因此，在保证满足CDM的需求的基础上，尽可能的简化所述静电保护电路113和/或所述静电保护电路133的电路结构，能够有效降低寄生电容。
应理解，所述数据接口110或所述数据接口130中的接收电路和发送电路可以如图1所示共用一个静电保护电路，也可以分别对应一个静电保护电路。本申请实施例对此不做具体限定。
在图1所示的芯片系统中，绑定线120为芯片之间用于互连的连接线。
这里需要指出的是，图1所示的芯片系统100仅为示例，但本身实施例不限于此。
例如，在其它可替代实施例中，所述数据接口110或所述数据接口130可以仅用于单工通信。
这种情况下，图1所示的四个开关和部分器件为可选器件。例如，以所述数据接口110为例，所述数据接口110可以仅包括发送电路111和静电保护电路113，或者，所述数据接口110可以仅包括接收电路115和静电保护电路113。
又例如，所述数据接口110和/或所述数据接口130用于半双工通信时，图1所示的四个开关并非一定是真实的物理开关。例如，在其他可替代实施例中，可以是通过复用发送电路和/或接收电路中的信号，实现发送电路和接收电路之间的切换。
图2是本申请实施例的数据接口210的示意性框图。
如图2所示，所述数据接口210可以包括：
第一发送电路220，所述第一发送电路220用于接收输入信号，并根据所述输入信号向第一接收电路输出第一电流或者从所述第一接收电路接收 第一电流，第一接收电路根据所述第一电流生成第一电压信号。
具体地，所述第一发送电路220用于接收输入信号，并根据所述输入信号向与所述数据接口相连的对端接口的第一接收电路输出第一电流，或者根据所述输入信号从所述对端接口的所述第一接收电路接收第一电流，以在对端接口产生与所述输入信号对应的第一电压信号。
其中，所述输入信号可以是所述数据接口210所在芯片的功能模块产生的信号，也可以是与所述数据接口210相连的功能模块产生的信号。
所述第一接收电路可以是与所述数据接口210相连的对端数据接口中的接收电路。例如，图2所示的数据接口210为图1所示的数据接口110时，所述第一发送电路220可以为图1所示的发送电路111，所述第一接收电路可以为图1所述的数据接口130中的接收电路131。
本申请实施例中，所述输入信号用于控制所述第一发送电路220向所述第一接收电路输出所述第一电流，或者所述输入信号用于控制所述第一发送电路220接收所述第一接收电路输出的所述第一电流。换句话说，所述输入信号用于控制所述第一发送电路220向第一接收电路灌入所述第一电流，或者所述输入信号用于控制所述第一发送电路220从所述第一接收电路抽取所述第一电流。也就是说，本申请实施例中的所述第一发送电路220可以通过向所述第一接收电路灌入所述第一电流，或者从所述第一接收电路抽取所述第一电流值的方式，控制所述第一接收电路的电流值，进而使得所述第一接收电路生成所述第一电压信号。
可选地，如图2所示，所述数据接口210还可以包括：
静电保护电路230，所述第一发送电路220与所述静电保护电路230的一端相连，所述静电保护电路230的另一端用于连接所述第一接收电路。
可选地，在本申请的一个实施例中，所述数据接口210用于半双工通信。
例如，所述数据接口210可以是如图1所示的数据接口110，所述第一发送电路220可以是图1所示的发送电路111，所述静电保护电路230可以是图1所示的静电保护电路113，所述第一接收电路可以是图1所示的接收电路131，绑定线240可以是图1所示的绑定线120。
又例如，所述数据接口210也可以是如图1所示的数据接口130，相应的，所述第一发送电路可以为如图1所示的发送电路135，所述静电保护电路230可以是如图1所示的静电保护电路133，所述第一接收电路可以是图 1所示的接收电路113。但本申请实施例不限于此。
可选地，在本申请的一个实施例中，所述数据接口310也可以用于单工通信。
本申请实施例中，所述数据接口210以所述第一电流作为传输信号的载体，并且通过所述绑定线240以单端输出的方式向所述第一接收电路输出或者接收所述第一电流，不仅能够实现数据传输，而且能够有效降低数据接口的成本。
应当理解，图1所示的数据接口210仅包括第一发送电路220和静电保护电路230的示例。但本申请实施例不限于此。
例如，在其它可替代实施例中，所述数据接口210还可以包括信号接收转换电路，所述信号接收转换电路用于接收与所述数据接口210相连的处理器的数字信号，并将所述数字信号转换为所述输入信号。
又例如，在其他可替代实施例中，所述数据接口210也可以不包括所述静电保护电路230。
下面结合图3和图4对本申请实施例的第一发送电路220进行说明。
图3是图2所示的第一发送电路220的电路设计的示例。
如图3所示，所述第一发送电路220可以包括：
第一金属氧化物半导体(Metal-Oxide-Semiconductor，MOS)场效应晶体管(Field-Effect Transistor,FET)208和电流控制电路212。其中，所述电流控制电路212受控于所述输入信号，以控制所述第一MOS管208的源极输出或接收所述第一电流。换句话说，所述电流控制电路212用于接收所述输入信号Vin，并根据所述输入信号Vin控制所述第一MOS管208的源极输出或接收所述第一电流。
可选地，如图3所示，所述第一发送电路220还可以包括：
第一偏置电路211。
具体地，所述第一偏置电路211通过所述电流控制电路212连接至第一MOS管208，所述第一偏置电路211用于为所述电流控制电路212提供偏置电流。
可选地，在本申请的一个实施例中，所述输入信号为高电平时，所述电流控制电路212用于控制所述第一MOS管208的源极输出所述第一电流Iout，所述输入信号为低电平时，所述电流控制电路212用于控制所述第一 MOS管208的源极接收与所述数据接口210相连的对端数据接口输出的所述第一电流Iout。
可选地，如图3所示，所述电流控制电路212可以包括：
第一开关205和第二开关207。
具体地，所述第一开关205的一端用于接收电源电压，所述第一开关205的另一端通过所述第一MOS管208连接至所述第二开关207的一端，所述第二开关207的另一端连接至地。所述输入信号用于控制所述第一开关205和所述第二开关207的导通或断开，所述第一MOS管208的源极为所述电流控制电路212的输出端。换句话说，本申请实施例中，所述控制信号控制所述第一开关205导通且所述第二开关207断开时，所述第一MOS管208的源极向所述第一接收电路输出所述第一电流。所述控制信号控制所述第一开关205断开且所述第二开关207导通时，所述第一MOS管208的源极从所述第一接收电路接收所述第一电流。
例如，所述第一MOS管208的栅极可以和所述第一偏置电路211相连，所述第一偏置电路用于为所述第一MOS管208提供偏置电流。
这种情况下，通过控制所述电流控制电路212中的所述第一开关205和所述第二开关207的导通或者关断，可以控制所述第一MOS管208的源极向与所述数据接口210相连的对端数据接口输出所述第一电流，或者控制所述第一MOS管208的源极接收与所述数据接口210相连的对端数据接口输出的所述第一电流。
本申请实施例中，通过所述第一开关205和所述第二开关207控制所述第一MOS管208的源极输出或接收所述第一电流，避免了所述数据接口210和对端数据接口采用回路的电路设计进行数据传输，使得数据接口210的输出端为单端，能够有效降低数据接口的成本。
下面以图3所示的电流控制电路212为例，对本申请实施例中将所述第一MOS管208的源极作为所述第一发送电路220的输出端，能够在传输信号的建立过程中为所述传输信号提供较大的摆率进行详细说明。
可选地，如图3所示，所述电流控制电路212还可以包括：
第二MOS管202、第三MOS管203和第一电阻206。
具体地，所述第二MOS管202的源极用于接收电源电压，所述第二MOS管202的漏极通过所述第三MOS管203连接至所述第一电阻206的一 端，所述第一电阻206的另一端连接至地，所述第三MOS管203的栅极与所述第一MOS管208的栅极相连。
本申请实施例中，当所述第一开关205导通且所述第二开关207断开时所述第一MOS管208源极的电压从0开始增加，这种情况下，所述第一MOS管208的源极的电流和所述第三MOS管203的源极的电流之间的比值为：
Figure PCTCN2018103841-appb-000001
其中，所述I OUT表示所述第一MOS管208的源极的电流，所述I 3表示所述第三MOS管203的源极的电流，所述(W/L) 4表示所述第一MOS管208的宽长比，所述(W/L) 3表示所述第三MOS管203的宽长比，所述V GS4表示所述第一MOS管208的栅极和源极之间的电压，所述V GS3表示所述第三MOS管203的栅极和源极之间的电压，所述V TH表示阈值电压，所述阈值电压又称开启电压。例如，所述V TH可以表示所述第一MOS管208的阈值电压，具体地，可以为使得所述第一MOS管208源极和漏极之间开始形成导电沟道所需的栅极电压。
可以发现，由于V GS3<V GS4，因此，所述第一MOS管208提供的电流满足以下条件：
Figure PCTCN2018103841-appb-000002
本申请实施例中，通过所述第一MOS管208和所述第三MOS管203组成的电流镜产生上述第一电流，相比将恒流源作为上述第一电流的供电电流，能够为所述第一MOS管208的源极电压提供更大的压摆率，进而提高传输信号的建立速度和传输速率。
换句话说，本申请实施例中，将所述第一MOS管208的源极作为所述第一发送电路220的输出端，能够在传输信号(即上述第一电流)的建立过程中为所述传输信号提供较大的摆率，进而能够提高传输信号的建立速度，进而实现数据接口之间数据的高速传输。
可选地，如图3所示，所述第一偏置电路211可以包括：
第四MOS管201和第一电流源204。
具体地，所述第四MOS管201的源极用于接收电源电压，所述第四 MOS管201的栅极与所述第四MOS管201的漏极相连，所述第四MOS管201的漏极通过所述第一电流源204连接至地，所述第四MOS管201的栅极与第二MOS管202的栅极相连。
换句话说，本申请实施例中，所述第四MOS管201与所述第二MOS管202组成的电流镜用于为所述电流控制电路212提供偏置电流。
应当理解，图3所示的第一偏置电路211仅为示例，本发明实施例中的第一偏置电路211旨在为电流控制电路212提供偏置电流。本发明实施例对所述第一偏置电路211的具体电路结构和使用工艺不做限定。
还应理解，图3所示的电路结构仅为本申请实施例的第一发送电路220的示例，本申请实施例不限于此。例如，在其它可替代实施例中，图3所示的电路结构中，所述第一电流的供电电路也可以是恒流源。当芯片内的功能模块，比如处理器等向其所连接的另一芯片(即，对端芯片)发送数据或者命令(需要传输的信号)，可发送与需要传输的信号对应的输入信号Vin至接口电路，接口电路中的一对开关205与207受控于Vin而形成组合状态，使得MOS管208源极因向对端芯片的数据接口产生灌入电流Iout或者抽取电流Iout的效果，从而使得对端“接收”到不同的信号，也就是实现了向对端“发送”不同的信号，实现输入信号的传递。
图4是图2所示的第一发送电路220的另一电路结构的示例。
如图4所示，在本实施例中，所述第一发送电路220可以包括：
开关221、电流源222、电流源223以及开关224。
具体地，所述开关221的一端连接到电源电压，所述开关221的另一端通过电流源222连接至电流源223的一端，所述电流源223的另一端通过所述开关224连接至地。其中，所述输入信号Vin用于控制所述开关221和所述开关224的导通或断开，所述电流源222和所述电流源223之间相连的端口作为所述第一发送电路220的输出端，所述输出端用于接收或者输出所述第一电流。
更具体地，所述输入信号Vin控制所述开关221导通且所述开关224断开时，所述输出端向所述第一接收电路输出所述第一电流，且所述第一电流的大小等于所述电流源222输出的电流。所述输入信号Vin控制所述开关221断开且所述开关224导通时，所述输出端从所述第一接收电路接收所述第一电流，且所述第一电流的大小等于所述电流源223输出的电流。
上文结合图2至图4，侧重描述了本申请实施例的包括第一发送电路220的数据接口210，下文结合图5至图7，对本申请实施例的具有接收数据功能的数据接口进行示例性说明。
图5是本申请实施例的另一数据接口310的示意性框图。
如图5所示，所述数据接口310可以包括：
第二接收电路330，所述第二接收电路330用于从与所述数据接口310相连的对端接口的第二发送电路接收第二电流，或者向所述对端接口的所述第二发送电路输出第二电流，并根据所述第二电流可生成第二电压信号。
其中，所述第二发送电路可以是与所述数据接口310相连的对端数据接口中的发送电路。例如，图5所示的数据接口310为图1所示的数据接口110时，所述第二接收电路330可以为图1所示的接收电路115，所述第二发送电路可以是图1所述的数据接口130中的发送电路135。
本申请实施例中，与所述数据接口310相连的对端数据接口通过向所述第二接收电路330灌入所述第二电流，或者从所述数据接口310抽取所述第二电流的方式，向所述数据接口310传输信号。换句话说，所述第二接收电路330可以通过灌入或抽取的所述第二电流的电流值的大小，生成所述第二电压信号。
可选地，如图5所示，所述数据接口310还可以包括：
静电保护电路320，所述第二接收电路330通过所述静电保护电路320连接至绑定线340的一端，所述绑定线340的另一端用于连接所述第二发送电路。
可选地，在本申请的一个实施例中，所述数据接口310用于半双工通信。
例如，所述数据接口310可以是如图1所示的数据接口110，所述第二接收电路330可以是如图1所示的接收电路115，所述静电保护电路320可以是图1所示的静电保护电路113，所述绑定线340可以是图1所示的绑定线120，所述第二发送电路可以是如图1所示的发送电路135。
又例如，所述数据接口310也可以是如图1所示的数据接口130，相应的，所述第二接收电路可以是如图1所示的接收电路131，所述第二发送电路可以是如图1所示的发送电路111，所述静电保护电路可以是如图1所示的静电保护电路133。
可选地，在本申请的一个实施例中，所述数据接口310可以用于单工通 信。
应理解，图5为数据接口310仅包括第二接收电路330和静电保护电路320的示例。但本申请实施例不限于此。
例如，所述数据接口310用于半双工通信时，还可以包括用于实现半双工通信的开关。
又例如，在其他可替代实施例中，所述数据接口310也可以不包括所述静电保护电路320。
可选地，在本申请的一个实施例中，所述第二接收电路330可以通过共栅放大电路来实现。
图6是本申请实施例的将共栅放大电路作为所述第二接收电路330的示例。
如图6所示，所述第二接收电路330可以包括：
MOS管301、电阻302、寄生电容303、寄生电容304以及负载电阻305。
具体地，电阻302可以是输入电阻，作为输入电路的等效电阻；所述MOS管301的源极通过电阻302与对端数据接口的发送电路相连，例如与所述第二接收电路330所在的数据接口相连的对端数据接口中的发送电路，且所述MOS管301的源极通过寄生电容303连接至地，所述MOS管301的漏极通过寄生电容304连接至地，且所述MOS管301的漏极通过所述负载电阻305连接至电源电压，所述MOS管301的漏极作为所述第二接收电路330的输出端，用于输出所述第二电压信号。
本申请实施例中，所述MOS管301的源极用于接收或者输出所述第二电流，所述第二电流承载的信息量经过所述电阻302能够形成传输电平VIN。进一步地，所述MOS管301的漏极将所述传输电平VIN转换为所述第二电压信号，并输出所述第二电压信号。
假设忽略MOS管301的沟道长度的调制效应，则可以认为所述第二接收电路330的输入和输出是彼此孤立的，即所述第二接收电路330没有寄生电容跨接在输入和输出之间，从而能够避免寄生电容的米勒效应，进而能够增大所述第二接收电路330的带宽。
也就是说，本申请实施例中，将共栅放大电路作为所述第二接收电路330能够降低所述第二接收电路330的输出信号(即所述第二电压信号)的建立时间，进而提高所述数据接口310的传输速率。
应理解，图6所示的第二接收电路330仅为示例，但本申请实施例不限于此。例如，在图6所示的第二接收电路330中，所述电阻302为信号源的内阻，所述电阻305作为电流源内阻(假设电阻305连接到电流源以接收电源电压)，在其具体实现中，所述电阻302和所述电阻305可以等效为其他等效器件或者等效元件。
图7是图6所示的第二接收电路330的具体电路设计的示例。
图6可以看作是图7电路对应的小信号模型图。
如图7所示，所述第二接收电路330可以包括：
电压比较电路350和第二偏置电路360。
具体地，所述第二偏置电路360用于为所述电压比较电路350提供偏置电流。所述电压比较电路350用于通过从所述第二发送电路接收第二电流或向所述第二发送电路输出第二电流，并根据第二电流生成第二电压信号。
本申请实施例中，所述第二电流承载有所述第二接收电路330待接收的信息量，所述第二接收电路330用于将所述第二电流承载的信息量转换为所述第二电压信号，并将所述第二电压信号发送给与所述数据接口310连接的处理器。
可选地，如图7所示，所述电压比较电路350可以包括：
第五MOS管321、第六MOS管325、第七MOS管322、第八MOS管324和第二电阻326。
具体地，所述第五MOS管321的源极用于接收电源电压，并且所述第五MOS管321的漏极与所述第六MOS管325的漏极连接，所述第六MOS管325的源极用于接收或者输出所述第二电流，所述第七MOS管322的源极用于接收电源电压，所述第七MOS管322的漏极与所述第八MOS管324的漏极相连，所述第八MOS管324的源极通过所述第二电阻326连接至地，所述第五MOS管321的栅极与所述第七MOS管322的栅极连接，所述第六MOS管325的栅极连接至所述第八MOS管324的栅极，所述第八MOS管324的漏极与所述第八MOS管324的栅极相连。
可选地，如图7所示，电压比较电路350还可以包括：
第三电阻327。
具体地，所述第六MOS管325的源极通过所述第三电阻327连接至地。
可选地，在本申请的一个实施例中，所述第三电阻327可以是外接电阻。
本申请实施例中，所述第三电阻327用于将所述第二电流承载的信号量(即B端的电压)转换为传输电平VIN，以便所述电压比较电路350根据所述传输电平VIN输出所述第二电压信号。其中，所述第二电压信号可以是逻辑数字信号。
本申请实施例中，所述第五MOS管321、所述第六MOS管325、所述第七MOS管322、所述第八MOS管324和所述第二电阻326可以组成所述电压比较电路350的放大电路。所述放大电路的一个接入端(如图所示的C端)为所述第八MOS管324的源极，所述C端的电平为所述第八MOS管324的源极电流与所述第二电阻326的乘积，所述C端的电平为固定电平。所述放大电路的另一个接入端(如图所示的B端)用于接收上述第二电流，所述B端的电平为所述第二电流承载的信号量经过所述第三电路327转换形成的电平。
假设C端的电压为翻转阈值电平V r且所述第二电流承载的信号量(即B端的电压)为传输电平VIN，则当VIN＞V r时所述第二接收电路330的D端输出高电平，当VIN＜V r时所述第二接收电路330的D端输出低电平。
也就是说，所述第二电流承载的信号量的判决标准是所述电压比较电路350的翻转阈值电平V r。
由于所述电压比较电路350的传输损耗可以表示为：
I P＝C×V×f              (3)
其中，C表示数据接口的总寄生电容，V表示传输电平(即VIN)的幅值，f表示传输速率。
因此，当所述翻转阈值电平V r设置的比较低时，所述传输电平VIN无需以满摆幅翻转。也就是说，所述电压比较电路350采用图7所示的电路设计时，能够有效降低传输电平VIN的幅值V，进而降低所述数据接口310的功耗。
例如，以通用输入输出接口(General Purpose Input Output，GPIO)为例，GPIO的传输电平为电源电压，假设将本申请实施例中的数据接口的传输电平设置为电源电压的十分之一，则在同等条件下，本申请实施例的数据接口310的传输损耗仅为GPIO的传输损耗的十分之一。
可选地，在本申请的一个实施例中，所述翻转阈值电平V r可以通过改变第九MOS管311和第七MOS管322的比例进行调整，也可以通过设置所述 第二电阻326的阻值进行调整。
可选地，如图7所示，所述第二偏置电路360可以包括：
第九MOS管311和第二电流源312。
具体地，所述第九MOS管311的源极用于接收电源电压，所述第九MOS管311的栅极与所述第五MOS管321的栅极相连，所述第九MOS管311的漏极通过所述第二电流源312连接至地。
应当理解，图7所示的第二偏置电路360的电路结构仅为示例，本发明实施例中的第二偏置电路360旨在为所述电压比较电路350提供偏置电流。本发明实施例对所述第二偏置电路360的具体电路结构和使用工艺不做限定。
可选地，如图7所示，所述电压比较电路350还可以包括：
第一反相器331和第二反相器332。
具体地，第六MOS管325的漏极通过第一反相器331连接至第二反相器332。
本申请实施例中，所述第一反相器331和所述第二反相器332用于对D端的电平进行整形，使得所述电压比较电路350输出的所述第二电压信号为处理器能够识别的数字信号“1”或者数字信号“0”。
可选地，如图7所示，电压比较电路350还包括：
第六开关323。
具体地，所述第六开关323的一端用于接收电源电压，所述第六开关323的另一端与第五MOS管321的栅极相连。
本申请实施例中，所述第六开关导通时，所述第九MOS管311、第五MOS管321以及第七MOS管322处于断开状态。由此，本申请实施例中的所述数据接口310不需要进行数据接收时，可以通过导通所述第六开关323来关闭所述数据接口310的接收功能，能够有效降低耗电量，进一步降低所述数据接口310的成本。
需要注意的是，由于信道容易受到干扰，倘若所述第二电流承载的信号量(即传输电平VIN)在所述电压比较电路350的翻转阈值电平V r附近跳动时，所述电压比较电路350的输出结果容易出现错误。
为了解决上述问题，可选地，在本申请的一个实施例中，所述翻转阈值电平V r可以包括一个迟滞量，即噪声容限，以增强所述电压比较电路350的 抗干扰能力。
图8是本申请实施例的具有迟滞功能的电压比较电路350的示例。
如图8所示，所述电压比较电路350还可以包括：
第四电阻328和第五开关329。
具体地，所述第八MOS管324的源极与所述第三电阻326的一端相连，所述第三电阻326的另一端通过所述第四电阻328连接至地，所述第四电阻328的一端通过所述第五开关329连接至所述第四电阻328的另一端，所述第一反相器311输出的信号用于控制所述第五开关329的导通或者断开。
可选地，在本申请的一个实施例中，当传输电平VIN从0开始上升时，如图8所示，A点电压为高电平，所述第五开关329处于断开状态，所述电压比较电路350的翻转阈值电平为：
V r+＝I×(R 1+R 2)             (4)
其中，I表示所述第三电阻326和所述第四电阻328上的电流，所述R 2表示所述第三电路326的阻值，所述R 1表示所述第四电阻328的阻值。
进一步地，随着传输电平VIN继续上升并超过翻转阈值电平V r+，A点电压从高电平变为低电平，所述第五开关329处于导通状态，所述第四电阻328被短路，这种情况下，所述电压比较电路350的翻转阈值电平为：
V r-＝I×R 2              (5)
通过以上分析可以发现，当传输电平VIN从0逐渐上升并超过翻转阈值电平V r+后，只要噪声抖动不超过-(I×R 1)，则所述电压比较电路350的输出是不会翻转成低电平。反之，当传输电平VIN从VDD逐渐下降并低于翻转阈值电平V r-后，只要噪声抖动不超过+(I×R 1)，则所述电压比较电路350的输出不会翻转为高电平。即，所述电压比较电路350的翻转阈值电平存在(I×R 1)的迟滞量，这也是所述电压比较电路350的输入噪声的容限。
本发明实施例中还提供了一种芯片或者芯片系统，其中，该芯片可以配置有上述涉及的至少一种数据接口，或者，该芯片系统中的第一芯片和第二芯片之间采用上述涉及至少一种的数据接口连接。
图9是本申请实施例的芯片系统400的电路设计的示例。
如图9所示，所述芯片系统400可以包括：
芯片410和芯片420，所述芯片410可以包括图3所示的第一发送电路220，所述芯片420可以包括图7所示的第二接收电路330。所述芯片410 和所述芯片420通过所述第一发送电路220和所述第二接收电路330进行通信。
其中，开关205和开关207受到输入信号的控制。
具体地，当输入信号控制所述开关205导通且所述开关207断开，所述芯片410中的所述第一发送电路220向所述芯片420中的所述第二接收电路330输出电流，即电流从A点流向B点，B点电压迅速升高。当B点电压超过C点电压时，D点电压升高并达到反相器331的翻转阈值电压，最终由反相器332输出高电平。至此，所述第二接收电路330成功接收到所述第一发送电路220发送的高电平信号。
当输入信号控制开关开关205断开且开关207导通，所述芯片410中的所述第一发送电路220接收所述芯片420中的所述第二接收电路330输出的电流，即电流从B点流向A点，B点电压迅速降低。当B点电压低于C点电压时，D点电压下降并达到反相器311的翻转阈值电平，最终由反相器332输出高电平。至此，所述第二接收电路330成功接收到所述第一发送电路220发送的低电平信号。
综上所述，本申请实施例提供的芯片410、芯片420和芯片系统400，采用电流作为传输信号的载体，并通过单端输出的方式进行数据传输，避免了采用回路的电路设计进行数据传输，能够有效降低数据接口的成本。
此外，所述芯片410作为发射端时，将MOS管208的源端作为所述数据接口的第一发送电路220的输出端，能够在传输信号建立过程中为所述传输信号提供较大的摆率，进而能够提高传输信号的建立速度，进而实现数据的高速传输。所述芯片420作为接收端时，一方面，通过调整所述数据接口中电压比较电路的翻转阈值电平，能够有效降低信号量的传输电平，进而降低所述数据接口的功耗。另一方面，所述电压比较电路中采用共栅放大电路能够有效提高所述电压信号的建立速度，进而实现数据的高速传输。应理解，为了避免重复，此处对所述第一发送电路220和所述第二接收电路330的具体结构不再赘述。
应理解，以上结合图1至图9详细描述了本申请的优选实施方式，但是，本申请并不限于上述实施方式中的具体细节，在本申请的技术构思范围内，可以对本申请的技术方案进行多种简单变型，这些简单变型均属于本申请的保护范围。
例如，MOS管根据“通道”(工作载流子)的极性不同，可以分为“N型”MOS管(NMOSFET)与“P型”MOS管(PMOSFET)，对于NMOSFET，其源极和漏极接在N型半导体上，接高压为漏端，接低压为源端，实际电流方向为流入漏极。对于PMOSFET，其源极和漏极则接在P型半导体上，接高压为源端，接低压为漏端，实际电流方向为流出漏极。以图8所示的第二偏置电路360为例，所述第二偏置电路360包括第九MOS管311，所述MOS管311为“P型”MOS管。但本发明实施例不限于此。例如，在其它可替代实施例中，可以将所述MOS管311设计为“N型”MOS管，并适应性的改进所述电压比较电路350中的部分器件，使得所述第二偏置电路360能够为所述电压比较电路350提供偏置电流即可。
另外，需要说明的是，在上述具体实施方式中所描述的各个具体技术特征，在不矛盾的情况下，可以通过任何合适的方式进行组合，为了避免不必要的重复，本申请对各种可能的组合方式不再另行说明。此外，本申请的各种不同的实施方式之间也可以进行任意组合，只要其不违背本申请的思想，其同样应当视为本申请所公开的内容。
最后，需要说明的是，在本发明实施例和所附权利要求书中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本发明实施例。例如，在本发明实施例和所附权利要求书中所使用的单数形式的“上述”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的部件，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明实施例的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的装置和部件，可以是或者也可以不是物理上分开的。可以根据实际的需要选择其中的部分或者全部部件来实现本发明实施例的目的。
以上内容，仅为本发明实施例的具体实施方式，但本发明实施例的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明实施例揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明实施例的保护范围之内。因此，本发明实施例的保护范围应以权利要求的保护范围为准。

Claims (27)

  1. 一种数据接口，其特征在于，所述数据接口应用于发送端或者半双工通信，所述数据接口包括：
    第一发送电路；
    所述第一发送电路用于接收输入信号，并根据所述输入信号向与所述数据接口相连的对端接口的第一接收电路输出第一电流，或者根据所述输入信号从所述对端接口的所述第一接收电路接收第一电流，以在对端接口产生与所述输入信号对应的第一电压信号。
  2. 根据权利要求1所述的数据接口，其特征在于，所述第一发送电路包括：
    第一MOS管和电流控制电路；
    所述电流控制电路受控于所述输入信号，以控制所述第一MOS管的源极输出或接收所述第一电流。
  3. 根据权利要求2所述的数据接口，其特征在于，所述第一发送电路进一步包括：
    第一偏置电路，所述第一偏置电路通过所述电流控制电路连接至所述第一MOS管，所述第一偏置电路用于为所述电流控制电路提供偏置电流。
  4. 根据权利要求2或3所述的数据接口，其特征在于，所述电流控制电路包括：
    第一开关和第二开关；
    所述第一开关的一端用于接收电源电压，所述第一开关的另一端通过所述第一MOS管连接至所述第二开关的一端，所述第二开关的另一端连接至地。
  5. 根据权利要求4所述的数据接口，其特征在于，所述电流控制电路还包括：
    第二MOS管、第三MOS管和第一电阻；
    所述第二MOS管的源极用于接收所述电源电压，所述第二MOS管的漏极通过所述第三MOS管连接至所述第一电阻的一端，所述第一电阻的另一端连接至地，所述第三MOS管的栅极与所述第一MOS管的栅极相连。
  6. 根据权利要求4所述的数据接口，其特征在于，所述第一偏置电路包 括：
    第四MOS管和第一电流源；
    所述第四MOS管的源极用于接收电源电压，所述第四MOS管的栅极与所述第四MOS管的漏极相连，所述第四MOS管的漏极通过所述第一电流源连接至地，所述第四MOS管的栅极与所述第二MOS管的栅极相连。
  7. 根据权利要求1至6中任一项所述的数据接口，其特征在于，所述数据接口还包括：
    静电保护电路，所述第一发送电路通过所述静电保护电路连接至绑定线的一端，所述绑定线的另一端用于连接所述第一接收电路。
  8. 根据权利要求7所述的数据接口，其特征在于，当所述数据接口应用于半双工通信，所述数据接口还包括：
    第二接收电路；
    所述第二接收电路通过所述静电保护电路连接至所述绑定线的一端，所述绑定线的另一端用于连接所述对端接口的第二发送电路；
    所述第二接收电路用于通过所述绑定线和所述静电保护电路从所述第二发送电路接收第二电流或向所述第二发送电路输出第二电流，并根据所述第二电流生成第二电压信号。
  9. 根据权利要求8所述的数据接口，其特征在于，所述数据接口还包括：
    第三开关和第四开关；
    所述第一发送电路通过所述第三开关连接至所述静电保护电路，所述第二接收电路通过所述第四开关连接至所述静电保护电路。
  10. 根据权利要求8或9所述的数据接口，其特征在于，所述第二接收电路包括：
    电压比较电路和第二偏置电路；
    所述第二偏置电路用于为所述电压比较电路提供偏置电流，所述电压比较电路用于接收或输出所述第二电流，并根据所述第二电流生成所述第二电压信号。
  11. 根据权利要求10所述的数据接口，其特征在于，所述电压比较电路包括：
    第五MOS管、第六MOS管、第七MOS管、第八MOS管和第二电阻；
    所述第五MOS管的源极用于接收电源电压，所述第五MOS管的漏极 与所述第六MOS管的漏极连接，所述第六MOS管的源极用于接收或者输出所述第二电流，所述第七MOS管的源极用于接收电源电压，所述第七MOS管的漏极与所述第八MOS管的漏极相连，所述第八MOS管的源极通过所述第二电阻连接至地，所述第五MOS管的栅极与所述第七MOS管的栅极连接，所述第六MOS管的栅极连接至所述第八MOS管的栅极，所述第八MOS管的漏极与所述第八MOS管的栅极相连。
  12. 根据权利要求11所述的数据接口，其特征在于，所述电压比较电路还包括：
    第一反相器和第二反相器；
    所述第六MOS管的漏极通过所述第一反相器连接至所述第二反相器。
  13. 根据权利要求11所述的数据接口，其特征在于，所述电压比较电路还包括：
    第三电阻；
    所述第六MOS管的源极通过所述第三电阻连接至地。
  14. 根据权利要求11所述的数据接口，其特征在于，所述电压比较电路还包括：
    第四电阻和第五开关；
    所述第八MOS管的源极与所述第三电阻的一端相连，所述第三电阻的另一端通过所述第四电阻连接至地，所述第四电阻的一端通过所述第五开关连接至所述第四电阻的另一端，所述第一反相器输出的信号用于控制所述第五开关的导通或者断开。
  15. 根据权利要求11所述的数据接口，其特征在于，所述电压比较电路还包括：
    第六开关；
    所述第六开关的一端用于接收电源电压，所述第六开关的另一端与所述第五MOS管的栅极相连。
  16. 根据权利要求11所述的数据接口，其特征在于，所述第二偏置电路包括：
    第九MOS管和第二电流源；
    所述第九MOS管的源极用于接收电源电压，所述第九MOS管的栅极与所述第五MOS管的栅极相连，所述第九MOS管的漏极通过所述第二电 流源连接至地。
  17. 一种数据接口，其特征在于，所述数据接口应用于接收端，所述数据接口包括：
    第二接收电路；
    所述第二接收电路用于从与所述数据接口相连的对端接口的第二发送电路接收第二电流，或者向所述对端接口的所述第二发送电路输出第二电流，并根据所述第二电流生成第二电压信号。
  18. 根据权利要求17所述的数据接口，其特征在于，所述数据接口还包括：
    静电保护电路；
    所述第二接收电路通过所述静电保护电路连接至绑定线的一端，所述绑定线的另一端用于连接所述第二发送电路。
  19. 根据权利要求17或18所述的数据接口，其特征在于，所述第二接收电路包括：
    电压比较电路和第二偏置电路；
    所述第二偏置电路用于为所述电压比较电路提供偏置电流，所述电压比较电路用于接收或输出所述第二电流，并根据所述第二电流生成所述第二电压信号。
  20. 根据权利要求19所述的数据接口，其特征在于，所述电压比较电路包括：
    第五MOS管、第六MOS管、第七MOS管、第八MOS管和第二电阻；
    所述第五MOS管的源极用于接收电源电压，所述第五MOS管的漏极与所述第六MOS管的漏极连接，所述第六MOS管的源极用于接收或者输出所述第二电流，所述第七MOS管的源极用于接收电源电压，所述第七MOS管的漏极与所述第八MOS管的漏极相连，所述第八MOS管的源极通过所述第二电阻连接至地，所述第五MOS管的栅极与所述第七MOS管的栅极连接，所述第六MOS管的栅极连接至所述第八MOS管的栅极，所述第八MOS管的漏极与所述第八MOS管的栅极相连。
  21. 根据权利要求20所述的数据接口，其特征在于，所述电压比较电路还包括：
    第一反相器和第二反相器；
    所述第六MOS管的漏极通过所述第一反相器连接至所述第二反相器。
  22. 根据权利要求20所述的数据接口，其特征在于，所述电压比较电路还包括：
    第三电阻；
    所述第六MOS管的源极第三电阻通过所述第三电阻连接至地。
  23. 根据权利要求20所述的数据接口，其特征在于，所述电压比较电路还包括：
    第四电阻和第五开关；
    所述第八MOS管的源极与所述第二电阻的一端相连，所述第二电阻的另一端通过所述第四电阻连接至地，所述第二电阻的一端通过所述第五开关连接至所述第二电阻的另一端，所述第一反相器输出的信号用于控制所述第五开关的导通或者断开。
  24. 根据权利要求20所述的数据接口，其特征在于，所述电压比较电路还包括：
    第六开关；
    所述第六开关的一端用于接收电源电压，所述第六开关的另一端与所述第五MOS管的栅极相连。
  25. 根据权利要求20所述的数据接口，其特征在于，所述第二偏置电路包括：
    第九MOS管和第二电流源；
    所述第九MOS管的源极用于接收电源电压，所述第九MOS管的栅极与所述第五MOS管的栅极相连，所述第九MOS管的漏极通过所述第二电流源连接至地。
  26. 一种芯片，其特征在于，包括：
    权利要求1至16中任一项所述的数据接口，和/或，权利要求17至25中任一项所述的数据接口。
  27. 一种芯片系统，其特征在于，包括：
    多个芯片，所述多个芯片中的芯片和第二芯片之间采用以下至少一种数据接口连接：
    权利要求1至16中任一项所述的数据接口，和/或，权利要求17至25中任一项所述的数据接口。
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