WO2020034069A1 - 数据接口、芯片和芯片系统 - Google Patents

数据接口、芯片和芯片系统 Download PDF

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Publication number
WO2020034069A1
WO2020034069A1 PCT/CN2018/100290 CN2018100290W WO2020034069A1 WO 2020034069 A1 WO2020034069 A1 WO 2020034069A1 CN 2018100290 W CN2018100290 W CN 2018100290W WO 2020034069 A1 WO2020034069 A1 WO 2020034069A1
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WIPO (PCT)
Prior art keywords
mos tube
circuit
voltage
mos
data interface
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PCT/CN2018/100290
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English (en)
French (fr)
Inventor
张孟文
杨博新
易律凡
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to CN201880001092.1A priority Critical patent/CN111052610A/zh
Priority to EP18917033.5A priority patent/EP3629479B1/en
Priority to PCT/CN2018/100290 priority patent/WO2020034069A1/zh
Priority to US16/658,063 priority patent/US10855279B2/en
Publication of WO2020034069A1 publication Critical patent/WO2020034069A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018592—Coupling arrangements; Interface arrangements using field effect transistors only with a bidirectional operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05F—STATIC ELECTRICITY; NATURALLY-OCCURRING ELECTRICITY
    • H05F3/00—Carrying-off electrostatic charges
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits

Definitions

  • Embodiments of the present invention relate to the field of communications, and more specifically, to a data interface, a chip, and a chip system.
  • MCU Microcontroller Unit
  • a general input / output interface (General Input / Output, GPIO) is usually used.
  • GPIO General Input / Output
  • the parasitic capacitance of the interconnected two GPIOs and the parasitic capacitance of the traces between the two GPIOs are as high as 10 picofarads (pf). Therefore, in the high-speed transmission scenario, the power consumption of the parasitic capacitance will be excessive.
  • LVDS Low-Voltage Differential Signaling
  • LVDS usually requires two sets of pins, increasing interconnect costs and manufacturing costs.
  • a data interface, chip and chip system are provided. This data interface can not only effectively reduce the power consumption of parasitic capacitance, but also reduce manufacturing costs.
  • a data interface including:
  • a charge transmitting circuit connected to a binding line through the electrostatic protection circuit, the charge transmitting circuit including a first capacitor, the charge transmitting circuit transferring a charge in the first capacitor to a parasitic capacitance of the electrostatic protection circuit And a parasitic capacitance of the binding line to generate a first voltage signal, and outputting the first voltage signal through the binding line.
  • the data interface according to the embodiment of the present invention not only can reduce the power consumption loss caused by the parasitic capacitance in the communication channel, but also can effectively reduce the time delay by redistributing the charge in the charging capacitor and the parasitic capacitance.
  • the use of two-line communication is avoided, and manufacturing costs are reduced relative to LVDS.
  • the charge sending circuit includes:
  • the first capacitor the first metal oxide semiconductor MOS tube, the second MOS tube, and the third MOS tube;
  • the source of the first MOS tube is used to receive a power supply voltage
  • the drain of the first MOS tube is connected to ground through the first capacitor
  • the gate of the first MOS tube is used to receive a first control signal.
  • the drain of the first MOS tube is connected to the source of the second MOS tube
  • the drain of the second MOS tube is used to output the first voltage signal
  • the gate of the second MOS tube The third MOS transistor is used to receive the first control signal.
  • the drain of the second MOS transistor is connected to the ground.
  • the gate of the third MOS transistor is used to receive the second control signal.
  • the first control signal and the second control signal are both control signals generated according to a third control signal.
  • the voltage value of the third control signal is the first level
  • the The second MOS transistor is turned on, the first MOS transistor and the third MOS transistor are turned off;
  • the voltage value of the third control signal is the second level
  • the second MOS transistor is turned off, A MOS transistor and the third MOS transistor are turned on, and the first level is greater than the second level.
  • the data interface further includes:
  • the signal receiving conversion circuit is connected to the binding line through the electrostatic protection circuit
  • the signal receiving and converting circuit is configured to receive a second voltage signal through the binding line, and convert the second voltage signal into a third voltage signal.
  • the signal receiving and converting circuit includes:
  • the bias circuit is configured to provide a bias current and a bias voltage signal to the at least one voltage comparison circuit
  • the voltage comparison circuit is configured to receive the second voltage signal and the bias voltage signal, and generate the third voltage signal according to a comparison result between the second voltage signal and the bias voltage signal.
  • the voltage comparison circuit includes:
  • the drain of the fourth MOS tube is used to receive a bias current output by the bias circuit, the gate of the fourth MOS tube is used to receive the bias voltage signal, and the source of the fourth MOS tube The pole is used for receiving the second voltage signal.
  • the voltage comparison circuit further includes:
  • a drain of the fourth MOS transistor is connected to the second inverter through the first inverter
  • the output signal of the second inverter is the third voltage signal.
  • the voltage comparison circuit further includes:
  • a drain of the fourth MOS transistor is connected to one end of the voltage dividing circuit, and the other end of the voltage dividing circuit is used to receive a bias current
  • Two ends of the voltage dividing circuit are respectively connected to a first input terminal and a second input terminal of the signal generating circuit;
  • the signal generating circuit is configured to receive a voltage signal across the voltage dividing circuit, and generate a fourth voltage signal according to the voltage signal across the voltage dividing circuit.
  • the voltage comparison circuit further includes:
  • An output terminal of the signal generating circuit is connected to an input terminal of the third inverter, and a signal output from an output terminal of the third inverter is the third voltage signal.
  • the signal generating circuit includes:
  • a fifth MOS transistor and a sixth MOS transistor A fifth MOS transistor and a sixth MOS transistor
  • the two ends of the voltage dividing circuit are respectively connected to the gate of the fifth MOS transistor and the gate of the sixth MOS transistor.
  • the fifth MOS transistor is connected to the ground through the sixth MOS transistor.
  • the drain of the sixth MOS transistor is used to output the fourth voltage signal.
  • the voltage dividing circuit includes:
  • the source of the seventh MOS tube is connected to the gate of the fifth MOS tube, the gate of the seventh MOS tube is connected to the gate of the sixth MOS tube, and the gate of the seventh MOS tube An electrode is connected to the drain of the seventh MOS transistor, and the drain of the seventh MOS transistor is connected to the ground through the first current source.
  • the bias circuit includes:
  • the eighth MOS transistor is connected to the ground through the second current source
  • the ninth MOS transistor is connected to one end of the first resistor through the tenth MOS transistor, and the other end of the first resistor is grounded;
  • the eleventh MOS transistor is configured to provide a bias current for the voltage comparison circuit
  • the eighth MOS tube and the ninth MOS tube form a first current mirror, and the mirror ratio of the eighth MOS tube to the ninth MOS tube is 1: K;
  • the eighth MOS tube and the eleventh MOS tube constitute a second current mirror, and the mirror ratio of the eighth MOS tube and the eleventh MOS tube is 1: K * L, and the tenth MOS tube
  • the mirror ratio of the tube to the fourth MOS tube is 1: L, where K> 1 and L> 1.
  • the bias circuit further includes:
  • the twelfth MOS tube, the gate of the twelfth MOS tube is used to receive a fourth control signal, the drain of the twelfth MOS tube is connected to the gate of the tenth MOS tube, and the tenth The source of the two MOS transistors is connected to ground.
  • a data interface including:
  • a fourth MOS tube a voltage dividing circuit, and a signal generating circuit
  • the drain of the fourth MOS transistor is connected to one end of the voltage dividing circuit, the other end of the voltage dividing circuit is used to receive a bias current, and the gate of the fourth MOS transistor is used to receive a bias voltage.
  • a source of the fourth MOS tube is used to receive a second voltage signal sent by a transmitting end;
  • Two ends of the voltage dividing circuit are respectively connected to a first input terminal and a second input terminal of the signal generating circuit;
  • the signal generating circuit is configured to receive a voltage signal across the voltage dividing circuit, and generate a fourth voltage signal according to the voltage signal across the voltage dividing circuit.
  • the data interface further includes:
  • An output terminal of the signal generating circuit is connected to an input terminal of the third inverter.
  • the signal generating circuit includes:
  • a fifth MOS transistor and a sixth MOS transistor A fifth MOS transistor and a sixth MOS transistor
  • the two ends of the voltage dividing circuit are respectively connected to the gate of the fifth MOS transistor and the gate of the sixth MOS transistor.
  • the fifth MOS transistor is connected to the ground through the sixth MOS transistor.
  • the drain of the sixth MOS transistor is used to output the fourth voltage signal.
  • the voltage dividing circuit includes:
  • the source of the seventh MOS transistor is connected to the gate of the fifth MOS transistor, the gate of the seventh MOS transistor is connected to the gate of the sixth MOS transistor, and the gate of the seventh MOS transistor is connected.
  • An electrode is connected to the drain of the seventh MOS transistor, and the drain of the seventh MOS transistor is connected to the ground through the first current source.
  • the data interface further includes:
  • the bias circuit includes:
  • the eighth MOS transistor is connected to the ground through the second current source
  • the ninth MOS transistor is connected to one end of the first resistor through the tenth MOS transistor, and the other end of the first resistor is grounded;
  • the eleventh MOS transistor is configured to provide the bias current for the voltage dividing circuit
  • the eighth MOS tube and the ninth MOS tube form a first current mirror, and the mirror ratio of the eighth MOS tube to the ninth MOS tube is 1: K;
  • the eighth MOS tube and the eleventh MOS tube constitute a second current mirror, and the mirror ratio of the eighth MOS tube and the eleventh MOS tube is 1: K * L, and the tenth MOS tube The mirror ratio of the tube to the fourth MOS tube is 1: L.
  • the bias circuit further includes:
  • the twelfth MOS tube, the gate of the twelfth MOS tube is used to receive a fourth control signal, the drain of the twelfth MOS tube is connected to the gate of the tenth MOS tube, and the tenth The source of the two MOS transistors is connected to ground.
  • a chip including:
  • the data interface according to the first aspect and / or the data interface according to the second aspect.
  • a chip system including:
  • the first chip and the second chip among the multiple chips are connected by at least one of the following data interfaces:
  • FIG. 1 is an example of a data interface according to an embodiment of the present invention.
  • FIG. 2 is a schematic block diagram of an interface connection relationship when a data interface according to an embodiment of the present invention is applied to a transmitting end (a first data interface) and a receiving end (a second data interface).
  • FIG. 3 is an example of a charge transmitting circuit included in a data interface according to an embodiment of the present invention.
  • the signal receiving conversion circuit includes a bias circuit and a voltage comparison circuit.
  • FIG. 5 is an exemplary diagram of a signal receiving and converting circuit included in a data interface according to an embodiment of the present invention.
  • FIG. 6 is another example diagram of a signal receiving and converting circuit included in a data interface according to an embodiment of the present invention.
  • FIG. 7 is an example of a voltage dividing circuit included in a data interface according to an embodiment of the present invention.
  • FIG. 8 is another example of a data interface according to an embodiment of the present invention.
  • the data interface, chip, and chip system of the embodiments of the present invention are applicable to any occasion requiring data communication, and particularly applicable to occasions with high-speed and low-power communication interconnection.
  • the data interface is particularly suitable for data communication between chips. For example, data communication between internal chips of a chip system.
  • the communication channel between multiple chips is not visible to the outside, and when the carrier for transmitting signals is voltage or current, the parasitic capacitance in the communication channel will be too large.
  • the data interface uses electric charge as a carrier for transmitting signals, and transfers the electric charges of the capacitors in the sending circuit to the parasitic capacitors to generate the sending signals, thereby reducing the data. Interface power consumption.
  • FIG. 1 is a schematic block diagram of a data interface (single-ended) according to an embodiment of the present invention.
  • the data interface 101 may include: a charge transmitting circuit 102 and an electrostatic protection circuit 103; the charge transmitting circuit 102 is connected to a binding wire 104 through the electrostatic protection circuit 103; and the charge transmitting circuit 102
  • the first capacitor in the charge transmitting circuit 102 is transferred to the parasitic capacitance of the electrostatic protection circuit 103 and the parasitic capacitance of the binding line 104 to generate and output a first voltage signal through the binding line 104.
  • the electrostatic protection circuit 103 is designed to prevent static electricity from damaging the device, especially in a chip system including multiple chips, because the communication channel is not exposed to the outside of the entire chip system, so This electrostatic protection (ESD) circuit only needs to ensure that it can meet the requirements of the Charged Device Model (CDM), and its purpose is to reduce parasitic capacitance.
  • the bonding wires are necessary connecting wires between chip interconnections.
  • the data interface in the embodiment of the present invention not only can reduce the power consumption loss caused by the parasitic capacitance in the communication channel, but also can effectively reduce the time delay by using the redistribution of charge in the charging capacitor and the parasitic capacitance.
  • the use of two-line communication is avoided, and manufacturing costs are reduced relative to LVDS.
  • FIG. 1 is an example in which the data interface 101 includes only a transmitting circuit.
  • the data interface may further include a receiving circuit.
  • the data interface may further include a signal receiving conversion circuit, which is configured to receive a second voltage signal sent by the opposite data interface and perform conversion processing on the second voltage signal.
  • FIG. 2 is a schematic block diagram of a connection relationship between a first data interface and a second data interface according to an embodiment of the present invention.
  • the first data interface and the second data interface may be regarded as a local interface and a peer interface, respectively, or may be used as a sending interface and a receiving interface, respectively.
  • the first data interface 110 may include a first charge transmitting circuit 111 and a first signal receiving conversion circuit 115.
  • the first charge transmitting circuit 111 is connected to one end of the first electrostatic protection circuit 113 through a first switch 112.
  • the other end of the first electrostatic protection circuit 113 is connected to the second data interface 130 through a bonding wire 120.
  • the first signal receiving conversion circuit 115 is connected to the first electrostatic protection circuit 113 through a second switch 114.
  • the second data interface 130 may include a second charge transmitting circuit 135 and a second signal receiving conversion circuit 131.
  • the second charge transmitting circuit 135 is connected to one end of the second electrostatic protection circuit 133 through a third switch 134.
  • both the first data interface 110 and the second data interface 130 shown in FIG. 2 may include a set of a receiving circuit (ie, a signal receiving conversion circuit) and a transmitting circuit (ie, a charge transmitting circuit) having the same functions.
  • the first data interface 110 and the second data interface 130 can switch between the charge transmitting circuit and the signal receiving conversion circuit through the first switch 112, the second switch 114, the fourth switch 132, and the third switch 134.
  • the first switch 112 and the fourth switch 132 may be controlled by a control signal en1
  • the second switch 114 and the third switch 134 may be controlled by a control signal en2.
  • the first data interface 110 when the first data interface 110 is used as a transmitting end and the second data interface 130 is used as a receiving end, the first data interface 110 generates a voltage signal Vo1 and sends the voltage signal Vo1 to the second data interface through the binding line 120. 130.
  • the second data interface 130 When the first data interface 110 is used as a receiving end and the second data interface 130 is used as a transmitting end, the second data interface 130 generates a voltage signal Vo2 and sends the voltage signal Vo2 to the first data interface 110 through the binding line 120.
  • connection relationship of the data interface shown in FIG. 2 is only an example. In other alternative embodiments, if the data interface is only used for simplex communication, the above four switches are optional switches. It should be understood that the four switches shown in FIG. 2 are not necessarily real physical switches. For example, the switches in the charge transmitting circuit and the signal receiving conversion circuit may be implemented by multiplexing signals in the charge transmitting circuit and / or the signal receiving conversion circuit. Switch between. It should also be understood that although both the first data interface 110 and the second data interface 130 shown in FIG. 2 may include a set of signal receiving conversion circuits and charge transmitting circuits having the same function, the signal receiving conversion circuits and charge transmitting circuits The specific implementation circuit and / or process used may be different.
  • FIG. 3 is an example of a charge transmitting circuit according to an embodiment of the present invention.
  • the charge transmitting circuit in the embodiment of the present invention is exemplarily described below:
  • the charge transmission circuit may include:
  • Capacitor 143 Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET, MOS for short) 141, MOS tube 142 and MOS tube 144; the source of the MOS tube 141 is used to receive power Voltage, the drain of the MOS tube 141 is connected to the ground through the capacitor 143, the gate of the MOS tube 141 is used to receive the first control signal, the drain of the MOS tube 141 is connected to the source of the MOS tube 142, the The gate of the MOS tube 142 is used to receive the first control signal, the drain of the MOS tube 142 is used to output the first voltage signal Vo x , and the drain of the MOS tube 142 is connected to the ground through the MOS tube 144. The gate of the MOS tube 144 is used to receive the second control signal, and the source of the MOS tube 144 is grounded.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • the first control signal and the second control signal may be control signals generated based on a third control signal.
  • the third control signal when the voltage value of the third control signal is the first level, the MOS tube 142 is turned on, and the MOS tube 141 and the MOS tube 144 are turned off; the third control When the voltage value of the signal is the second level, the MOS tube 142 is turned off, the MOS tube 141 and the MOS tube 144 are turned on, and the first level is greater than the second level.
  • the first control signal and the second control signal may be control signals generated based on the third control signal and at least one of the following control signals: shown in FIG. 2 en1 (for controlling the first switch 112 and the fourth switch 132) and en2 (for controlling the second switch 114 and the third switch 134) shown in FIG. 2.
  • the first control signal is a control signal generated by the third control signal Di and en x
  • the first control signal en x ⁇ Di indicates that the control signal en x and the third control signal Di are passed through a "logical AND"
  • the second control signal en x ⁇ _Di represents a logical expression formed by connecting the negation of the control signal en x and the third control signal Di with a "logical AND”.
  • the control signal en x may be en1 or en2, and Vo x may be Vo1 or Vo2.
  • the circuit shown in FIG. 3 is the first one in the first data interface 110.
  • a charge transmitting circuit 111 The first charge transmitting circuit 111 can be used to generate a voltage signal Vo1.
  • the control signal en2 1, the first data interface 110 can be used as a receiving end, and the second data interface 130 can be used as a transmitting end. That is, the circuit shown in FIG. 3 is the second charge transmitting circuit 135 in the second data interface 130, and the second charge transmitting circuit 135 can be used to generate a voltage signal Vo2.
  • the MOS tube 141 can be turned on, so that the capacitor 143 is precharged to the power supply voltage Vdd, and the MOS tube 142 and the MOS tube 144 are controlled to be turned off. At this time, Vo1 output has high impedance The charge sending circuit is in a disabled state.
  • the power consumption of the GPIO that is flipped at full speed at the operating frequency F is as follows:
  • the signal receiving conversion circuit involved in the embodiment of the present invention may be connected to the binding line through the electrostatic protection circuit; the signal receiving conversion circuit is configured to receive a second voltage signal and convert the second voltage signal into a third voltage signal .
  • the signal receiving and converting circuit may include:
  • a bias circuit and at least one voltage comparison circuit the bias circuit is used to provide a bias current and a bias voltage signal to the at least one voltage comparison circuit, and the voltage comparison circuit is used to receive the second voltage signal and the bias voltage A third voltage signal according to a comparison result between the second voltage signal and the bias voltage signal, wherein the third voltage signal may be a signal directly used by a chip or a processor.
  • the signal receiving and converting circuit may include a bias circuit 210 and n voltage comparison circuits (a first voltage comparison circuit 231, a second voltage comparison circuit 232, and an nth voltage comparison circuit as shown in the figure). 233).
  • the data interface 110 in the embodiment of the present application when used as a receiving end, it can be used to include a plurality of first signal receiving conversion circuits 115, and each of the plurality of first signal receiving conversion circuits 115
  • a signal receiving conversion circuit 115 may include a bias circuit 210 and n voltage comparison circuits (a first voltage comparison circuit 231, a second voltage comparison circuit 232, and an nth voltage comparison circuit 233 as shown in the figure).
  • Each of the n voltage comparison circuits is respectively configured to receive a second voltage signal.
  • the n voltage comparison circuits can be used to receive n second voltage signals.
  • the n second voltage signals may include Vo 21 , Vo 22 through Vo 2n as shown in FIG. 4.
  • the first voltage comparison circuit 231 shown in FIG. 3 is configured to receive the second voltage signal.
  • the voltage signal Vo 21 and the bias voltage signal, and a third voltage signal is generated and output according to a comparison result between the second voltage signal Vo11 and the bias voltage signal, that is, a signal that can be directly used by a chip or a processor.
  • one bias circuit may be configured for multiple voltage comparison circuits, or one bias circuit may be configured for each voltage comparison circuit.
  • the configuration method of configuring one bias circuit for multiple voltage comparison circuits is adopted. In the scenario of parallel transmission, power consumption can be effectively reduced. It should be noted that, for a configuration manner in which a bias circuit is configured for a plurality of voltage comparison circuits, the circuit structures and / or using processes of the plurality of voltage comparison circuits may be different.
  • FIG. 5 and 6 are examples of a signal receiving conversion circuit according to the embodiment of the present invention.
  • An embodiment in which a single bias circuit corresponds to a single voltage comparison circuit (such as the voltage comparison circuit 231 shown in FIG. 4) is given below. Since some devices in FIG. 5 and FIG. 6 are similar, for convenience of explanation, the same reference numerals are used to represent the same components.
  • the signal receiving and converting circuit may include a bias circuit 210 and a voltage comparison circuit 231.
  • the bias circuit in the embodiment of the present invention is intended to provide a bias current and a bias voltage signal to the voltage comparison circuit.
  • the embodiment of the present invention does not limit the specific circuit structure and use process of the bias circuit.
  • the bias circuit 210 may include:
  • MOS tube 212 MOS tube 213, MOS tube 214, MOS tube 217, resistor 215, and current source 211;
  • MOS tube 212 is connected to ground through the current source 211;
  • MOS tube 213 is connected to the resistor 215 through the MOS tube 214 One end of the resistor 215 and the other end of the resistor 215 are grounded;
  • the MOS tube 217 is used to provide a bias current for the voltage comparison circuit 231;
  • the MOS tube 212 and the MOS tube 213 form a first current mirror, and the MOS tube 212 and the
  • the mirror ratio of the MOS tube 213 is 1: K;
  • the MOS tube 212 and the MOS tube 217 form a second current mirror, and the mirror ratio of the MOS tube 212 and the MOS tube 217 is 1: K * L, and the MOS tube 214
  • the mirror ratio with the MOS tube 242 is 1: L, where K> 1 and L> 1.
  • the resistor 215 is used to
  • the bias circuit 210 may include:
  • the gate of the MOS transistor 216 is used to receive a fourth control signal.
  • the fourth control signal may be en x .
  • the en x may be en1 shown in FIG. 2 (for controlling the first switch). 112 and the fourth switch 132) and en2 shown in FIG. 2 (for controlling the second switch 114 and the third switch 134).
  • the drain of the MOS tube 216 is connected to the gate of the MOS 214, and the source of the MOS tube 216 is connected to the ground.
  • the power loss of the data interface when it is in an inoperative state can be effectively saved.
  • the voltage comparison circuit 231 may include:
  • MOS tube 242 the drain of the MOS tube 242 is used to receive the bias current output by the bias circuit 210, the gate of the MOS tube 242 is used to receive the bias voltage signal, and the source of the MOS tube 242 is used to Receiving the second voltage signal.
  • the voltage comparison circuit 231 may further include:
  • the current source 211 provides a certain reference current for the entire signal receiving conversion circuit.
  • the MOS tube 212 and the MOS tube 213 form a first current mirror, and the current of the current source 211 is mirrored to the MOS tube 213 and the MOS tube.
  • the voltage drop across resistor 215 can be calculated according to formula (4):
  • V r K * I b * R (4)
  • the MOS tube 212 and the MOS tube 217 also constitute a current mirror. It is assumed that the MOS tube 212 and the MOS tube 217 form a second current mirror, and the mirror ratio of the MOS tube 212 and the MOS tube 217 is 1: K * L, then the current flowing through the MOS tube 217 in a saturated state is K * L * I b .
  • the MOS tube 242 is an amplifying tube in the voltage comparison circuit 231.
  • the mirror ratio of the MOS tube 214 to the MOS tube 242 is designed to be 1: L, when the voltage of the second voltage signal (Vox) is equal to the offset
  • the drain of the MOS tube 242 outputs 1 when Vox> Vr, and the drain of the MOS tube 242 outputs 0 when Vox ⁇ Vr.
  • the swing of the second voltage signal (Vox) is only in the order of several hundred mV, but the power supply voltage of the voltage comparison circuit 231 is relatively much higher. It is usually on the order of several V. Therefore, the drain node of the MOS tube 242 needs to swing from ground to the power supply voltage, and it depends on the parasitic capacitance of the charging node of the MOS tube 217. If the charging current is increased by increasing the aspect ratio of the MOS tube 217, the power consumption of the voltage comparison circuit 231 will increase sharply.
  • the embodiment of the present invention simply deforms the voltage comparison circuit 231 shown in FIG. 5 to form the voltage comparison circuit 231 shown in FIG. 6.
  • the voltage comparison circuit 231 may further include:
  • the signal generating circuit 248 is connected to a first input terminal and a second input terminal of the signal generating circuit 248.
  • the signal generating circuit 248 is configured to receive voltage signals from both ends of the voltage dividing circuit 245 and generate the voltage signals from the two ends of the voltage dividing circuit 245. Fourth voltage signal.
  • the voltage comparison circuit 231 may further include:
  • Inverter 249 the output terminal of the signal generating circuit 248 is connected to the input terminal of the inverter 249. At this time, the signal output from the output terminal of the inverter 249 is the third voltage signal.
  • the gates of the two MOS transistors in the inverter 243 are respectively used as one input terminal to form a signal generating circuit 248.
  • a voltage dividing circuit 245 is designed between the tube 217 and the MOS tube 242.
  • the signal generating circuit 248 may include:
  • MOS tube 246 and MOS tube 247 the two ends of the voltage dividing circuit 245 are respectively connected to the gate of the MOS tube 246 and the gate of the MOS tube 247, the MOS tube 246 is connected to the ground through the MOS tube 247, and the MOS tube The drain of the tube 247 is used to output the fourth voltage signal.
  • the voltage dividing circuit 245 may include:
  • MOS tube 311 and current source 312 the source of the MOS tube 311 is connected to the gate of the MOS tube 246, the gate of the MOS tube 311 is connected to the gate of the MOS tube 247, and the gate of the MOS tube 311 is connected to The drain of the MOS tube 311 is connected, and the drain of the MOS tube 311 is connected to the ground through the current source 312.
  • the MOS tube 242 enters the cut-off area, and the MOS tube 217 pulls up the voltage across the voltage dividing circuit 245 (Vop and Von shown in FIG. 6) until Vop rises to the power supply voltage.
  • the MOS tube 217 is caused to enter the linear region. Because the current of the current source 312 described in FIG. 7 is much smaller than the current of the current source 211 described in FIG. 6, Vop is approximately equal to the power supply voltage, thereby ensuring that the MOS tube 246 can be turned off normally.
  • the voltage dividing circuit 245 has a Vgs voltage drop, so that Von will never rise to the power supply voltage.
  • the voltage swing circuit 245 is added, so that the swing amplitude of Vop is V dd ⁇ V_gs, and the swing amplitude of Von is (V dd -V_gs) ⁇ 0, thereby reducing the final stability of the MOS transistor 246 to each node
  • the required swing, reduced charging time, and reduced transmission delay Further, under the condition that the transmission delay is not changed, the charging current of the MOS transistor 217 can also be reduced, and the power consumption of the voltage comparison circuit 231 can be effectively reduced.
  • the data interface of the embodiment of the present invention when used to send signals, the redistribution of charges in the charging capacitor and the parasitic capacitance is adopted, which can not only reduce the power loss caused by the parasitic capacitance in the communication channel, but also effectively reduce Delay.
  • the use of two-line communication is avoided, and manufacturing costs are reduced relative to LVDS.
  • the voltage division circuit can not only effectively reduce the swing amplitude of the nodes in the voltage comparison circuit, so that the voltage comparator can work at a higher rate under the same power consumption, but also can Further reduce power consumption.
  • the voltage dividing circuit 245 shown in FIG. 7 is merely an example, and the specific structure of the circuit is not limited in the embodiment of the present invention.
  • the voltage dividing circuit may be a resistor or diode.
  • MOS transistors can be divided into “N-type” MOS transistors (NMOSFET) and “P-type” MOS transistors (PMOSFET) according to the polarity of the "channel" (working carrier).
  • NMOSFET N-type MOS transistors
  • PMOSFET P-type MOS transistors
  • NMOSFET its source and drain
  • the electrode is connected to the N-type semiconductor, the high voltage is connected to the drain terminal, and the low voltage is connected to the source terminal.
  • the actual current direction is flowing into the drain.
  • PMOSFET its source and drain are connected to a P-type semiconductor, high voltage is used as the source terminal, and low voltage is used as the drain terminal.
  • the actual current direction is the outflow drain. Taking the signal generating circuit 248 shown in FIG.
  • the signal generating circuit 248 includes a MOS tube 246 and a MOS tube 247.
  • the MOS tube 246 is an “N-type” MOS tube and the MOS tube 247 is a “P-type” MOS tube.
  • the embodiment of the present invention is not limited thereto.
  • the MOS tube 246 can be designed as a “P-type” MOS tube, and the MOS tube 247 can be designed as an “N-type” MOS tube, and further, two can be connected at the back end of the signal generating circuit.
  • the inverter can also obtain the third voltage signal in the embodiment of the present invention.
  • the MOS transistor 217 may be moved from the bias circuit 210 to the voltage comparison circuit 231.
  • the MOS transistor 216 shown in FIG. 5 or FIG. 6 is an optional MOS transistor.
  • the data interface including the charge transmitting circuit according to the embodiment of the present invention is described in conjunction with FIG. 1 to FIG. 7 above, and the data interface including only the voltage dividing circuit and the signal generating circuit according to the embodiment of the present invention is exemplified below with reference to FIG. 8. Instructions.
  • FIG. 8 is another example of a data interface 400 according to an embodiment of the present invention.
  • the data interface 400 may include:
  • the drain of the fourth MOS transistor 430 is connected to one end of the voltage dividing circuit 410, the other end of the voltage dividing circuit 410 is used to receive a bias current, and the gate of the fourth MOS transistor 430 is used to receive A bias voltage, a source of the fourth MOS transistor 430 is configured to receive a second voltage signal sent by a transmitting end;
  • the two ends of the voltage dividing circuit 410 are also connected to the first input terminal and the second input terminal of the signal generating circuit 420, respectively.
  • the signal generating circuit 420 is configured to receive voltage signals from the two ends of the voltage dividing circuit 410, and A voltage signal across the voltage dividing circuit 410 generates a fourth voltage signal.
  • the data interface 400 further includes:
  • a third inverter an output terminal of the voltage dividing circuit 410 is connected to an input terminal of the third inverter;
  • the signal generating circuit 420 includes:
  • a fifth MOS transistor and a sixth MOS transistor both ends of the voltage dividing circuit 410 are respectively connected to the gate of the fifth MOS transistor and the gate of the sixth MOS transistor, and the fifth MOS transistor passes through the sixth MOS transistor; Connected to ground, the drain of the sixth MOS transistor is used to output the fourth voltage signal.
  • the voltage dividing circuit 410 includes:
  • a seventh MOS tube and a first current source a source of the seventh MOS tube is connected to a gate of the fifth MOS tube, a gate of the seventh MOS tube is connected to a gate of the sixth MOS tube, and the first The gate of the seven MOS tube is connected to the drain of the seventh MOS tube, and the drain of the seventh MOS tube is connected to the ground through the first current source.
  • the data interface 400 further includes:
  • the bias circuit includes: an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a first resistor, and a second current source; the eighth MOS tube passes through the second The current source is connected to the ground; the ninth MOS tube is connected to one end of the first resistor through the tenth MOS tube, and the other end of the first resistor is grounded; the eleventh MOS tube is used to provide the voltage dividing circuit 410 with the Bias current; the eighth MOS tube and the ninth MOS tube form a first current mirror, and the mirror ratio of the eighth MOS tube to the ninth MOS tube is 1: K; the eighth MOS tube and the tenth MOS tube A MOS tube constitutes a second current mirror.
  • the mirror ratio of the eighth MOS tube to the eleventh MOS tube is 1: K * L
  • the mirror ratio of the tenth MOS tube to the fourth MOS tube 430 is 1: L.
  • the bias circuit further includes:
  • the twelfth MOS tube, the gate of the twelfth MOS tube is used to receive a fourth control signal, the drain of the twelfth MOS tube is connected to the gate of the tenth MOS tube, and the tenth The source of the two MOS transistors is connected to ground.
  • the voltage dividing circuit 410 in the embodiment of the present invention may be the voltage dividing circuit 210 shown in FIG. 6 or FIG. 7, and the signal generating circuit 420 may be the signal generating circuit 231 shown in FIG. 6.
  • the fourth MOS transistor 430 may refer to the MOS transistor 242 shown in FIG. 5 or FIG.
  • I will not repeat them here.
  • an embodiment of the present invention further provides a chip or a chip system, where the chip may be configured with at least one of the data interfaces mentioned above, or a first chip and a second chip in the chip system are used.
  • the above relates to at least one data interface connection.

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Abstract

一种数据接口（101）、芯片和芯片系统。该数据接口（101）包括：静电保护电路（103）；电荷发送电路（102），通过所述静电保护电路（103）连接至绑定线（104），所述电荷发送电路（102）包括第一电容，所述电荷发送电路（102）将所述第一电容中的电荷转移至所述静电保护电路（103）的寄生电容和所述绑定线（104）的寄生电容，以生成第一电压信号，并通过所述绑定线（104）输出所述第一电压信号。该数据接口（101）通过采用充电电容与寄生电容中电荷再分配的方式，不仅能够降低通信信道中寄生电容带来的功耗损失，而且能够有效降低时延。此外，通过使用单线通信，避免了使用双线通信，相对于LVDS降低了制造成本。

Description

数据接口、芯片和芯片系统 技术领域
本发明实施例涉及通信领域，并且更具体地，涉及数据接口、芯片和芯片系统。
背景技术
在多芯片(比如多个微控制单元(Microcontroller Unit，MCU))封装中，多个芯片之间不可避免的需要数据通信。
现有技术中，通常采用通用输入输出接口(General Purpose Input Output，GPIO)。然而，由于互联的两个GPIO的寄生电容以及两个GPIO之间走线的寄生电容高达10皮法(pf)量级，因此，在高速传输场景下，会导致寄生电容的功耗过大。
为了解决GPIO功耗过大的问题，可以使用低电压差分信号(Low-Voltage Differential Signalling，LVDS)进行数据通信。但是，LVDS通常需要两组引脚增加了互联成本和制造成本。
发明内容
提供了一种数据接口、芯片和芯片系统。该数据接口不仅能够有效降低寄生电容的功耗，而且能够降低制造成本。
第一方面，提供了一种数据接口，包括：
静电保护电路；
电荷发送电路，通过所述静电保护电路连接至绑定线，所述电荷发送电路包括第一电容，所述电荷发送电路将所述第一电容中的电荷转移至所述静电保护电路的寄生电容和所述绑定线的寄生电容，以生成第一电压信号，并通过所述绑定线输出所述第一电压信号。
本发明实施例的数据接口，通过采用充电电容与寄生电容中电荷再分配的方式，不仅能够降低通信信道中寄生电容带来的功耗损失，而且能够有效降低时延。此外，通过使用单线通信，避免了使用双线通信，相对于LVDS降低了制造成本。
在一些可能的实现方式中，所述电荷发送电路包括：
所述第一电容、第一金属氧化物半导体MOS管、第二MOS管和第三MOS管；
所述第一MOS管的源极用于接收电源电压，所述第一MOS管的漏极通过所述第一电容连接至地，所述第一MOS管的栅极用于接收第一控制信号，所述第一MOS管的漏极与所述第二MOS管的源极相连，所述第二MOS管的漏极用于输出所述第一电压信号，所述第二MOS管的栅极用于接收所述第一控制信号，所述第二MOS管的漏极通过所述第三MOS管连接至地，所述第三MOS管的栅极用于接收第二控制信号。
在一些可能的实现方式中，所述第一控制信号和所述第二控制信号均是根据第三控制信号生成的控制信号，所述第三控制信号的电压值为第一电平时，所述第二MOS管导通，所述第一MOS管和所述第三MOS管关断；所述第三控制信号的电压值为第二电平时，所述第二MOS管关断，所述第一MOS管和所述第三MOS管导通，所述第一电平大于所述第二电平。
在一些可能的实现方式中，所述数据接口还包括：
信号接收转换电路；
所述信号接收转换电路通过所述静电保护电路连接至所述绑定线；
所述信号接收转换电路用于通过所述绑定线接收第二电压信号，并将所述第二电压信号转换为第三电压信号。
在一些可能的实现方式中，所述信号接收转换电路包括：
偏置电路和至少一个电压比较电路；
所述偏置电路用于为所述至少一个电压比较电路提供偏置电流和偏置电压信号；
所述电压比较电路用于接收所述第二电压信号和所述偏置电压信号，并根据所述第二电压信号和所述偏置电压信号的比较结果生成所述第三电压信号。
在一些可能的实现方式中，所述电压比较电路包括：
第四MOS管；
所述第四MOS管的漏极用于接收所述偏置电路输出的偏置电流，所述第四MOS管的栅极用于接收所述偏置电压信号，所述第四MOS管的源极用于接收所述第二电压信号。
在一些可能的实现方式中，所述电压比较电路还包括：
第一反相器和第二反相器；
所述第四MOS管的漏极通过所述第一反相器连接至所述第二反相器；
其中，所述第二反相器的输出信号为所述第三电压信号。
在一些可能的实现方式中，所述电压比较电路还包括：
分压电路和信号生成电路；
所述第四MOS管的漏极与所述分压电路的一端相连，所述分压电路的另一端用于接收偏置电流；
所述分压电路的两端分别与所述信号生成电路的第一输入端和第二输入端相连；
所述信号生成电路用于接收所述分压电路的两端的电压信号，并根据所述分压电路的两端的电压信号生成第四电压信号。
在一些可能的实现方式中，所述电压比较电路还包括：
第三反相器；
所述信号生成电路的输出端与所述第三反相器的输入端相连，所述第三反相器的输出端输出的信号为所述第三电压信号。
在一些可能的实现方式中，所述信号生成电路包括：
第五MOS管和第六MOS管；
所述分压电路的两端分别与所述第五MOS管的栅极和所述第六MOS管的栅极相连，所述第五MOS管通过所述第六MOS管连接至地，所述第六MOS管的漏极用于输出所述第四电压信号。
在一些可能的实现方式中，所述分压电路包括：
第七MOS管和第一电流源；
所述第七MOS管的源极与所述第五MOS管的栅极相连，所述第七MOS管的栅极与所述第六MOS管的栅极相连，所述第七MOS管的栅极与所述第七MOS管的漏极相连，所述第七MOS管的漏极通过所述第一电流源连接至地。
在一些可能的实现方式中，所述偏置电路包括：
第八MOS管、第九MOS管、第十MOS管、第十一MOS管、第一电阻和第二电流源；
所述第八MOS管通过所述第二电流源连接至地；
所述第九MOS管通过所述第十MOS管连接至所述第一电阻的一端， 所述第一电阻的另一端接地；
所述第十一MOS管用于为所述电压比较电路提供偏置电流；
所述第八MOS管与所述第九MOS管组成第一电流镜，且所述第八MOS管与所述第九MOS管的镜像比率为1：K；
所述第八MOS管与所述第十一MOS管组成第二电流镜，所述第八MOS管与所述第十一MOS管的镜像比率为1：K*L，且所述第十MOS管与所述第四MOS管的镜像比率为1：L，其中，K＞1，L＞1。
在一些可能的实现方式中，所述偏置电路还包括：
第十二MOS管，所述第十二MOS管的栅极用于接收第四控制信号，所述第十二MOS管的漏极与所述第十MOS管的栅极相连，所述第十二MOS管的源极连接至地。
第二方面，提供了一种数据接口，包括：
第四MOS管、分压电路和信号生成电路；
所述第四MOS管的漏极与所述分压电路的一端相连，所述分压电路的另一端用于接收偏置电流，所述第四MOS管的栅极用于接收偏置电压，所述第四MOS管的源极用于接收发送端发送的第二电压信号；
所述分压电路的两端分别与所述信号生成电路的第一输入端和第二输入端相连；
所述信号生成电路用于接收所述分压电路的两端的电压信号，并根据所述分压电路的两端的电压信号生成第四电压信号。
在一些可能的实现方式中，所述数据接口还包括：
第三反相器；
所述信号生成电路的输出端与所述第三反相器的输入端相连。
在一些可能的实现方式中，所述信号生成电路包括：
第五MOS管和第六MOS管；
所述分压电路的两端分别与所述第五MOS管的栅极和所述第六MOS管的栅极相连，所述第五MOS管通过所述第六MOS管连接至地，所述第六MOS管的漏极用于输出所述第四电压信号。
在一些可能的实现方式中，所述分压电路包括：
第七MOS管和第一电流源；
所述第七MOS管的源极与所述第五MOS管的栅极相连，所述第七MOS 管的栅极与所述第六MOS管的栅极相连，所述第七MOS管的栅极与所述第七MOS管的漏极相连，所述第七MOS管的漏极通过所述第一电流源连接至地。
在一些可能的实现方式中，所述数据接口还包括：
所述偏置电路，所述偏置电路包括：
第八MOS管、第九MOS管、第十MOS管、第十一MOS管、第一电阻和第二电流源；
所述第八MOS管通过所述第二电流源连接至地；
所述第九MOS管通过所述第十MOS管连接至所述第一电阻的一端，所述第一电阻的另一端接地；
所述第十一MOS管用于为所述分压电路提供所述偏置电流；
所述第八MOS管与所述第九MOS管组成第一电流镜，且所述第八MOS管与所述第九MOS管的镜像比率为1：K；
所述第八MOS管与所述第十一MOS管组成第二电流镜，所述第八MOS管与所述第十一MOS管的镜像比率为1：K*L，且所述第十MOS管与所述第四MOS管的镜像比率为1：L。
在一些可能的实现方式中，所述偏置电路还包括：
第十二MOS管，所述第十二MOS管的栅极用于接收第四控制信号，所述第十二MOS管的漏极与所述第十MOS管的栅极相连，所述第十二MOS管的源极连接至地。
第三方面，提供了一种芯片，包括：
第一方面所述的数据接口，和/或，第二方面所述的数据接口。
第四方面，提供了一种芯片系统，包括：
多个芯片，所述多个芯片中的第一芯片和第二芯片之间采用以下至少一种数据接口连接：
第一方面所述的数据接口，和第二方面所述的数据接口。
附图说明
图1是本发明实施例的数据接口的示例。
图2是本发明实施例的数据接口应用到发送端(第一数据接口)和接收端(第二数据接口)时的接口连接关系的示意性框图。
图3是本发明实施例数据接口所包含的电荷发送电路的示例。
图4是本发明实施例数据接口所包含的信号接收转换电路的方框示意图，其中，信号接收转换电路包括偏置电路和电压比较电路。
图5是本发明实施例的数据接口所包含的信号接收转换电路的示例图。
图6是本发明实施例的数据接口所包含的信号接收转换电路的另一示例图。
图7是本发明实施例的数据接口包含的分压电路的示例。
图8是本发明实施例的数据接口的另一示例。
具体实施方式
下面将结合附图，对本发明实施例中的技术方案进行描述。应理解，本发明实施例的数据接口、芯片和芯片系统适用于任何需要数据通信的场合，尤其适用于高速低功耗通信互联的场合。其中，数据接口尤其适用于芯片之间的数据通信。例如，芯片系统的内部芯片之间的数据通信。
本发明实施例中，考虑到多芯片间通信信道不对外可见，而用于传输信号的载体为电压或者电流时，会导致通信信道中寄生电容过大。
为了解决上述问题，本发明实施例中提供了一种新的数据接口，该数据接口采用电荷作为传输信号的载体，通过将发送电路中电容的电荷转移至寄生电容以生成发送信号，进而降低数据接口的功耗。
图1是本发明实施例的数据接口(单端)的示意性框图。
如图1所示，该数据接口101可以包括：电荷发送电路102和静电保护电路103；该电荷发送电路102通过该静电保护电路103连接至绑定线(binding wire)104；该电荷发送电路102用于将该电荷发送电路102中第一电容中的电荷转移至该静电保护电路103的寄生电容和该绑定线104的寄生电容，以生成并通过绑定线104输出第一电压信号。
可选地，本发明实施例中，静电保护电路103旨在用于防止静电对器件的破坏，尤其在包括多个芯片的芯片系统中，由于通信信道并不是暴露在整个芯片系统的外部，因此，该静电保护(ESD)电路只需要保证能满足充电器件模型(Charged Device Model，CDM)的需求即可，其目的是为了降低寄生电容。此外，绑定线为芯片互连之间必要的连接线。
本发明实施例的数据接口，通过采用充电电容与寄生电容中电荷再分配 的方式，不仅能够降低通信信道中寄生电容带来的功耗损失，而且能够有效降低时延。此外，通过使用单线通信，避免了使用双线通信，相对于LVDS降低了制造成本。
应当理解，图1为数据接口101仅包括发送电路的示例。在其它可替代实施例中，数据接口还可以包括接收电路。例如，作为示例，该数据接口还可以包括信号接收转换电路，该信号接收转换电路用于接收对端数据接口发送的第二电压信号，并对该第二电压信号进行转换处理。
图2是本发明实施例的第一数据接口和第二数据接口的连接关系的示意性框图。第一数据接口和第二数据接口可分别视为本端接口和对端接口，或者分别作为发送端接口和接收端接口。
如图2所示，第一数据接口110可以包括第一电荷发送电路111和第一信号接收转换电路115，该第一电荷发送电路111通过第一开关112连接至第一静电保护电路113的一端，该第一静电保护电路113的另一端通过绑定线120连接至第二数据接口130，同时，该第一信号接收转换电路115通过第二开关114连接至第一静电保护电路113。相应的，第二数据接口130可以包括第二电荷发送电路135和第二信号接收转换电路131，该第二电荷发送电路135通过第三开关134连接至第二静电保护电路133的一端，该第二静电保护电路133的另一端通过绑定线120连接至第一数据接口110，同时，该第二信号接收转换电路131通过第四开关132连接至第二静电保护电路133。可以看出，图2所示的第一数据接口110和第二数据接口130都可以包括一套功能相同的接收电路(即信号接收转换电路)和发送电路(即电荷发送电路)。
在实际操作中，第一数据接口110和第二数据接口130可以通过第一开关112、第二开关114、第四开关132和第三开关134实现电荷发送电路和信号接收转换电路之间的切换。作为一种可选地实现方式，如图2所示，第一开关112和第四开关132可以通过控制信号en1控制，第二开关114和第三开关134可以通过控制信号en2控制。在具体切换过程中，当en1＝0且en2＝1时，第一数据接口110可以作为发射端，第二数据接口130作为接收端；当en1＝1且en2＝0时，第一数据接口110可以作为接收端，第二数据接口130作为发射端，从而实现半双工通信功能。
具体地，如图2所示，第一数据接口110作为发射端且第二数据接口130 作为接收端时，第一数据接口110生成电压信号Vo1，并通过绑定线120发送给第二数据接口130。第一数据接口110作为接收端且第二数据接口130作为发射端时，第二数据接口130生成电压信号Vo2，并通过绑定线120发送给第一数据接口110。
这里需要指出的是，图2所示的数据接口的连接关系仅为示例，在其它可替代实施例中，如果数据接口仅仅用于单工通信时，上述四个开关为可选开关。应当理解，图2所示的四个开关并非一定是真实的物理开关，例如，可以是通过复用电荷发送电路和/或信号接收转换电路中的信号，实现电荷发送电路和信号接收转换电路之间的切换。还应当理解，虽然，图2所示的第一数据接口110和第二数据接口130都可以包括一套功能相同的信号接收转换电路和电荷发送电路，但是，其信号接收转换电路和电荷发送电路的具体实现电路和/或使用工艺可以不同。
图3是本发明实施例的电荷发送电路的示例，下面对本发明实施例中的电荷发送电路进行示例性说明：
如图3所示，该电荷发送电路可以包括：
电容143、金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET，简称MOS管)141、MOS管142和MOS管144；其中，该MOS管141的源极用于接收电源电压，该MOS管141的漏极通过该电容143连接至地，该MOS管141的栅极用于接收第一控制信号，该MOS管141的漏极与该MOS管142的源极相连，该MOS管142的栅极用于接收该第一控制信号，该MOS管142的漏极用于输出该第一电压信号Vo x，该MOS管142的漏极通过该MOS管144连接至地，该MOS管144的栅极用于接收第二控制信号，该MOS管144的源极接地。
在实际操作中，该第一控制信号和该第二控制信号可以是基于第三控制信号生成的控制信号。
可选地，在本申请的一些实施例中，该第三控制信号的电压值为第一电平时，该MOS管142导通，该MOS管141和该MOS管144关断；该第三控制信号的电压值为第二电平时，该MOS管142关断，该MOS管141和该MOS管144导通，该第一电平大于该第二电平。
可选地，在本申请的一些实施例中，该第一控制信号和该第二控制信号可以是基于该第三控制信号和以下控制信号中的至少一个生成的控制信号： 图2所示的en1(用于控制第一开关112和第四开关132)和图2所示的en2(用于控制第二开关114和第三开关134)。
在图3中，该第一控制信号为第三控制信号Di和en x生成的控制信号，该第一控制信号en x·Di表示将控制信号en x和第三控制信号Di通过“逻辑与”连接后形成的逻辑表达式。该第二控制信号en x·_Di表示将控制信号en x和第三控制信号Di的非，通过“逻辑与”连接后形成的逻辑表达式。
其中，控制信号en x可以是en1，也可以是en2，Vo x可以是Vo1，可以是Vo2。结合图2来说，当控制信号en1＝1时，第一数据接口110可以作为发射端，第二数据接口130作为接收端时，即图3所示的电路为第一数据接口110中的第一电荷发送电路111，该第一电荷发送电路111可以用于生成电压信号Vo1；当控制信号en2＝1时，第一数据接口110可以作为接收端，且第二数据接口130作为发射端时，即图3所述的电路为第二数据接口130中的第二电荷发送电路135，该第二电荷发送电路135可以用于生成电压信号Vo2。
下面以图3所示的电路为第一数据接口110中的第一电荷发送电路111(即en x为en1，Vo x为Vo1)为例对图3所示的电路的工作原理进行说明。
当en1＝0时，本发明实施例中，可以使得MOS管141导通，进而使得电容143预充电至电源电压Vdd，并控制MOS管142和MOS管144断开，此时，Vo1输出高阻，电荷发送电路处于失能状态。
当en1＝1时，若Di＝1，则en x·Di＝1，且en x·_Di＝0，此时，MOS管141和MOS管144断开，MOS管142导通，该电路进入使能状态，此时预充电后的电容143上的电荷倾倒在静电保护和绑定线的寄生电容上，通过调节电容143可以得到不同的电压值，如下公式所示：
Figure PCTCN2018100290-appb-000001
若Di＝0，则en x·Di＝0，且en x·_Di＝0，此时，MOS管141和MOS管144导通，MOS管142断开，电容143预充电到电源电压Vdd，Vo1的电压被拉到地，其以工作频率F全速翻转的功耗为：
Figure PCTCN2018100290-appb-000002
此外，GPIO的以工作频率F全速翻转的功耗，如下：
I P,GPIO＝(C P1+C P2)*V dd*F  (3)
通过对比公式(2)和公式(3)可以看出，本申请提供的数据接口的功耗会随电容143减小而减小。
本发明实施例中涉及的信号接收转换电路可以通过该静电保护电路连接至该绑定线；该信号接收转换电路用于接收第二电压信号，并将该第二电压信号转换为第三电压信号。
可选地，该信号接收转换电路可以包括：
偏置电路和至少一个电压比较电路；该偏置电路用于为这至少一个电压比较电路提供偏置电流和偏置电压信号，该电压比较电路用于接收该第二电压信号和该偏置电压信号，并根据该第二电压信号和该偏置电压信号的比较结果生成该第三电压信号，其中，该第三电压信号可以是芯片或者处理器直接使用的信号。
例如，如图4所示，该信号接收转换电路可以包括偏置电路210和n个电压比较电路(如图所示的第一电压比较电路231、第二电压比较电路232以及第n电压比较电路233)。
结合图2来说，本申请实施例中的数据接口110作为接收端时，可以用于包括多个第一信号接收转换电路115，且该多个第一信号接收转换电路115中的每个第一信号接收转换电路115可以包括一个偏置电路210和n个电压比较电路(如图所示的第一电压比较电路231、第二电压比较电路232以及第n电压比较电路233)。其中，该n个电压比较电路中的每一个电压比较电路分别用于接收一个该第二电压信号。换句话说，该n个电压比较电路可以用于接收n个第二电压信号。该n个第二电压信号可以包括如图4所示的Vo 21，Vo 22直至Vo 2n。
例如，以图3所示的第一电压比较电路为例，所述数据接口110接收到的第二电压信号为Vo 21时，图3所示的第一电压比较电路231用于接收该第二电压信号Vo 21和该偏置电压信号，并根据该第二电压信号Vo11和该偏置电压信号的比较结果生成并输出第三电压信号，即芯片或者处理器可以直接使用的信号。
本发明实施例中，可以为多个电压比较电路配置一个偏置电路，也可以为每个电压比较电路配置一个偏置电路，采用为多个电压比较电路配置一个偏置电路的配置方式，在并行传输的场景下，可以有效降低功耗。需要注意的是，针对为多个电压比较电路配置一个偏置电路的配置方式，该多个电压 比较电路的电路结构和/或使用工艺可以不同。
图5和图6是本发明实施例的信号接收转换电路的示例。下面给出单个偏置电路对应单个电压比较电路(如图4所示的电压比较电路231)的实施方式。由于图5和图6中的部分器件类似，因此，为了便于说明，采用相同的附图标记表示相同的部件。
如图5或图6所示，该信号接收转换电路可以包括偏置电路210和电压比较电路231。
应当理解，本发明实施例中的偏置电路旨在为电压比较电路提供偏置电流和偏置电压信号。本发明实施例对偏置电路的具体电路结构和使用工艺不做限定。
作为示例，如图5或图6所示，该偏置电路210可以包括：
MOS管212、MOS管213、MOS管214、MOS管217、电阻215和电流源211；该MOS管212通过该电流源211连接至地；该MOS管213通过该MOS管214连接至该电阻215的一端，该电阻215的另一端接地；该MOS管217用于为该电压比较电路231提供偏置电流；该MOS管212与该MOS管213组成第一电流镜，且该MOS管212与该MOS管213的镜像比率为1：K；该MOS管212与该MOS管217组成第二电流镜，该MOS管212与该MOS管217的镜像比率为1：K*L，且该MOS管214与该MOS管242的镜像比率为1：L，其中，K＞1，L＞1。其中，电阻215用于生成偏置电压信号。
可选地，如图5或图6所示，该偏置电路210可以包括：
MOS管216，该MOS管216的栅极用于接收第四控制信号，该第四控制信号可以是en x，进一步地，该en x可以是图2所示的en1(用于控制第一开关112和第四开关132)和图2所示的en2(用于控制第二开关114和第三开关134)。该MOS管216的漏极与MOS214的栅极连接，该MOS管216的源极连接至地。
本申请实施例中，通过控制该MOS管216的导通或者关断，可以有效节省数据接口处于未工作状态时的电量损耗。
此外，如图5或图6所示，该电压比较电路231可以包括：
MOS管242；该MOS管242的漏极用于接收该偏置电路210输出的偏置电流，该MOS管242的栅极用于接收该偏置电压信号，该MOS管242 的源极用于接收该第二电压信号。
进一步地，如图5所示，该电压比较电路231还可以包括：
反相器243和反相器244；该MOS管242的漏极通过该反相器243连接至该反相器244；此时，该反相器244的输出信号为该第三电压信号。
在实际工作中，电流源211为整个信号接收转换电路提供一个确定的参考电流，该MOS管212与该MOS管213组成第一电流镜，将电流源211的电流镜像到MOS管213、MOS管214和电阻215所在的支路，假设MOS管212与该MOS管213的镜像比率为1：K，则电阻215上的压降根据公式(4)可计算出：
V r＝K*I b*R    (4)
在电压比较电路231中，MOS管212与MOS管217同样是构成电流镜，假设该MOS管212与该MOS管217组成第二电流镜，且该MOS管212与该MOS管217的镜像比率为1：K*L，则该MOS管217在饱和状态下流过的电流为K*L*I b。此外，MOS管242为该电压比较电路231中的放大管，若将该MOS管214与该MOS管242的镜像比率设计为1：L，则当第二电压信号(Vox)的电压等于偏置电压信号(Vr)的电压时，该MOS管217与该MOS管242的电流刚好一致，也即是说，Vox＝Vr的点即为该电压比较电路231的翻转阈值点。换句话说，当Vox>Vr时该MOS管242的漏极输出1，当Vox<Vr时该MOS管242的漏极输出0。
结合图5来说，该MOS管242的漏极输出的信号经过反相器243和反相器244进行放大后，能够输出一个稳定标准的逻辑电平(0或者1)。
但是，通过分析可以发现：在图5所示的电压比较电路231中，通常第二电压信号(Vox)的摆幅只有几百mV的量级，但是电压比较电路231的供电电压相对会高许多，通常在几V的量级，因此，该MOS管242的漏端结点需要从地摆到电源电压，全靠该MOS管217的充电结点的寄生电容。若通过增加该MOS管217的宽长比来增加充电的电流，则会导致电压比较电路231的功耗急剧上升。
为了解决这个问题，本发明实施例对图5所示的电压比较电路231进行了简单的变形，形成了如图6所示的电压比较电路231。
如图6所示，该电压比较电路231还可以包括：
分压电路245和信号生成电路248；该MOS管242的漏极与该分压电 路245的一端相连，该分压电路245的另一端连接MOS管217；该分压电路245的两端还分别与该信号生成电路248的第一输入端和第二输入端相连；该信号生成电路248用于接收该分压电路245的两端的电压信号，并根据该分压电路245的两端的电压信号生成第四电压信号。
进一步地，如图6所示，该电压比较电路231还可以包括：
反相器249；该信号生成电路248的输出端与该反相器249的输入端相连，此时，该反相器249的输出端输出的信号为该第三电压信号。
针对电压比较电路231，相对于图5所示的电路结构，在图6中，将反相器243中两个MOS管的栅极分别作为一个输入端，形成信号生成电路248，并且在该MOS管217和该MOS管242之间设计了分压电路245。
作为示例，如图6所示，该信号生成电路248可以包括：
MOS管246和MOS管247；该分压电路245的两端分别与该MOS管246的栅极和该MOS管247的栅极相连，该MOS管246通过该MOS管247连接至地，该MOS管247的漏极用于输出该第四电压信号。
作为一种低成本设计的示例，如图7所示，该分压电路245可以包括：
MOS管311和电流源312；该MOS管311的源极与该MOS管246的栅极相连，该MOS管311的栅极与该MOS管247的栅极相连，该MOS管311的栅极与该MOS管311的漏极相连，该MOS管311的漏极通过该电流源312连接至地。
下面结合图6对该电压比较电路231的工作过程进行说明：
在实际工作中，当Vox>Vr时，MOS管242进入截止区，MOS管217将分压电路245两端的电压(如图6所示的Vop和Von)上拉，直至Vop升至电源电压，令MOS管217进入线性区。由于图7所述的电流源312的电流远小于图6所述的电流源211的电流，因此，Vop近似等于电源电压，进而确保MOS管246能够正常关闭。此外，由于MOS管311和电流源312的共同作用，使得分压电路245有一个Vgs的压降，从而使得Von总是不会上升到电源电压，此时，由于Von足够高，能够保证MOS管247的导通，进而有输出0，经反相器249后输出1，即Do输出为1。相应的，当Vox<Vr时，其电压比较电路231的工作过程与上述正好相反，为避免重复，此处不再赘述。
通过以上分析可以看出，由于加入了分压电路245，使得Vop的摆动幅 度为V dd～V_gs，Von的摆动幅度为(V dd-V_gs)～0，从而降低MOS管246对各节点最终稳定所需要的摆幅，降低的充电时间，减小了传输延迟。进一步地，在保证传输延迟不变的情况下，还可以减小MOS管217的充电电流，进而能够有效降低该电压比较电路231的功耗。
此外，由于Vop的摆动幅度为V dd～V_gs，Von的摆动幅度为(V dd-V_gs)～0，能够避免MOS管246和MOS管247同时导通，进一步降低了该电压比较电路231的功耗。
综上所述，本发明实施例的数据接口用于发送信号时，采用充电电容与寄生电容中电荷再分配的方式，不仅能够降低通信信道中寄生电容带来的功耗损失，而且能够有效降低时延。此外，通过使用单线通信，避免了使用双线通信，相对于LVDS降低了制造成本。另外，本发明实施例的数据接口用于接收信号时，通过分压电路不仅能够有效降低电压比较电路中节点的摆动幅度，使得同样功耗下电压比较器可以工作到更高的速率，而且能够进一步降低功耗。
应理解，图7所示的分压电路245仅为示例，本发明实施例对其电路的具体结构不做限定，例如，在一种可实现的方式中，该分压电路可以是一个电阻或者二极管。
还应理解，以上结合图1至图7详细描述了本申请的优选实施方式，但是，本申请并不限于上述实施方式中的具体细节，在本申请的技术构思范围内，可以对本申请的技术方案进行多种简单变型，这些简单变型均属于本申请的保护范围。
例如，MOS管根据“通道”(工作载流子)的极性不同，可以分为“N型”MOS管(NMOSFET)与“P型”MOS管(PMOSFET)，对于NMOSFET，其源极和漏极接在N型半导体上，接高压为漏端，接低压为源端，实际电流方向为流入漏极。对于PMOSFET，其源极和漏极则接在P型半导体上，接高压为源端，接低压为漏端，实际电流方向为流出漏极。以图6所示的信号生成电路248为例，该信号生成电路248包括MOS管246和MOS管247，其中，MOS管246为“N型”MOS管，MOS管247为“P型”MOS管。但本发明实施例不限于此。例如，在其它可替代实施例中，可以将MOS管246设计为“P型”MOS管，将MOS管247设计为“N型”MOS管，并进一步地，在信号生成电路后端连接两个反相器，也可以得到本发明实施例中 的第三电压信号。
另外，需要说明的是，在上述具体实施方式中所描述的各个具体技术特征，在不矛盾的情况下，可以通过任何合适的方式进行组合，为了避免不必要的重复，本申请对各种可能的组合方式不再另行说明。此外，本申请的各种不同的实施方式之间也可以进行任意组合，只要其不违背本申请的思想，其同样应当视为本申请所公开的内容。
例如，图5或图6中，也可以将MOS管217从偏置电路210中移至电压比较电路231。
又例如，图5或图6中所示的MOS管216为可选MOS管。
上文结合图1至图7，侧重描述了本发明实施例的包括电荷发送电路的数据接口，下文结合图8，对本发明实施例的仅包括分压电路和信号生成电路的数据接口进行示例性说明。
图8是本发明实施例的数据接口400的另一示例。
如图8所示，该数据接口400可以包括：
分压电路410和信号生成电路420；
所述第四MOS管430的漏极与所述分压电路410的一端相连，所述分压电路410的另一端用于接收偏置电流，所述第四MOS管430的栅极用于接收偏置电压，所述第四MOS管430的源极用于接收发送端发送的第二电压信号；
该分压电路410的两端还分别与该信号生成电路420的第一输入端和第二输入端相连；该信号生成电路420用于接收该分压电路410的两端的电压信号，并根据该分压电路410的两端的电压信号生成第四电压信号。
可选地，该数据接口400还包括：
第三反相器；该分压电路410的输出端与该第三反相器的输入端相连。
可选地，该信号生成电路420包括：
第五MOS管和第六MOS管；该分压电路410的两端分别与该第五MOS管的栅极和该第六MOS管的栅极相连，该第五MOS管通过该第六MOS管连接至地，该第六MOS管的漏极用于输出该第四电压信号。
可选地，该分压电路410包括：
第七MOS管和第一电流源；该第七MOS管的源极与该第五MOS管的栅极相连，该第七MOS管的栅极与该第六MOS管的栅极相连，该第七MOS 管的栅极与该第七MOS管的漏极相连，该第七MOS管的漏极通过该第一电流源连接至地。
可选地，该数据接口400还包括：
该偏置电路，该偏置电路包括：第八MOS管、第九MOS管、第十MOS管、第十一MOS管、第一电阻和第二电流源；该第八MOS管通过该第二电流源连接至地；该第九MOS管通过该第十MOS管连接至该第一电阻的一端，该第一电阻的另一端接地；该第十一MOS管用于为该分压电路410提供该偏置电流；该第八MOS管与该第九MOS管组成第一电流镜，且该第八MOS管与该第九MOS管的镜像比率为1：K；该第八MOS管与该第十一MOS管组成第二电流镜，该第八MOS管与该第十一MOS管的镜像比率为1：K*L，且该第十MOS管与该第四MOS管430的镜像比率为1：L。
在一些可能的实现方式中，所述偏置电路还包括：
第十二MOS管，所述第十二MOS管的栅极用于接收第四控制信号，所述第十二MOS管的漏极与所述第十MOS管的栅极相连，所述第十二MOS管的源极连接至地。
应理解，本发明实施例中的分压电路410可以是图6或图7所示的分压电路210，信号生成电路420可以是图6所示的信号生成电路231，该分压电路410的电路结构和信号生成电路420的电路结构可以参考图6和图7所示的电路结构，第四MOS管430可以参考图5或图6所示的MOS管242。为了简洁，在此不再赘述。
此外，本发明实施例中还提供了一种芯片或者芯片系统，其中，该芯片可以配置有上述涉及的至少一种数据接口，或者，该芯片系统中的第一芯片和第二芯片之间采用上述涉及至少一种的数据接口连接。
最后，需要说明的是，在本发明实施例和所附权利要求书中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本发明实施例。例如，在本发明实施例和所附权利要求书中所使用的单数形式的“上述”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的部件，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所 描述的功能，但是这种实现不应认为超出本发明实施例的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的装置和部件，可以是或者也可以不是物理上分开的。可以根据实际的需要选择其中的部分或者全部部件来实现本发明实施例的目的。
以上内容，仅为本发明实施例的具体实施方式，但本发明实施例的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明实施例揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明实施例的保护范围之内。因此，本发明实施例的保护范围应以权利要求的保护范围为准。

Claims (21)

  1. 一种数据接口，其特征在于，包括：
    静电保护电路；
    电荷发送电路，通过所述静电保护电路连接至绑定线，所述电荷发送电路包括第一电容，所述电荷发送电路将所述第一电容中的电荷转移至所述静电保护电路的寄生电容和所述绑定线的寄生电容，以生成第一电压信号，并通过所述绑定线输出所述第一电压信号。
  2. 根据权利要求1所述的数据接口，其特征在于，所述电荷发送电路还包括：
    第一MOS管、第二MOS管和第三MOS管；
    所述第一MOS管的源极用于接收电源电压，所述第一MOS管的漏极通过所述第一电容连接至地，所述第一MOS管的栅极用于接收第一控制信号，所述第一MOS管的漏极与所述第二MOS管的源极相连，所述第二MOS管的漏极用于输出所述第一电压信号，所述第二MOS管的栅极用于接收所述第一控制信号，所述第二MOS管的漏极通过所述第三MOS管连接至地，所述第三MOS管的栅极用于接收第二控制信号。
  3. 根据权利要求2所述的数据接口，其特征在于，所述第一控制信号和所述第二控制信号均是根据第三控制信号生成的控制信号，所述第三控制信号的电压值为第一电平时，所述第二MOS管导通，所述第一MOS管和所述第三MOS管关断；所述第三控制信号的电压值为第二电平时，所述第二MOS管关断，所述第一MOS管和所述第三MOS管导通，所述第一电平大于所述第二电平。
  4. 根据权利要求1至3中任一项所述的数据接口，其特征在于，所述数据接口还包括：
    信号接收转换电路；
    所述信号接收转换电路通过所述静电保护电路连接至所述绑定线；
    所述信号接收转换电路用于通过所述绑定线接收发送端发送的第二电压信号，并将所述第二电压信号转换为第三电压信号。
  5. 根据权利要求4所述的数据接口，其特征在于，所述信号接收转换电路包括：
    偏置电路和至少一个电压比较电路；
    所述偏置电路用于为所述至少一个电压比较电路提供偏置电流和偏置电压信号；
    所述电压比较电路用于接收所述第二电压信号和所述偏置电压信号，并根据所述第二电压信号和所述偏置电压信号的比较结果生成所述第三电压信号。
  6. 根据权利要求5所述的数据接口，其特征在于，所述电压比较电路包括：
    第四MOS管；
    所述第四MOS管的漏极用于接收所述偏置电路输出的偏置电流，所述第四MOS管的栅极用于接收所述偏置电压信号，所述第四MOS管的源极用于接收所述第二电压信号。
  7. 根据权利要求6所述的数据接口，其特征在于，所述电压比较电路还包括：
    第一反相器和第二反相器；
    所述第四MOS管的漏极通过所述第一反相器连接至所述第二反相器；
    其中，所述第二反相器的输出信号为所述第三电压信号。
  8. 根据权利要求6所述的数据接口，其特征在于，所述电压比较电路还包括：
    分压电路和信号生成电路；
    所述第四MOS管的漏极与所述分压电路的一端相连，所述分压电路的另一端用于接收偏置电流；
    所述分压电路的两端还分别与所述信号生成电路的第一输入端和第二输入端相连；
    所述信号生成电路用于接收所述分压电路的两端的电压信号，并根据所述分压电路的两端的电压信号生成第四电压信号。
  9. 根据权利要求8所述的数据接口，其特征在于，所述电压比较电路还包括：
    第三反相器；
    所述信号生成电路的输出端与所述第三反相器的输入端相连，所述第三反相器的输出端输出的信号为所述第三电压信号。
  10. 根据权利要求8或9所述的数据接口，其特征在于，所述信号生成电路包括：
    第五MOS管和第六MOS管；
    所述分压电路的两端分别与所述第五MOS管的栅极和所述第六MOS管的栅极相连，所述第五MOS管通过所述第六MOS管连接至地，所述第六MOS管的漏极用于输出所述第四电压信号。
  11. 根据权利要求10所述的数据接口，其特征在于，所述分压电路包括：
    第七MOS管和第一电流源；
    所述第七MOS管的源极与所述第五MOS管的栅极相连，所述第七MOS管的栅极与所述第六MOS管的栅极相连，所述第七MOS管的栅极与所述第七MOS管的漏极相连，所述第七MOS管的漏极通过所述第一电流源连接至地。
  12. 根据权利要求5至11中任一项所述的数据接口，其特征在于，所述偏置电路包括：
    第八MOS管、第九MOS管、第十MOS管、第十一MOS管、第一电阻和第二电流源；
    所述第八MOS管通过所述第二电流源连接至地；
    所述第九MOS管通过所述第十MOS管连接至所述第一电阻的一端，所述第一电阻的另一端接地；
    所述第十一MOS管用于为所述电压比较电路提供偏置电流；
    所述第八MOS管与所述第九MOS管组成第一电流镜，且所述第八MOS管与所述第九MOS管的镜像比率为1：K；
    所述第八MOS管与所述第十一MOS管组成第二电流镜，所述第八MOS管与所述第十一MOS管的镜像比率为1：K*L，且所述第十MOS管与所述第四MOS管的镜像比率为1：L，其中，K＞1，L＞1。
  13. 根据权利要求12所述的数据接口，其特征在于，所述偏置电路还包括：
    第十二MOS管，所述第十二MOS管的栅极用于接收第四控制信号，所述第十二MOS管的漏极与所述第十MOS管的栅极相连，所述第十二MOS管的源极连接至地。
  14. 一种数据接口，其特征在于，包括：
    第四MOS管、分压电路和信号生成电路；
    所述第四MOS管的漏极与所述分压电路的一端相连，所述分压电路的另一端用于接收偏置电流，所述第四MOS管的栅极用于接收偏置电压，所述第四MOS管的源极用于接收发送端发送的第二电压信号；
    所述分压电路的两端分别与所述信号生成电路的第一输入端和第二输入端相连；
    所述信号生成电路用于接收所述分压电路的两端的电压信号，并根据所述分压电路的两端的电压信号生成第四电压信号。
  15. 根据权利要求14所述的数据接口，其特征在于，所述数据接口还包括：
    第三反相器；
    所述信号生成电路的输出端与所述第三反相器的输入端相连。
  16. 根据权利要求14或15所述的数据接口，其特征在于，所述信号生成电路包括：
    第五MOS管和第六MOS管；
    所述分压电路的两端分别与所述第五MOS管的栅极和所述第六MOS管的栅极相连，所述第五MOS管通过所述第六MOS管连接至地，所述第六MOS管的漏极用于输出所述第四电压信号。
  17. 根据权利要求16所述的数据接口，其特征在于，所述分压电路包括：
    第七MOS管和第一电流源；
    所述第七MOS管的源极与所述第五MOS管的栅极相连，所述第七MOS管的栅极与所述第六MOS管的栅极相连，所述第七MOS管的栅极与所述第七MOS管的漏极相连，所述第七MOS管的漏极通过所述第一电流源连接至地。
  18. 根据权利要求14至17中任一项所述的数据接口，其特征在于，所述数据接口还包括：
    所述偏置电路，所述偏置电路包括：
    第八MOS管、第九MOS管、第十MOS管、第十一MOS管、第一电阻和第二电流源；
    所述第八MOS管通过所述第二电流源连接至地；
    所述第九MOS管通过所述第十MOS管连接至所述第一电阻的一端， 所述第一电阻的另一端接地；
    所述第十一MOS管用于为所述分压电路提供所述偏置电流；
    所述第八MOS管与所述第九MOS管组成第一电流镜，且所述第八MOS管与所述第九MOS管的镜像比率为1：K；
    所述第八MOS管与所述第十一MOS管组成第二电流镜，所述第八MOS管与所述第十一MOS管的镜像比率为1：K*L，且所述第十MOS管与所述第四MOS管的镜像比率为1：L。
  19. 根据权利要求18所述的数据接口，其特征在于，所述偏置电路还包括：
    第十二MOS管，所述第十二MOS管的栅极用于接收第四控制信号，所述第十二MOS管的漏极与所述第十MOS管的栅极相连，所述第十二MOS管的源极连接至地。
  20. 一种芯片，其特征在于，包括：
    权利要求1至13中任一项所述的数据接口，和/或，权利要求14至19中任一项所述的数据接口。
  21. 一种芯片系统，其特征在于，包括：
    多个芯片，所述多个芯片中的第一芯片和第二芯片之间采用以下至少一种数据接口连接：
    权利要求1至13中任一项所述的数据接口，和权利要求14至19中任一项所述的数据接口。
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