CN111052610A - 数据接口、芯片和芯片系统 - Google Patents

数据接口、芯片和芯片系统 Download PDF

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Publication number
CN111052610A
CN111052610A CN201880001092.1A CN201880001092A CN111052610A CN 111052610 A CN111052610 A CN 111052610A CN 201880001092 A CN201880001092 A CN 201880001092A CN 111052610 A CN111052610 A CN 111052610A
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CN
China
Prior art keywords
mos tube
circuit
voltage
mos transistor
mos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201880001092.1A
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English (en)
Inventor
张孟文
杨博新
易律凡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Goodix Technology Co Ltd filed Critical Shenzhen Goodix Technology Co Ltd
Publication of CN111052610A publication Critical patent/CN111052610A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018592—Coupling arrangements; Interface arrangements using field effect transistors only with a bidirectional operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05F—STATIC ELECTRICITY; NATURALLY-OCCURRING ELECTRICITY
    • H05F3/00—Carrying-off electrostatic charges
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits

Abstract

提供了一种数据接口(101)、芯片和芯片系统。该数据接口(101)包括：静电保护电路(103)；电荷发送电路(102)，通过所述静电保护电路(103)连接至绑定线(104)，所述电荷发送电路(102)包括第一电容，所述电荷发送电路(102)将所述第一电容中的电荷转移至所述静电保护电路(103)的寄生电容和所述绑定线(104)的寄生电容，以生成第一电压信号，并通过所述绑定线(104)输出所述第一电压信号。该数据接口(101)通过采用充电电容与寄生电容中电荷再分配的方式，不仅能够降低通信信道中寄生电容带来的功耗损失，而且能够有效降低时延。此外，通过使用单线通信，避免了使用双线通信，相对于LVDS降低了制造成本。

Description

PCT国内申请，说明书已公开。

Claims (21)

  1. PCT国内申请，权利要求书已公开。
CN201880001092.1A 2018-08-13 2018-08-13 数据接口、芯片和芯片系统 Pending CN111052610A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/100290 WO2020034069A1 (zh) 2018-08-13 2018-08-13 数据接口、芯片和芯片系统

Publications (1)

Publication Number Publication Date
CN111052610A true CN111052610A (zh) 2020-04-21

Family

ID=69406600

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201880001092.1A Pending CN111052610A (zh) 2018-08-13 2018-08-13 数据接口、芯片和芯片系统

Country Status (4)

Country Link
US (1) US10855279B2 (zh)
EP (1) EP3629479B1 (zh)
CN (1) CN111052610A (zh)
WO (1) WO2020034069A1 (zh)

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US6014410A (en) * 1997-02-03 2000-01-11 Mitsubishi Denki Kabushiki Kaisha Transmission-reception system which transmits and receives data via signal transmission line
US6396329B1 (en) * 1999-10-19 2002-05-28 Rambus, Inc Method and apparatus for receiving high speed signals with low latency
US20120025883A1 (en) * 2010-07-30 2012-02-02 Guangyuan Lin Lock detection circuit and phase-locked loop circuit including the same
US20130195165A1 (en) * 2012-01-26 2013-08-01 Nvidia Corporation Ground referenced single-ended signaling
CN205202469U (zh) * 2015-12-07 2016-05-04 珠海艾派克微电子有限公司 数据接口电路、耗材芯片、耗材盒及成像系统
JP2016174119A (ja) * 2015-03-18 2016-09-29 セイコーエプソン株式会社 回路装置及び電子機器

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JP3693204B2 (ja) * 1996-12-06 2005-09-07 株式会社日立製作所 半導体集積回路装置
US7620121B1 (en) * 2004-12-09 2009-11-17 Xilinx, Inc. DC balance compensation for AC-coupled circuits
JP5607904B2 (ja) 2009-08-31 2014-10-15 パナソニック株式会社 ダイレクトサンプリング回路及び受信機
US20110141829A1 (en) * 2009-12-14 2011-06-16 Ware Frederick A Circuits for Reducing Power Consumption of Memory Components
US9338036B2 (en) * 2012-01-30 2016-05-10 Nvidia Corporation Data-driven charge-pump transmitter for differential signaling
CN103369809A (zh) 2012-04-05 2013-10-23 鸿富锦精密工业（深圳）有限公司 防静电电气设备及其保护电路
JP6010990B2 (ja) * 2012-04-09 2016-10-19 富士通株式会社 伝送システム
CN202759437U (zh) * 2012-06-21 2013-02-27 上海华虹集成电路有限责任公司 用于双界面智能卡的接口电路
US9170980B2 (en) * 2013-03-15 2015-10-27 Nvidia Corporation Ground-referenced single-ended signaling connected graphics processing unit multi-chip module
KR102048254B1 (ko) * 2013-04-11 2020-01-08 에스케이하이닉스 주식회사 데이터 출력 회로 및 그의 구동 방법
CN203205866U (zh) * 2013-04-27 2013-09-18 成都市宏山科技有限公司 一种用于手机接口处的防静电电路
US9917589B2 (en) 2016-02-02 2018-03-13 Samsung Electronics Co., Ltd. Transmitter circuit and receiver circuit for operating under low voltage
JP2018207195A (ja) * 2017-05-31 2018-12-27 セイコーエプソン株式会社 回路装置及び電子機器
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6014410A (en) * 1997-02-03 2000-01-11 Mitsubishi Denki Kabushiki Kaisha Transmission-reception system which transmits and receives data via signal transmission line
US6396329B1 (en) * 1999-10-19 2002-05-28 Rambus, Inc Method and apparatus for receiving high speed signals with low latency
US20120025883A1 (en) * 2010-07-30 2012-02-02 Guangyuan Lin Lock detection circuit and phase-locked loop circuit including the same
US20130195165A1 (en) * 2012-01-26 2013-08-01 Nvidia Corporation Ground referenced single-ended signaling
JP2016174119A (ja) * 2015-03-18 2016-09-29 セイコーエプソン株式会社 回路装置及び電子機器
CN205202469U (zh) * 2015-12-07 2016-05-04 珠海艾派克微电子有限公司 数据接口电路、耗材芯片、耗材盒及成像系统

Also Published As

Publication number Publication date
US20200052701A1 (en) 2020-02-13
EP3629479B1 (en) 2021-03-24
WO2020034069A1 (zh) 2020-02-20
EP3629479A4 (en) 2020-05-27
EP3629479A1 (en) 2020-04-01
US10855279B2 (en) 2020-12-01

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Application publication date: 20200421