WO2019141141A1 - 驱动电路以及串行解串器 - Google Patents

驱动电路以及串行解串器 Download PDF

Info

Publication number
WO2019141141A1
WO2019141141A1 PCT/CN2019/071539 CN2019071539W WO2019141141A1 WO 2019141141 A1 WO2019141141 A1 WO 2019141141A1 CN 2019071539 W CN2019071539 W CN 2019071539W WO 2019141141 A1 WO2019141141 A1 WO 2019141141A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
switch tube
input
output
drive circuit
Prior art date
Application number
PCT/CN2019/071539
Other languages
English (en)
French (fr)
Inventor
陈焱沁
吴春标
刘鹏飞
刘永旺
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2019141141A1 publication Critical patent/WO2019141141A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT

Definitions

  • the present invention relates to the field of electronic power, and in particular to a driving circuit and a serial deserializer.
  • serializer-Deserializer has gradually become an interface circuit in high-speed data communication.
  • the serial deserializer includes a serializer (Serializer) and a deserializer (Deserializer).
  • the serializer and the deserializer are connected by a link, and the serializer sends the serialized data serialized data to the chain.
  • the deserializer receives the serial data on the link and de-serializes the serial data to obtain parallel data.
  • the driver circuit is an important part of the serializer. The driver circuit is used to convert the input digital logic level signal into a signal conforming to the transmission protocol and send it to the link.
  • the driving circuit comprises a pre-driving circuit for receiving the input high-speed digital logic level signal and outputting a pre-drive output signal capable of driving the main driving circuit; the main driving circuit is configured to receive the pre-driving output signal and A signal conforming to the transmission protocol is sent to the link.
  • the current drive circuit is shown in Figure 1.
  • the pre-driver circuit consists of four inverters.
  • the main drive circuit consists of a differential circuit consisting of a pair of resistors (R21 and R22) and a pair of thin-gate switches (N21 and N22), a pair of thick gate switches (N23 and N24) and a current source (N25).
  • the input of the pre-drive circuit is VIN+ and VIN-
  • the output of the pre-drive circuit is VPRE+ and VPRE-
  • the input of the main drive circuit is VPRE+ and VPRE-
  • the output of the main drive circuit is VTX+ and VTX-
  • the supply voltage of the pre-drive circuit For the low voltage power supply VDD_LV, the supply voltage of the main drive circuit is the high voltage power supply VDD_HV.
  • VIN+ is logic high (for example, 3.3V, the corresponding digital signal is “1")
  • VIN- is logic low (for example, 0V, the corresponding digital signal is "0")
  • VPRE+ is logic high (logic high level is VDD_LV)
  • VPRE- is logic low
  • N21 is on
  • N22 Shutdown
  • VTX+ is logic high (logic high level is VDD_HV)
  • VTX- is logic low.
  • VIN+ is logic low
  • VIN- is logic high
  • VPRE+ is logic low
  • VPRE- is logic high
  • VTX+ is logic low
  • VTX+ is logic low
  • VTX- is logic high.
  • the pre-driver circuit uses the low-voltage power supply VDD_LV as the supply voltage to reduce the power consumption of the driver circuit, and the logic high level of the pre-drive circuit output is also VDD_LV. Since the VDD_LV cannot directly drive the thick gate switch, the input of the main drive circuit
  • the switch tube (N21 and N22) uses a thin gate switch tube. Since the output of the main drive circuit needs to meet the high level voltage of the transmission protocol, the supply voltage of the main drive circuit is VDD_HV, in order to avoid the input switch tube of the main drive circuit ( N21 and N22) are broken down by high voltage, and thick gate tubes (N23 and N24) are added to the main drive circuit.
  • the output signal of the pre-drive circuit (VPRE+ or VPRE-) is lower, and the supply voltage of the current source N25 of the main drive circuit is too low, which causes the current source N25 to work close to the linear region, resulting in The operating current of the current source N25 may fluctuate greatly, resulting in a large fluctuation in the output of the main drive circuit.
  • the embodiment of the invention provides a driving circuit and a serial deserializer, which can solve the problem that the output fluctuation of the main driving circuit is large.
  • a first aspect of the embodiments of the present invention provides a driving circuit including a first pre-driving circuit and a main driving circuit, where the driving circuit further includes a selecting circuit, wherein:
  • the first pre-driver circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal
  • the selection circuit includes a first output terminal and a second output terminal
  • the main driving circuit includes a first input terminal and a second output terminal
  • the input end, the first output end of the first pre-drive circuit is connected to the first input end of the main drive circuit and the first output end of the selection circuit
  • the second output end of the first pre-drive circuit is connected to the second input end of the main drive circuit
  • a second output end of the selection circuit when the first input end and the second input end of the first pre-drive circuit input a high-frequency differential signal, the first output end and the second output end of the first pre-drive circuit output a common mode a high-frequency differential signal having a voltage of zero, the first output terminal and the second output terminal of the selection circuit output a first common mode voltage, and the high-frequency differential signal having a common mode voltage of zero and the first common mode voltage are superposed to form a common mode voltage
  • the selection circuit Since the selection circuit is added, the common mode voltage of the high frequency differential signal outputted to the main driving circuit is determined by the selection circuit to be the first common mode voltage, and the first common mode voltage is determined by the selection circuit, and the controllability is high, and the output can be guaranteed.
  • the high-frequency differential signal to the main driving circuit does not have large fluctuations, and the stability of the high-frequency differential signal outputted to the main driving circuit is improved, thereby avoiding the problem that the output fluctuation of the main driving circuit is large.
  • the first pre-drive circuit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first DC blocking capacitor, and a second DC blocking capacitor;
  • the input end of the first inverter is connected to the first input end of the first pre-drive circuit, the output end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter is connected to the first partition a first end of the direct capacitance, a second end of the first DC blocking capacitor is connected to the first output end of the first pre-drive circuit; an input end of the third inverter is connected to the second input end of the first pre-drive circuit, and a third The output end of the inverter is connected to the input end of the fourth inverter, the output end of the fourth inverter is connected to the first end of the second DC blocking capacitor, and the second end of the second DC blocking capacitor is connected to the first pre-drive circuit The second output.
  • An inverter is added to the first pre-driver circuit, and when the input level of the inverter jumps, the output level of the first pre-driver circuit can also quickly jump.
  • the transmission delay of the high frequency differential signal can be reduced.
  • the driving circuit further includes a controller, wherein the power supply voltage of the selection circuit is a high voltage power supply, and the selection circuit includes a first current source, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and the first a switch tube and a second switch tube;
  • the high voltage power supply is connected to the positive end of the first current source, the negative end of the first current source is connected to the first end of the first resistor, and the second end of the first resistor is connected to the first end of the second resistor and the first end of the fourth resistor And a first end of the fifth resistor, the second end of the second resistor is connected to the first end of the third resistor, the second end of the third resistor is grounded; the second end of the fourth resistor is connected to the first end of the first switch tube
  • the second end of the first switch tube is connected to the first output end of the selection circuit;
  • the second end of the fifth switch is connected to the first end of the second switch tube, and the second end of the second switch tube is connected to the second output of the selection circuit
  • the controller includes a first control end and a second control end, the first control end is connected to the control end of the first switch tube, and the second control end is connected to the control end of the second switch tube;
  • the controller controls the first switch tube and the second switch tube to be turned on;
  • the controller controls the first switch tube and the second switch tube to be turned off.
  • the use of a high voltage power supply to power the selected circuit ensures that the selection circuit can output the first common mode voltage required to satisfy the main drive circuit.
  • the driving circuit further includes a second pre-driving circuit
  • the second pre-driving circuit includes a first input end, a second input end, a first output end, and a second output end
  • the selecting circuit further includes a first input end and a first Two input terminals
  • the first input end of the second pre-drive circuit is connected to the first input end of the first pre-drive circuit
  • the second input end of the second pre-drive circuit is connected to the second input end of the first pre-drive circuit
  • the first of the second pre-drive circuit The output end is connected to the first input end of the selection circuit, and the second output end of the second pre-drive circuit is connected to the second input end of the selection circuit;
  • the first output end and the second output end of the second pre-drive circuit When the first input end and the second input end of the second pre-drive circuit input the low frequency differential signal, the first output end and the second output end of the second pre-drive circuit output a low frequency differential control signal, and the low frequency differential control signal is used for controlling The first output end and the second output end of the selection circuit output a first low frequency differential signal for driving the main drive circuit.
  • the selection circuit can output a stable signal under the control of the low frequency differential control signal output by the second pre-driver circuit. There is no problem that the low frequency differential signal is attenuated during transmission.
  • the second pre-driver circuit includes a first level shifter and a second level shifter
  • the input end of the first level shifter is connected to the first input end of the second pre-driver circuit, the output end of the first level shifter is connected to the first output end of the second pre-driver circuit; the input of the second level shifter The terminal is connected to the second input end of the second pre-driver circuit, and the output end of the second level shifter is connected to the second output end of the second pre-driver circuit.
  • the selection circuit further includes a third switch tube, a fourth switch tube, a fifth switch tube, and a sixth switch tube;
  • the first end of the first resistor is connected to the first end of the third switch tube and the first end of the fourth switch tube, the second end of the third switch tube is connected to the first output end of the selection circuit, and the second end of the fourth switch tube Connecting a second output end of the selection circuit;
  • the first end of the third resistor is connected to the first end of the fifth switch tube and the first end of the sixth switch tube, the second end of the fifth switch tube is connected to the first output end of the selection circuit, and the second end of the sixth switch tube Connecting a second output end of the selection circuit;
  • the first input end of the selection circuit is connected to the control end of the third switch tube and the control end of the fifth switch tube, and the second input end of the selection circuit is connected to the control end of the fourth switch tube and the control end of the sixth switch tube;
  • the low frequency differential control signal is used to control the third switch tube and the fifth switch tube to be turned on, or to control the fourth switch tube and the sixth switch The switch tube is turned on;
  • the controller controls the third switch tube, the fourth switch tube, the fifth switch tube, and the sixth switch tube to be turned off.
  • the power supply voltage of the main driving circuit is a high voltage power supply
  • the main driving circuit includes a second current source, a third current source, a seventh switching tube, an eighth switching tube, a sixth resistor, and a seventh resistor;
  • the high voltage power supply is connected to the first end of the sixth resistor and the first end of the seventh resistor, the second end of the sixth resistor is connected to the first end of the seventh switch tube, and the second end of the seventh switch tube is connected to the second current source
  • the positive end, the negative end of the second current source is connected to the positive end of the third current source, the negative end of the third current source is grounded;
  • the second end of the seventh resistor is connected to the first end of the eighth switch tube, and the eighth switch tube is The second end is connected to the positive end of the second current source;
  • the first input end of the main drive circuit is connected to the control end of the seventh switch tube, and the second input end of the main drive circuit is connected to the control end of the eighth switch tube.
  • the main driving circuit is powered by a high voltage power supply, so that the main driving circuit outputs a differential signal conforming to the transmission protocol, and the main driving circuit 20 uses two current sources (the second current source and the third current source), which can be changed at the input of the main driving circuit.
  • the bias current jitter in the main driving circuit is reduced, thereby reducing the jitter of the output common mode voltage of the main driving circuit.
  • the seventh switch tube and the eighth switch tube are metal-oxide-semiconductor field effect transistors, and the seventh switch tube and the eighth switch tube are thick gate tubes.
  • the power supply voltage of the first pre-drive circuit is a low voltage power supply; and the power supply voltage of the second pre-drive circuit is a high voltage power supply.
  • the first pre-driver circuit is powered by a low voltage power supply to reduce the power consumption of the first pre-driver circuit.
  • the second pre-drive circuit is powered by a high voltage power supply, so that the low frequency differential control signal output by the second pre-drive circuit can effectively control the on and off of the switch tube in the selection circuit.
  • a second aspect of the embodiments of the present invention provides a serial deserializer, including a serializer and a deserializer.
  • the serializer and the deserializer are connected by a data link, and the serializer includes the driver of the first aspect of the embodiment of the present invention.
  • a circuit, the deserializer configured to receive a serial signal transmitted by the serializer from the data link and perform deserialization processing on the serial signal to obtain parallel data.
  • FIG. 1 is a schematic structural view of a driving circuit disclosed in the prior art
  • FIG. 2 is a schematic structural diagram of a serial deserializer according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a driving circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of waveforms of a differential signal disclosed in an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of another driving circuit according to an embodiment of the present invention.
  • FIG. 6(a) is a schematic diagram showing the waveform of the signal VO2_P before and after passing through the first DC blocking capacitor C1 according to the embodiment of the present invention
  • 6(b) is a schematic diagram showing waveforms of the signal VO2_N disclosed before and after passing through the second DC blocking capacitor C2 according to the embodiment of the present invention
  • FIG. 7 is a schematic structural diagram of another driving circuit according to an embodiment of the present invention.
  • FIG. 8(a) is a schematic diagram showing superimposed waveforms of an output of a selection circuit and an output of a first pre-drive circuit disclosed in the implementation of the present invention
  • FIG. 8(b) is a schematic diagram showing superimposed waveforms of an output of another selection circuit and an output of the first pre-drive circuit disclosed in the implementation of the present invention
  • FIG. 9 is a schematic diagram of comparison between a high frequency differential signal input by a first pre-drive circuit and a low frequency differential signal according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of another driving circuit according to an embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of another driving circuit according to an embodiment of the present invention.
  • FIG. 12 is a schematic structural diagram of a main driving circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a serial deserializer according to an embodiment of the present invention.
  • the serial deserializer 1000 includes a serializer 2000 and a deserializer 3000.
  • the processor 2000 and the deserializer 3000 are connected by a data link 4000.
  • the serializer 2000 includes a driving circuit 100 and a parallel-serial circuit 200, and the serial-sequence circuit 200 is used for serializing parallel data to obtain serial data and driving
  • the circuit 100 converts the serial data into a serial signal conforming to the transmission protocol of the data link 400 and transmits it to the data link 400.
  • the deserializer 3000 receives the serial signal transmitted by the serializer 2000 from the data link 400 and The serial signal is deserialized to obtain parallel data.
  • the serializer 2000 may also be referred to as a transmitting end (Rx), and the deserializer 3000 may also be referred to as a receiving end (Tx).
  • the serial deserializer 1000 may also be referred to as a high-speed serial signal transmitting and receiving circuit, which can realize high speed. Transmission and reception of serial signals.
  • the transmission protocol of the data link 400 may include any one of a High Definition Multimedia Interface (HDMI) protocol, a DDR protocol, and a USB protocol.
  • HDMI High Definition Multimedia Interface
  • the serial deserializer 1000 can adopt a differential transmission mode.
  • the differential transmission is that the transmitting end transmits two signals of equal amplitude and opposite phase on two transmission lines, and the receiving end performs subtraction on the two received signals.
  • Differential transmission can improve the signal-to-noise ratio of the transmitted signal.
  • the data link 400 of the serial deserializer 1000 only needs a pair of transmission lines (such as data line 1 and data line 2 shown in FIG. 1) to realize differential transmission of serial signals, and the data link adopting parallel transmission. This reduces the cost, reduces the complexity of the serializer 2000 and deserializer 3000 interconnects, and eliminates the need to transmit synchronous clocks in the data link, increasing the data transfer rate.
  • FIG. 3 is a schematic structural diagram of a driving circuit according to an embodiment of the present invention.
  • the driving circuit shown in FIG. 3 can be applied to the serial deserializer shown in FIG. 2.
  • the driving circuit may include a first pre-driving circuit 11, a main driving circuit 20, and a selection circuit 30, wherein:
  • the first pre-drive circuit 11 includes a first input terminal 1101, a second input terminal 1102, a first output terminal 1103, and a second output terminal 1104.
  • the selection circuit 30 includes a first output terminal 3001 and a second output terminal 3002.
  • the main driver circuit 20 includes a first input terminal 2001 and a second input terminal 2002, the first output terminal 1103 of the first pre-drive circuit 22 is connected to the first input terminal 2001 of the main drive circuit 20 and the first output terminal 3001 of the selection circuit 30, first The second output terminal 1104 of the pre-driver circuit 11 is connected to the second input terminal 2002 of the main drive circuit 20 and the second output terminal 3002 of the selection circuit 30; when the first input terminal 1101 and the second input terminal of the first pre-driver circuit 11 When the high frequency differential signal is input to 1102, the first output terminal 1103 and the second output terminal 1104 of the first pre-driver circuit 11 output a high frequency differential signal having a common mode voltage of zero, and the first output terminal 3001 and the second of the selection circuit 30
  • the first input terminal 1101 and the second input terminal 1102 of the first pre-driver circuit 11 can input a differential signal (a differential signal composed of a signal VIN_P and a signal VIN_N), and the differential signal is equal to a pair of amplitudes.
  • the signal consists of opposite phases.
  • FIG. 4 is a schematic diagram of a waveform of a differential signal according to an embodiment of the present invention.
  • the differential signal is composed of a signal VIN_P and a signal VIN_N, and the amplitudes of the signals VIN_P and VIN_N are both VDD and phase. in contrast.
  • a high level signal VIN_P, VIN_N signal is low, the time period t 2, the signal VIN_P is low, a high level signal VIN_N.
  • the common mode voltage of the differential signal is equal to the average value of the high level and the low level of the differential signal. If the low level of the differential signal is 0 and the high level is VDD, the common mode voltage of the differential signal is 0.5 VDD.
  • the differential signal can be divided into a high frequency differential signal and a low frequency differential signal.
  • High frequency refers to the frequency band above the minimum operating frequency specified by the transmission protocol
  • low frequency refers to the frequency band below the minimum operating frequency specified by the transmission protocol.
  • a high frequency differential signal refers to a differential signal having a frequency greater than 250 MHz.
  • Low frequency differential signals refer to differential signals with frequencies below 250 MHz.
  • the low frequency differential signal is primarily used to modulate or test the circuit.
  • the low frequency differential signal may comprise a direct current signal.
  • the first pre-drive circuit 11 and the selection circuit 30 jointly drive the main drive circuit 20. Since the selection circuit 30 is added, the common mode voltage of the high frequency differential signal outputted to the main driving circuit 20 can be determined by the selection circuit 30 to be the first common mode voltage, and the first common mode voltage is determined by the selection circuit 20, the first common mode The high stability of the voltage ensures that the high-frequency differential signal outputted to the main driving circuit 20 does not fluctuate greatly, and the stability of the high-frequency differential signal outputted to the main driving circuit 20 is improved, thereby avoiding the occurrence of the main driving circuit 20. The problem of large fluctuations in output.
  • FIG. 5 is a schematic structural diagram of another driving circuit according to an embodiment of the present invention.
  • the first pre-drive circuit 11 includes a first inverter U1, a second inverter U2, a third inverter U3, a fourth inverter U4, a first DC blocking capacitor C1, and a second DC blocking capacitor C2;
  • the input end of the first inverter U1 is connected to the first input end 1101 of the first pre-driver circuit 11.
  • the output end of the first inverter U1 is connected to the input end of the second inverter U2, and the second inverter U2 is The output end is connected to the first end of the first DC blocking capacitor C1, the second end of the first DC blocking capacitor C1 is connected to the first output end 1103 of the first pre-drive circuit 11;
  • the input end of the third inverter U3 is connected to the first end a second input end 1102 of the pre-driver circuit 11, an output end of the third inverter U3 is connected to the input end of the fourth inverter U4, and an output end of the fourth inverter U4 is connected to the first end of the second DC blocking capacitor C2.
  • the second end of the second DC blocking capacitor C2 is connected to the second output end 1104 of the first pre-driver circuit 11.
  • the inverter can reverse the phase of the input signal by 180°, and when the input of the inverter is high, the output is low; when the input of the inverter is low, the output is High level.
  • the inverter can be a Transistor-Transistor Logic (TTL) inverter or a Complementary Metal Oxide Semiconductor (COMS) inverter.
  • the input end of the first inverter U1 is connected to the first input end 1101 of the first pre-driver circuit 11
  • the input end of the third inverter U3 is connected to the second input end 1102 of the first pre-driver circuit 11, the first
  • the phase comparator U1 and the third inverter U3 input a high frequency differential signal, wherein the high frequency differential signal is composed of a signal VIN_P and a signal VIN_N, the signal VIN_P and the signal VIN_N have the same amplitude, opposite phases, and the signals VIN_P and VIN_N
  • the flat change frequency is greater than or equal to the minimum operating frequency specified by the transmission protocol.
  • the signal VIN_P When the signal VIN_P is high, the signal VIN_N is low, and when the signal VIN_P is low, the signal VIN_N is high.
  • the differential signal diagram shown in Figure 4. the input terminal VIN_P is input to the input terminal of the first inverter U1, and the signal VIN_N is input to the input terminal of the third inverter U3.
  • the power supply voltage of the first pre-drive circuit 11 is the low-voltage power supply VDD_LV, and the first pre-drive circuit 11 is powered by the low-voltage power supply VDD_LV to reduce the power consumption of the first pre-drive circuit 11.
  • the first pre-drive circuit 11 employs an inverter, and the inverter consumes less power when the input level does not jump, further reducing the power consumption of the first pre-drive circuit 11.
  • the output level of the first pre-driver circuit 11 can also quickly jump.
  • the output signal VO1_P of the first inverter U1 When the signal VIN_P is at a high level, the output signal VO1_P of the first inverter U1 is at a low level, the output signal VO2_P of the second inverter U2 is at a high level; when the signal VIN_P is at a low level, the first inversion is performed.
  • the output signal VO1_P of the U1 is at a high level, and the output signal VO2_P of the second inverter U2 is at a low level.
  • the first DC blocking capacitor C1 can filter the DC component of the signal VO2_P so that the DC component of the signal VO2_P cannot be output to the first output terminal 1103 of the first pre-drive circuit 11, the first output of the first pre-drive circuit 11.
  • the signal output from the terminal 1103 does not include a DC component.
  • a waveform diagram of the signal VO2_P passing back and forth through the first DC blocking capacitor C1 will be described below with reference to FIG. 6(a).
  • the high level voltage of the signal VO2_P is VDD_LV
  • the low level voltage of the signal VO2_P is 0, and the DC component of the signal VO2_P is the signal VO2_P.
  • the signal output by the first output terminal 1103 of the first pre-driver circuit 11 is a signal after the signal VO2_P passes through the first DC blocking capacitor C1.
  • the output signal VO1_N of the third inverter U1 is at a low level, and the output signal VO2_N of the fourth inverter U2 is at a high level; when the signal VIN_N is at a low level, The output signal VO1_N of the three inverter U1 is at a high level, and the output signal VO2_N of the fourth inverter U2 is at a low level.
  • the second DC blocking capacitor C2 can filter the DC component of the signal VO2_N such that the DC component of the signal VO2_N cannot be output to the second output terminal 1104 of the first pre-drive circuit 11, and the second output of the first pre-drive circuit 11
  • the signal output by terminal 1104 does not include a DC component.
  • a waveform diagram of the signal VO2_N passing back and forth through the second DC blocking capacitor C2 will be described below with reference to FIG. 6(b). As shown in FIG.
  • the signal VO2_N passes through the second DC blocking capacitor C2
  • the high level voltage of the signal VO2_N is VDD_LV
  • the low level voltage of the signal VO2_N is 0
  • the DC component of the signal VO2_N is the signal VO2_N.
  • the DC component in the signal VO2_N is filtered out.
  • the signal outputted by the second output terminal 1104 of the first pre-driver circuit 11 is a signal after the signal VO2_N passes through the second DC blocking capacitor C2.
  • FIG. 7 is a schematic structural diagram of another driving circuit according to an embodiment of the present invention.
  • the driving circuit further includes a controller 40.
  • the power supply voltage of the selection circuit 30 is a high voltage power supply VDD_HV, and the selection circuit 30 includes a first current source N1, a first resistor R1, a second resistor R2, and a third resistor R3. a fourth resistor R4, a fifth resistor R5, a first switching transistor T1 and a second switching transistor T2;
  • the high voltage power supply VDD_HV is connected to the positive end of the first current source N1, the negative end of the first current source N1 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the first end of the second resistor R2, The first end of the fourth resistor R4 and the first end of the fifth resistor R5, the second end of the second resistor R2 is connected to the first end of the third resistor R3, the second end of the third resistor R3 is grounded; the fourth resistor R4 The second end is connected to the first end of the first switch tube T1, the second end of the first switch tube T1 is connected to the first output end 3001 of the selection circuit 30; the second end of the fifth resistor R5 is connected to the second switch tube T2 The second end of the second switch tube T2 is connected to the second output end 3002 of the selection circuit 30.
  • the controller 40 includes a first control end 4001 and a second control end 4002. The first control end 4001 is connected to the first switch tube T1.
  • the controller 40 controls the first switch transistor T1 and the second switch transistor T2 to be turned on;
  • the controller 40 controls the first switching transistor T1 and the second switching transistor T2 to be turned off.
  • the first common mode voltage VCM I 1 ⁇ (R2+R3), where I 1 is the bias current supplied by the first current source N1, R2 is the resistance of the second resistor R2, and R3 is The resistance of the third resistor R3.
  • the magnitude of the first common mode voltage VCM can be determined by the bias current of the first current source N1 in the selection circuit 30, the second resistance R2, and the third resistance R3.
  • the bias current of the current source in the selection circuit 30, the second resistor R2, and the third resistor R3 may be designed to design the magnitude of the first common mode voltage VCM such that the first common mode voltage VCM can satisfy the requirements of the main driving circuit 20. .
  • the controller 40 controls the first switch transistor T1 and the second switch transistor T2 to be turned on.
  • the high frequency differential signal is composed of a signal VIN_P and a signal VIN_N.
  • the signal VIN_P and the signal VIN_N have the same amplitude and opposite phases, and the level change frequency of the signal VIN_P and the signal VIN_N is greater than or equal to the minimum operating frequency specified by the transmission protocol.
  • the signal VIN_P is high, the signal VIN_N is low, and when the signal VIN_P is low, the signal VIN_N is high.
  • the first switching transistor T1 and the second switching transistor T2 When the first switching transistor T1 and the second switching transistor T2 are turned on, the first output terminal 3001 and the second output terminal 3002 of the selection circuit 30 output the first common mode voltage VCM, and the first output terminal 3001 of the selection circuit 30 and the first The output terminal 3002 outputs the first common mode voltage VCM and superimposes the high frequency differential signal of the common mode voltage outputted by the first output terminal 1103 and the second output terminal 1104 of the first output terminal 1103 of the first pre-driver circuit 11 to zero.
  • a high frequency differential signal (signal VPRE_P and signal VPRE_N) having a common mode voltage of a first common mode voltage VCM, wherein the common mode voltage is a high frequency differential signal of the first common mode voltage VCM for driving the main driving circuit 20, the signal The VPRE_P and the signal VPRE_N serve as input signals to the main drive circuit 20.
  • the outputs of the first output terminal 3001 and the second output terminal 3002 of the selection circuit 30 are zero.
  • the conduction conditions of the first switching transistor T1 and the second switching transistor T2 are either a high level conduction or a low level conduction.
  • the guiding of the first switching transistor T1 and the second switching transistor T2 The pass condition is a high level conduction; if the first switch tube T1 and the second switch tube T2 are P-Metal-Oxide-Semiconductor (PMOS) transistors, the first switch tube T1 and the second The conduction condition of the switch tube T2 is a low level conduction.
  • NMOS N-Metal-Oxide-Semiconductor
  • PMOS P-Metal-Oxide-Semiconductor
  • the signal output by the first output terminal 1103 of the first pre-driver circuit 11 is a signal after the signal VO2_P passes through the first DC blocking capacitor C1.
  • the signal output by the first output terminal 3001 of the selection circuit 30 is the first common mode voltage VCM.
  • FIG. 8(a) is a schematic diagram showing superimposed waveforms of the output of the selection circuit 30 and the output of the first pre-drive circuit 11 disclosed in the implementation of the present invention.
  • the signal VO2_P is superimposed with the first common mode voltage VCM by the signal after the first DC blocking capacitor C1 to form a signal VPRE_P
  • the common mode voltage of the signal VPRE_P is the first common mode voltage VCM.
  • FIG. 8(b) is a schematic diagram showing superimposed waveforms of the output of another selection circuit 30 and the output of the first pre-drive circuit 11 disclosed in the practice of the present invention.
  • the signal VO2_N is superimposed with the first common mode voltage VCM by the signal after the second DC blocking capacitor C2 to form a signal VPRE_N, and the common mode voltage of the signal VPRE_N is the first common mode voltage VCM.
  • the driving circuit shown in FIGS. 5 and 7 is applied to the case where the first pre-driving circuit 11 inputs a high-frequency differential signal.
  • the first pre-drive circuit 11 inputs the low-frequency differential signal
  • the driving circuit shown in FIGS. 5 and 7 is still employed, the first blocking capacitor C1 and the second blocking capacitor C2 in the first pre-driving circuit 11
  • the blocking action of the low-frequency differential signal causes a large attenuation of the low-frequency differential signal in the signal VPRE_P and the signal VPRE_N, causing the output of the first pre-driver circuit 11 to fluctuate greatly, thereby causing the output of the main drive circuit 20 to be abnormal, resulting in a difference. Signal distortion.
  • FIG. 9 is a schematic diagram of comparison between a high frequency differential signal and a low frequency differential signal input by the first pre-drive circuit 11 according to an embodiment of the present invention.
  • the left diagram is a schematic diagram of the input signals (signal VPRE_P and signal VPRE_N) of the main drive circuit 20 when the high frequency differential signal is input by the first pre-drive circuit 11, and the right diagram shows the input low frequency of the first pre-drive circuit 11.
  • the signal VPRE_P and the signal VPRE_N do not exhibit attenuation; when the first pre-drive circuit 11 inputs the low frequency differential signal, the signal VPRE_P and the signal VPRE_N exhibit a significant attenuation.
  • the embodiment of the invention discloses a second pre-drive circuit for processing the input low-frequency differential signal without causing attenuation of the low-frequency differential signal.
  • FIG. 10 is a schematic structural diagram of another driving circuit according to an embodiment of the present invention.
  • the driving circuit further includes a second pre-driving circuit 12, and the second pre-driving circuit 12 includes a first input.
  • the terminal 1201, the second input terminal 1202, the first output terminal 1203 and the second output terminal 1204, the selection circuit 30 further includes a first input terminal 3003 and a second input terminal 3004;
  • the first input terminal 1201 of the second pre-drive circuit 12 is connected to the first input end 1101 of the first pre-drive circuit 11, and the second input end 1202 of the second pre-drive circuit 12 is connected to the second input end 1102 of the first pre-drive circuit 11.
  • the first output terminal 1203 of the second pre-driver circuit 12 is connected to the first input terminal 3003 of the selection circuit 30, and the second output terminal 1204 of the second pre-driver circuit 12 is connected to the second input terminal 3004 of the selection circuit 30;
  • the first output terminal 1203 and the second output terminal 1204 of the second pre-drive circuit 12 output a low frequency differential control signal, and the low frequency
  • the differential control signal is used to control the first output terminal 3001 and the second output terminal 3002 of the selection circuit 30 to output a first low frequency differential signal for driving the main driving circuit 20.
  • the first low-frequency differential signal is output by the selection circuit 30 under the control of the low-frequency differential control signal output by the second pre-drive circuit 12, and the high-level and low-level sizes of the first low-frequency differential signal can be selected.
  • Circuit 30 determines. By using the second pre-drive circuit 12, the output of the selection circuit 30 can be stabilized, thereby ensuring that the input signal of the main drive circuit 20 is stable and there is no problem of signal distortion.
  • FIG. 11 is a schematic structural diagram of another driving circuit according to an embodiment of the present invention.
  • the second pre-driver circuit 12 includes a first level shifter 121 and a second level shifter 122;
  • the input end of the first level shifter 121 is connected to the first input end 1201 of the second pre-driver circuit 12, and the output end of the first level shifter 121 is connected to the first output end 1203 of the second pre-driver circuit 12;
  • the input of the level shifter 122 is coupled to the second input 1202 of the second pre-driver circuit 12, and the output of the second level shifter 122 is coupled to the second output 1204 of the second pre-driver circuit 12.
  • the level shifter can process the input low frequency differential signal, and when the level shifter inputs the high frequency differential signal, the output of the level shifter is zero.
  • the level shifter is used to convert the high level in the differential signal to the supply voltage of the level shifter, and the level shifter does not process the low level in the differential signal and still outputs a low level.
  • the signal input to the input terminal of the first level shifter 121 is the signal VIN_P
  • the signal input to the input terminal of the second level shifter 122 is the signal VIN_N.
  • the signal VIN_P is at a high level
  • the signal VIN_N is at a low level
  • the supply voltages of the first level shifter 121 and the second level shifter 122 are VDD_HV
  • the output of the first level shifter 121 outputs VDD_HV
  • the output of the second level shifter 122 still outputs a low level.
  • the selection circuit 30 may further include a third switch tube T3, a fourth switch tube T4, a fifth switch tube T5 and a sixth switch tube T6;
  • the first end of the first resistor R1 is connected to the first end of the third switch tube T3 and the first end of the fourth switch tube T4, and the second end of the third switch tube T3 is connected to the first output end 3001 of the selection circuit 30, The second end of the four switch tube T4 is connected to the second output end 3002 of the selection circuit 30;
  • the first end of the third resistor R3 is connected to the first end of the fifth switch tube T5 and the first end of the sixth switch tube T6, and the second end of the fifth switch tube T5 is connected to the first output end 3001 of the selection circuit 30, The second end of the six switch tube T6 is connected to the second output end 3002 of the selection circuit 30;
  • the first input terminal 3003 of the selection circuit 30 is connected to the control terminal of the third switch transistor T3 and the control terminal of the fifth switch transistor T5, and the second input terminal 3004 of the selection circuit 30 is connected to the control terminal and the sixth switch of the fourth switch transistor T4.
  • the low frequency differential control signal is used to control the third switch transistor T3 and the sixth switch transistor T6 to be turned on, and the fourth switch transistor T4 and the fifth switch tube T5 are turned off, or the fourth switch tube T4 and the fifth switch tube T5 are controlled to be turned on, the third switch tube T3 and the sixth switch tube T6 are turned off; the controller 40 controls the first switch tube T1 and The second switch tube T2 is turned off;
  • the controller 40 controls the third switch transistor T3, the fourth switch transistor T4, the fifth switch transistor T5, and the sixth The switch tube T6 is turned off.
  • the output end of the first level shifter 121 is connected to the first output end 1203 of the second pre-drive circuit 12, and the first output end 1203 of the second pre-drive circuit 12 is connected to the first input end of the selection circuit 30. 3003.
  • the first input terminal 3003 of the selection circuit 30 is connected to the control end of the third switch tube T3 and the control end of the fifth switch tube T5.
  • the output end of the first level shifter 121 is connected to the control end of the third switch tube T3 and the control end of the fifth switch tube T5.
  • the output of the second level shifter 122 is connected to the second output terminal 1204 of the second pre-driver circuit 12, and the second output terminal 1204 of the second pre-driver circuit 12 is connected to the second input terminal 3004 of the selection circuit 30.
  • the selection circuit 30 The second input terminal 3004 is connected to the control end of the fourth switch tube T4 and the control end of the sixth switch tube T6.
  • the output end of the second level shifter 122 is connected to the control end of the fourth switch tube T4 and the control end of the sixth switch tube T6.
  • the conduction condition of the third switch tube T3 and the fourth switch tube T4 is a high level conduction, and the conduction characteristics of the fifth switch tube T5 and the sixth switch tube T6 are a low level conduction; or, the third The conduction condition of the switching transistor T3 and the fourth switching transistor T4 is a low level conduction, and the conduction characteristics of the fifth switching tube T5 and the sixth switching tube T6 are a high level conduction.
  • the conduction characteristics of the third switching transistor T3 and the fourth switching transistor T4 are turned on at a high level, and the conduction characteristics of the fifth switching transistor T5 and the sixth switching transistor T6 are turned on at a low level as an example.
  • the third switching transistor T3 and the fourth switching transistor T4 are PMOS transistors
  • the fifth switching transistor T5, and the sixth switching transistor T6 are PMOS as an example.
  • the low frequency mode refers to that the signal input by the first pre-drive circuit 11 or the second pre-drive circuit 12 is a low frequency differential signal.
  • the high frequency mode means that the signal input by the first pre-drive circuit 11 or the second pre-drive circuit 12 is a high frequency differential signal.
  • the third switch T3 is turned on, and the fifth switch T5 is turned off, the fourth switch The tube T4 is turned off, and the sixth switch tube T6 is turned on. Since the first switching transistor T1 and the second switching transistor T2 are controlled to be turned off by the controller 40 in the low frequency mode, the first output terminal 3001 of the selection circuit 30 outputs the voltage VH, and the second output terminal 3002 of the selection circuit 30 outputs Voltage VL.
  • the third switch transistor T3 is turned off, and the fifth switch transistor T5 is turned on, and the fourth switch is turned on.
  • the tube T4 is turned on, and the sixth switch tube T6 is turned off. Since the first switch tube T1 and the second switch tube T2 are controlled to be turned off by the controller 40 in the low frequency mode, the first output terminal 3001 of the selection circuit 30 outputs the voltage VL, and the second output terminal 3002 of the selection circuit 30 outputs Voltage VH.
  • the voltage VH constitutes a high level of the first low frequency differential signal
  • the voltage VL constitutes a low level of the first low frequency differential signal.
  • VL I 1 ⁇ R3
  • I 1 is the bias current supplied by the first current source N1
  • R1 is the resistance of the first resistor R1
  • R2 is the second The resistance of the resistor R2
  • R3 is the resistance of the third resistor R3.
  • the magnitude of the voltage VH and the voltage VL can be determined by the bias current of the first current source N1 in the selection circuit 30, the second resistor R2, and the third resistor R3.
  • the bias current of the current source in the selection circuit 30, the first resistor R1, the second resistor R2, and the third resistor R3 can be designed to design the magnitudes of the voltage VH and the voltage VL so that the voltage VH and the voltage VL can satisfy the main driving circuit. 20 needs.
  • the signals input by the first pre-driver circuit 11 and the second pre-driver circuit 12 are high frequency differential signals, the first pre-driver circuit 11 operates, the second pre-driver circuit 12 stops operating, and the second pre-driver The output of the drive circuit 12 is zero, and the selection circuit 30 outputs the first common mode voltage VCM.
  • the signals input by the first input terminal 1101 of the first pre-driver circuit 11 and the first input terminal 1201 of the second pre-driver circuit 12 are the signal VIN_P
  • the second input terminal 1102 and the second of the first pre-driver circuit 11 are
  • the input signal of the second input 1202 of the pre-driver circuit 12 is the signal VIN_N
  • the signal VIN_P and the signal VIN_N form a high frequency differential signal.
  • the signal VIN_P is at a high level
  • the signal VIN_N is at a low level
  • the first output terminal 1103 of the first pre-driver circuit 11 outputs a high voltage of VDD_LV/2, the first pre-driver circuit.
  • the second output terminal 1104 of the output voltage of 11 is a low level of -VDD_LV/2
  • the controller 40 controls the first switch tube T1 and the second switch tube T2 in the selection circuit 30 to be turned on, and the third switch tube T3, fourth The switch tube T4, the fifth switch tube T5 and the sixth switch tube T6 are turned off, and the first output terminal 3001 and the second output terminal 3002 of the selection circuit 30 output the first common mode voltage VCM, and the first input end of the main driving circuit 20
  • the input signal of 2001 is the signal VPRE_P
  • the signal input by the second input terminal 2002 of the main driving circuit 20 is the signal VPRE_N
  • the signal VPRE_P is the level of the high level of VDD_LV/2 superimposed with the first common mode voltage VCM
  • the signal VPRE_N The level at which the high level of -VDD_LV/2 is superimposed with the first common mode voltage VCM.
  • the signal VIN_P is low and the signal VIN_N is high
  • the signal VPRE_P is the level at which the high level of -VDD_LV/2 is superimposed with the first common mode voltage VCM
  • the signal VPRE_N is VDD_LV/2. The level at which the high level is superimposed with the first common mode voltage VCM.
  • the signals input by the first pre-drive circuit 11 and the second pre-drive circuit 12 are low frequency differential signals
  • the first pre-drive circuit 11 outputs the attenuated low frequency differential signals
  • the second pre-drive circuit 12 operates.
  • the selection circuit 30 outputs a first low frequency differential signal.
  • the signals input by the first input terminal 1101 of the first pre-driver circuit 11 and the first input terminal 1201 of the second pre-driver circuit 12 are the signal VIN_P
  • the second input terminal 1102 and the second of the first pre-driver circuit 11 are
  • the input signal of the second input 1202 of the pre-driver circuit 12 is the signal VIN_N
  • the signal VIN_P and the signal VIN_N form a low frequency differential signal.
  • the controller 40 controls the first switch transistor T1 and the second switch transistor T2 in the selection circuit 30 to be turned off, and the voltage output from the first output terminal 1203 of the second pre-driver circuit 12 (VDD_HV)
  • the third switch tube T3 is turned on and the fifth switch tube T5 is turned off, and the low level output of the second output terminal 1204 of the second pre-drive circuit 12 controls the fourth switch tube T4 to be turned off and the sixth switch tube T6 to be turned on.
  • the first output terminal 3001 of the selection circuit 30 outputs the voltage VH
  • the second output terminal 3002 of the selection circuit 30 outputs the voltage VL.
  • the signal input by the first input terminal 2001 of the main driving circuit 20 is the signal VPRE_P
  • the signal input by the two input terminals 2002 is the signal VPRE_N
  • the signal VPRE_P is the voltage VH
  • signal VIN_P is low and signal VIN_N is high
  • signal VPRE_P is voltage VL
  • signal VPRE_N is voltage VH
  • signal VPRE_P 2.7V
  • VPRE_N 3.0V.
  • the power supply voltage of the second pre-drive circuit 12 is a high-voltage power supply VDD_HV, and the high-voltage power supply VDD_HV can ensure that the high-level VDD_HV outputted by the second pre-drive circuit 12 reaches the turn-on voltage of the third switch tube T3 or the fourth switch tube T4.
  • the conduction of the third switching transistor T3 or the fourth switching transistor T4 can be effectively controlled.
  • FIG. 12 is a schematic structural diagram of a main driving circuit according to an embodiment of the present invention.
  • the power supply voltage of the main driving circuit 20 is a high voltage power supply VDD_HV
  • the main driving circuit 20 includes a second current source N2, a third current source N3, a seventh switching transistor T7, an eighth switching transistor T8, and a sixth resistor. R6 and seventh resistor R7;
  • the first end of the sixth resistor R6 is connected to the first end of the sixth resistor R6, and the second end of the sixth resistor R6 is connected to the first end of the seventh switch tube T7, and the second end of the seventh switch tube T7 is connected to the first end of the sixth resistor R6.
  • the negative terminal of the second current source N2 is connected to the positive terminal of the third current source N3, the negative terminal of the third current source N3 is grounded; the second terminal of the seventh resistor R7 is connected to the eighth switch The first end of the tube T8, the second end of the eighth switch tube T8 is connected to the positive end of the second current source N2; the first input end 2001 of the main drive circuit 20 is connected to the control end of the seventh switch tube T7, the main drive circuit 20 The second input terminal 2002 is connected to the control end of the eighth switch tube T8.
  • the main driving circuit 20 is a differential circuit, and the differential signal input from the main driving circuit 20 can be converted into a differential signal conforming to the transmission protocol.
  • the signal input by the first input terminal 2001 of the main driving circuit 20 is the signal VPRE_P
  • the signal input by the second input terminal 2002 of the main driving circuit 20 is the signal VPRE_N
  • the signal input by the first output terminal 2003 of the main driving circuit 20 is the signal VTX+.
  • the signal output by the second output terminal 2004 of the main driving circuit 20 is the signal VTX-.
  • the seventh switching transistor T7 and the eighth switching transistor T8 in FIG. 12 take an NMOS transistor as an example.
  • the seventh switch T7 is turned on, the eighth switch T8 is turned off, and the current flow of the second current source N2 and the third current source N3 is: VDD_HV ⁇ R6 ⁇ T7 ⁇ N2 ⁇ N3, signal VTX- output low level, signal VTX+ output high level; when signal VPRE_P is low level, signal VPRE_N is high level, seventh switch tube T7 is turned off, eighth switch tube T8
  • the current flow directions of the second current source N2 and the third current source N3 are: VDD_HV ⁇ R7 ⁇ T8 ⁇ N2 ⁇ N3, the signal VTX ⁇ outputs a high level, and the signal VTX+ outputs a low level.
  • the main driving circuit 20 employs two current sources (the second current source N2 and the third current source N3), and can reduce the bias current jitter in the main driving circuit 20 when the input of the main driving circuit 20 changes, thereby reducing The jitter of the output common mode voltage of the small main drive circuit 20.
  • the seventh switch tube T7 and the eighth switch tube T8 are metal-oxide-semiconductor field effect transistors, and the seventh switch tube T7 and the eighth switch tube T8 are thick gate tubes. Since the seventh switch tube T7 and the eighth switch tube T8 employ a thick gate tube, the main drive circuit 20 does not need to add an extra thick gate tube to prevent the seventh switch tube T7 and the eighth switch tube T8 from being broken down by high voltage, thereby reducing the main The number of switching tubes in the drive circuit 20.
  • the controllability is high, and the output of the pre-drive circuit can be ensured to be stable, thereby avoiding the large fluctuation of the output of the main drive circuit. problem.

Abstract

一种驱动电路以及串行解串器。该驱动电路包括第一预驱动电路（11）、主驱动电路（20）和选择电路（30），第一预驱动电路（11）的第一输出端（1103）连接主驱动电路（20）的第一输入端（2001）和选择电路（30）的第一输出端（3001），第一预驱动电路（11）的第二输出端（1104）连接主驱动电路（20）的第二输入端（2002）和选择电路（30）的第二输出端（3002）；当第一预驱动电路（11）的第一输入端（1101）和第二输入端（1102）输入高频差分信号时，第一预驱动电路（11）的第一输出端（1103）和第二输出端（1104）输出共模电压为零的高频差分信号，选择电路（30）的第一输出端（3001）和第二输出端（3002）输出第一共模电压，共模电压为零的高频差分信号和第一共模电压叠加形成用于驱动主驱动电路（20）的共模电压为第一共模电压的高频差分信号。可以在提高输出至主驱动电路（20）的高频差分信号的稳定性。

Description

驱动电路以及串行解串器
本申请要求于2018年01月18日提交中国专利局、申请号为2018100510337、发明名称为“驱动电路以及串行解串器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电子电力领域，尤其涉及一种驱动电路以及串行解串器。
背景技术
随着通信技术的不断发展，串行解串器(Serializer-Deserializer，SERDES)逐渐成为高速数据通信中的接口电路。串行解串器包括串行器(Serializer)和解串器(Deserializer)，串行器和解串器通过链路连接，串行器将并行的数据进行串行化处理后的串行数据发送到链路上，解串器接收链路上的串行数据并将串行数据进行解串处理，得到并行的数据。驱动电路是串行器的重要组成部分，驱动电路用于将输入的数字逻辑电平信号转换成符合传输协议的信号发送到链路上。驱动电路包括预驱动电路和主驱动电路，预驱动电路用于接收输入的高速数字逻辑电平信号以及输出能够驱动主驱动电路的预驱动输出信号；主驱动电路用于接收该预驱动输出信号以及输出符合传输协议的信号发送到链路上。
目前的驱动电路如图1所示，预驱动电路包括四个反相器，主驱动电路由差分电路组成，差分电路由一对电阻(R21和R22)、一对薄栅极开关管(N21和N22)、一对厚栅极开关管(N23和N24)和一个电流源(N25)组成。预驱动电路的输入为VIN+和VIN-，预驱动电路的输出为VPRE+和VPRE-，主驱动电路的输入为VPRE+和VPRE-，主驱动电路的输出为VTX+和VTX-，预驱动电路的供电电压为低压电源VDD_LV，主驱动电路的供电电压为高压电源VDD_HV。当VIN+为逻辑高电平(例如，3.3V，对应的数字信号为“1”)，VIN-为逻辑低电平(例如，0V，对应的数字信号为“0”)时，经过两级反相器后，VPRE+为逻辑高电平(逻辑高电平的大小为VDD_LV)，VPRE-为逻辑低电平；当VPRE+为逻辑高电平，VPRE-为逻辑低电平时，N21导通，N22关断，VTX+为逻辑高电平(逻辑高电平的大小为VDD_HV)，VTX-为逻辑低电平。类似的，当VIN+为逻辑低电平，VIN-为逻辑高电平时，VPRE+为逻辑低电平，VPRE-为逻辑高电平，VTX+为逻辑低电平，VTX-为逻辑高电平。预驱动电路采用低压电源VDD_LV作为供电电压是为了降低驱动电路的功耗，同时预驱动电路输出的逻辑高电平也为VDD_LV，由于VDD_LV无法直接驱动厚栅极开关管，因此主驱动电路的输入开关管(N21和N22)采用薄栅极开关管，由于主驱动电路的输出需要满足传输协议的高电平电压，所以主驱动电路的供电电压为VDD_HV，为了避免主驱动电路的输入开关管(N21和N22)被高压击穿，主驱动电路中增加了厚栅极管(N23和N24)。由于预驱动电路采用VDD_LV供电，导致预驱动电路的输出信号(VPRE+或VPRE-)的电压较低，主驱动电路的电流源N25的供电电压过低，会使得电流源N25工作接近线性区，导致电流源N25的工作电流会出现较大的波动，导致主驱动电路的输出波动较大。
发明内容
本发明实施例提供一种驱动电路以及串行解串器，可以解决主驱动电路的输出波动较大的问题。
本发明实施例第一方面提供了一种驱动电路，包括第一预驱动电路和主驱动电路，驱动电路还包括选择电路，其中：
第一预驱动电路包括第一输入端、第二输入端、第一输出端和第二输出端，选择电路包括第一输出端和第二输出端，主驱动电路包括第一输入端和第二输入端，第一预驱动电路的第一输出端连接主驱动电路的第一输入端和选择电路的第一输出端，第一预驱动电路的第二输出端连接主驱动电路的第二输入端和选择电路的第二输出端；当第一预驱动电路的第一输入端和第二输入端输入高频差分信号时，第一预驱动电路的第一输出端和第二输出端输出共模电压为零的高频差分信号，选择电路的第一输出端和第二输出端输出第一共模电压，共模电压为零的高频差分信号和第一共模电压叠加形成共模电压为第一共模电压的高频差分信号，共模电压为第一共模电压的高频差分信号用于驱动主驱动电路。
由于加入了选择电路，可以由选择电路确定输出至主驱动电路的高频差分信号的共模电压为第一共模电压，第一共模电压由选择电路确定，可控性高，可以保证输出至主驱动电路的高频差分信号不会出现较大波动，提高输出至主驱动电路的高频差分信号的稳定性，进而避免出现主驱动电路的输出波动较大的问题。
可选的，第一预驱动电路包括第一反相器、第二反相器、第三反相器、第四反相器、第一隔直电容和第二隔直电容；
第一反相器的输入端连接第一预驱动电路的第一输入端，第一反相器的输出端连接第二反相器的输入端，第二反相器的输出端连接第一隔直电容的第一端，第一隔直电容的第二端连接第一预驱动电路的第一输出端；第三反相器的输入端连接第一预驱动电路的第二输入端，第三反相器的输出端连接第四反相器的输入端，第四反相器的输出端连接第二隔直电容的第一端，第二隔直电容的第二端连接第一预驱动电路的第二输出端。
在第一预驱动电路中加入反相器，当反相器的输入电平发生跳变时，第一预驱动电路的输出电平也可以快速发生跳变。可以降低高频差分信号的传输延时。
可选的，驱动电路还包括控制器，选择电路的供电电压为高压电源，选择电路包括第一电流源、第一电阻、第二电阻、第三电阻、第四电阻、第五电阻、第一开关管和第二开关管；
高压电源连接第一电流源的正端，第一电流源的负端连接第一电阻的第一端，第一电阻的第二端连接第二电阻的第一端、第四电阻的第一端和第五电阻的第一端，第二电阻的第二端连接第三电阻的第一端，第三电阻的第二端接地；第四电阻的第二端连接第一开关管的第一端，第一开关管的第二端连接选择电路的第一输出端；第五电阻的第二端连接第二开关管的第一端，第二开关管的第二端连接选择电路的第二输出端；控制器包括第一控制端和第二控制端，第一控制端连接第一开关管的控制端，第二控制端连接第二开关管的控制端；
当第一预驱动电路的第一输入端和第二输入端输入高频差分信号时，控制器控制第一开关管和第二开关管导通；
当第一预驱动电路的第一输入端和第二输入端输入低频差分信号时，控制器控制第一开关管和第二开关管关断。
采用高压电源为选择电路供电，可以保证选择电路能够输出满足主驱动电路所需要的第一共模电压。
可选的，驱动电路还包括第二预驱动电路，第二预驱动电路包括第一输入端、第二输入端、第一输出端和第二输出端，选择电路还包括第一输入端和第二输入端；
第二预驱动电路第一输入端连接第一预驱动电路的第一输入端，第二预驱动电路第二输入端连接第一预驱动电路的第二输入端，第二预驱动电路的第一输出端连接选择电路的第一输入端，第二预驱动电路的第二输出端连接选择电路的第二输入端；
当第二预驱动电路的第一输入端和第二输入端输入低频差分信号时，第二预驱动电路的第一输出端和第二输出端输出低频差分控制信号，低频差分控制信号用于控制选择电路的第一输出端和第二输出端输出第一低频差分信号，第一低频差分信号用于驱动主驱动电路。
在第二预驱动电路输出的低频差分控制信号的控制下，选择电路可以输出稳定的信号。不会出现低频差分信号在传输过程中出现衰减的问题。
可选的，第二预驱动电路包括第一电平转换器和第二电平转换器；
第一电平转换器的输入端连接第二预驱动电路的第一输入端，第一电平转换器的输出端连接第二预驱动电路的第一输出端；第二电平转换器的输入端连接第二预驱动电路的第二输入端，第二电平转换器的输出端连接第二预驱动电路的第二输出端。
可选的，选择电路还包括第三开关管、第四开关管、第五开关管和第六开关管；
第一电阻的第一端连接第三开关管的第一端和第四开关管的第一端，第三开关管的第二端连接选择电路的第一输出端，第四开关管的第二端连接选择电路的第二输出端；
第三电阻的第一端连接第五开关管的第一端和第六开关管的第一端，第五开关管的第二端连接选择电路的第一输出端，第六开关管的第二端连接选择电路的第二输出端；
选择电路的第一输入端连接第三开关管的控制端和第五开关管的控制端，选择电路的第二输入端连接第四开关管的控制端和第六开关管的控制端；
当第二预驱动电路的第一输入端和第二输入端输入低频差分信号时，低频差分控制信号用于控制第三开关管和第五开关管导通，或者控制第四开关管和第六开关管导通；
当第二预驱动电路的第一输入端和第二输入端输入高频差分信号时，控制器控制第三开关管、第四开关管、第五开关管和第六开关管关断。
可选的，主驱动电路的供电电压为高压电源，主驱动电路包括第二电流源、第三电流源、第七开关管、第八开关管、第六电阻和第七电阻；
高压电源连接第六电阻的第一端和第七电阻的第一端，第六电阻的第二端连接第七开关管的第一端，第七开关管的第二端连接第二电流源的正端，第二电流源的负端连接第三电流源的正端，第三电流源的负端接地；第七电阻的第二端连接第八开关管的第一端，第八开关管的第二端连接第二电流源的正端；主驱动电路的第一输入端连接第七开关管的控制端，主驱动电路的第二输入端连接第八开关管的控制端。
主驱动电路采用高压电源供电可以使得主驱动电路输出符合传输协议的差分信号，主 驱动电路20采用两个电流源(第二电流源和第三电流源)，可以在主驱动电路的输入发生变化时，减小主驱动电路中的偏置电流抖动，从而减小主驱动电路的输出共模电压的抖动。
可选的，第七开关管和第八开关管为金属-氧化物-半导体场效应晶体管，第七开关管和第八开关管为厚栅管。
主驱动电路中无需增加额外的厚栅管来防止第七开关管和第八开关管被高压击穿，可以减少主驱动电路中开关管的数量。
可选的，第一预驱动电路的供电电压为低压电源；第二预驱动电路的供电电压为高压电源。
第一预驱动电路采用低压电源供电可以降低第一预驱动电路的功耗。第二预驱动电路采用高压电源供电，可以使得第二预驱动电路输出的低频差分控制信号能够有效控制选择电路中的开关管的导通与关断。
本发明实施例第二方面提供了一种串行解串器，包括串行器和解串器，串行器和解串器通过数据链路连接，串行器包括本发明实施例第一方面的驱动电路，该解串器，用于从该数据链路上接收该串行器发送的串行信号并将该串行信号进行解串处理以得到并行数据。
附图说明
为了更清楚地说明本发明实施例或背景技术中的技术方案，下面将对本发明实施例或背景技术中所需要使用的附图进行说明。
图1是现有技术公开的一种驱动电路的结构示意图；
图2是本发明实施例公开的一种串行解串器的结构示意图；
图3是本发明实施例公开的一种驱动电路的结构示意图；
图4是本发明实施例公开的一种差分信号的波形示意图；
图5是本发明实施例公开的另一种驱动电路的结构示意图；
图6(a)是本发明实施公开的信号VO2_P通过第一隔直电容C1前后变化波形示意图；
图6(b)是本发明实施公开的信号VO2_N通过第二隔直电容C2前后变化波形示意图；
图7是本发明实施例公开的另一种驱动电路的结构示意图；
图8(a)是本发明实施公开的一种选择电路的输出与第一预驱动电路的输出的叠加波形示意图；
图8(b)是本发明实施公开的另一种选择电路的输出与第一预驱动电路的输出的叠加波形示意图；
图9是本发明实施例公开的一种第一预驱动电路输入高频差分信号与低频差分信号的对比示意图；
图10是本发明实施例公开的另一种驱动电路的结构示意图；
图11是本发明实施例公开的另一种驱动电路的结构示意图；
图12是本发明实施例公开的一种主驱动电路的结构示意图。
具体实施方式
下面结合本发明实施例中的附图对本发明实施例进行描述。
请参阅图2，图2是本发明实施例公开的一种串行解串器的结构示意图，如图2所示，该串行解串器1000包括串行器2000和解串器3000，串行器2000和解串器3000通过数据链路4000连接，串行器2000包括驱动电路100和并转串电路200，并转串电路200用于将并行数据进行串行化处理后得到串行数据，驱动电路100将该串行数据转换为符合数据链路400的传输协议的串行信号发送到数据链路400上，解串器3000从数据链路400上接收串行器2000发送的串行信号并将该串行信号进行解串处理得到并行数据。
其中，串行器2000也可以称为发送端(Rx)，解串器3000也可以称为接收端(Tx)，串行解串器1000也可以称为高速串行信号收发电路，可以实现高速串行信号的发送和接收。
数据链路400的传输协议可以包括高清晰度多媒体接口(High Definition Multimedia Interface，HDMI)协议、DDR协议、USB协议中的任意一种。
串行解串器1000可以采用差分传输方式，差分传输是发送端在两条传输线上传输幅值相等，相位相反的两个信号，接收端对接收的两个信号做减法运算。采用差分传输的方式可以提高传输的信号的信噪比。串行解串器1000的数据链路400只需要一对传输线(如图1所示的数据线1和数据线2)即可实现串行信号的差分传输，与采用并行传输的数据链路相比，可以减小成本，减少串行器2000和解串器3000互连的复杂度，并且不需要在数据链路中传输同步时钟，提高数据传输速率。
请参见图3，图3是本发明实施例公开的一种驱动电路的结构示意图。图3所示的驱动电路可以应用于图2所示的串行解串器。如图3所示，该驱动电路可以包括第一预驱动电路11、主驱动电路20和选择电路30，其中：
第一预驱动电路11包括第一输入端1101、第二输入端1102、第一输出端1103和第二输出端1104，选择电路30包括第一输出端3001和第二输出端3002，主驱动电路20包括第一输入端2001和第二输入端2002，第一预驱动电路22的第一输出端1103连接主驱动电路20的第一输入端2001和选择电路30的第一输出端3001，第一预驱动电路11的第二输出端1104连接主驱动电路20的第二输入端2002和选择电路30的第二输出端3002；当第一预驱动电路11的第一输入端1101和第二输入端1102输入高频差分信号时，第一预驱动电路11的第一输出端1103和第二输出端1104输出共模电压为零的高频差分信号，选择电路30的第一输出端3001和第二输出端3002输出第一共模电压，共模电压为零的高频差分信号和第一共模电压叠加形成共模电压为第一共模电压的高频差分信号，共模电压为第一共模电压的高频差分信号用于驱动主驱动电路20。
如图3所示，第一预驱动电路11的第一输入端1101和第二输入端1102可以输入差分信号(信号VIN_P和信号VIN_N组成的差分信号)，差分信号是由一对幅值相等、相位相反的信号组成。请参阅图4，图4是本发明实施例公开的一种差分信号的波形示意图，如图4所示，差分信号由信号VIN_P和信号VIN_N组成，信号VIN_P与信号VIN_N幅值均为VDD，相位相反。从图4可以看出，在t 1时间段，信号VIN_P为高电平，信号VIN_N 为低电平，在t 2时间段，信号VIN_P为低电平，信号VIN_N为高电平。差分信号的共模电压等于差分信号的高电平和低电平的平均值，如果差分信号的低电平为0，高电平为VDD，则该差分信号的共模电压为0.5VDD。
其中，差分信号可以分为高频差分信号和低频差分信号。高频指的是传输协议规定的最低工作频率以上的频段，低频指的是低于传输协议规定的最低工作频率的频段。例如，对于HDMI协议而言，高频差分信号指的是频率大于250MHz的差分信号。低频差分信号指的是频率低于250MHz的差分信号。低频差分信号主要是用于对电路进行调制或测试。其中，低频差分信号可以包括直流信号。
本发明实施例中，第一预驱动电路11和选择电路30共同驱动主驱动电路20。由于加入了选择电路30，可以由选择电路30确定输出至主驱动电路20的高频差分信号的共模电压为第一共模电压，第一共模电压由选择电路20确定，第一共模电压的稳定性高，可以保证输出至主驱动电路20的高频差分信号不会出现较大波动，提高输出至主驱动电路20的高频差分信号的稳定性，进而避免出现主驱动电路20的输出波动较大的问题。
其中，第一预驱动电路11的具体结构以图5为例进行说明。请参阅图5，图5是本发明实施例公开的另一种驱动电路的结构示意图。如图5所示，第一预驱动电路11包括第一反相器U1、第二反相器U2、第三反相器U3、第四反相器U4、第一隔直电容C1和第二隔直电容C2；
第一反相器U1的输入端连接第一预驱动电路11的第一输入端1101，第一反相器U1的输出端连接第二反相器U2的输入端，第二反相器U2的输出端连接第一隔直电容C1的第一端，第一隔直电容C1的第二端连接第一预驱动电路11的第一输出端1103；第三反相器U3的输入端连接第一预驱动电路11的第二输入端1102，第三反相器U3的输出端连接第四反相器U4的输入端，第四反相器U4的输出端连接第二隔直电容C2的第一端，第二隔直电容C2的第二端连接第一预驱动电路11的第二输出端1104。
本发明实施例中，反相器可以将输入信号的相位反转180°，当反相器的输入为高电平时，输出为低电平；当反相器的输入为低电平时，输出为高电平。反相器可以是逻辑门电路(Transistor-Transistor Logic，TTL)反相器或互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，COMS)反相器。
由于第一反相器U1的输入端连接第一预驱动电路11的第一输入端1101，第三反相器U3的输入端连接第一预驱动电路11的第二输入端1102，第一反相器U1和第三反相器U3输入高频差分信号，其中，高频差分信号由信号VIN_P和信号VIN_N组成，信号VIN_P与信号VIN_N幅值相同，相位相反，并且信号VIN_P和信号VIN_N的电平变化频率大于或等于传输协议规定的最低工作频率。当信号VIN_P为高电平时，信号VIN_N为低电平，当信号VIN_P为低电平时，信号VIN_N为高电平。具体请参见图4所示的差分信号示意图。图5中，第一反相器U1的输入端输入信号VIN_P，第三反相器U3的输入端输入信号VIN_N。
其中，第一预驱动电路11的供电电压为低压电源VDD_LV，第一预驱动电路11采用低压电源VDD_LV供电可以降低第一预驱动电路11的功耗。并且第一预驱动电路11采用反相器，反相器在输入电平不发生跳变时功耗较低，进一步降低第一预驱动电路11的功耗。 反相器在输入电平发生跳变时，第一预驱动电路11的输出电平也可以快速发生跳变。在第一预驱动电路11中加入反相器，可以降低高频差分信号的传输延时。
当信号VIN_P为高电平时，第一反相器U1的输出信号VO1_P为低电平，第二反相器U2的输出信号VO2_P为高电平；当信号VIN_P为低电平时，第一反相器U1的输出信号VO1_P为高电平，第二反相器U2的输出信号VO2_P为低电平。第一隔直电容C1可以将信号VO2_P中的直流分量滤除，使得信号VO2_P中的直流分量无法输出至第一预驱动电路11的第一输出端1103，第一预驱动电路11的第一输出端1103输出的信号中不包含直流分量。下面结合图6(a)阐述信号VO2_P通过第一隔直电容C1前后变化波形示意图。如图6(a)所示，信号VO2_P通过第一隔直电容C1之前，如果信号VO2_P的高电平电压为VDD_LV，信号VO2_P的低电平电压为0，信号VO2_P的直流分量为信号VO2_P的平均电压，假设信号VO2_P的高低电平占比相同，则信号VO2_P的直流分量DC＝VDD_LV/2。信号VO2_P通过第一隔直电容C1之后，信号VO2_P中的直流分量被滤除。第一预驱动电路11的第一输出端1103输出的信号为信号VO2_P通过第一隔直电容C1之后的信号。
类似的，当信号VIN_N为高电平时，第三反相器U1的输出信号VO1_N为低电平，第四反相器U2的输出信号VO2_N为高电平；当信号VIN_N为低电平时，第三反相器U1的输出信号VO1_N为高电平，第四反相器U2的输出信号VO2_N为低电平。第二隔直电容C2可以将信号VO2_N中的直流分量滤除，使得信号VO2_N中的直流分量无法输出至第一预驱动电路11的第二输出端1104，第一预驱动电路11的第二输出端1104输出的信号中不包含直流分量。下面结合图6(b)阐述信号VO2_N通过第二隔直电容C2前后变化波形示意图。如图6(b)所示，信号VO2_N通过第二隔直电容C2之前，如果信号VO2_N的高电平电压为VDD_LV，信号VO2_N的低电平电压为0，信号VO2_N的直流分量为信号VO2_N的平均电压，假设信号VO2_N的高低电平占比相同，则信号VO2_N的直流分量DC＝VDD_LV/2。信号VO2_N通过第二隔直电容C2之后，信号VO2_N中的直流分量被滤除。第一预驱动电路11的第二输出端1104输出的信号为信号VO2_N通过第二隔直电容C2之后的信号。
其中，选择电路30的具体结构以图7为例进行说明。请参阅图7，图7是本发明实施例公开的另一种驱动电路的结构示意图。如图7所示，驱动电路还包括控制器40，选择电路30的供电电压为高压电源VDD_HV，选择电路30包括第一电流源N1、第一电阻R1、第二电阻R2、第三电阻R3、第四电阻R4、第五电阻R5、第一开关管T1和第二开关管T2；
高压电源VDD_HV连接第一电流源N1的正端，第一电流源N1的负端连接第一电阻R1的第一端，第一电阻R1的第二端连接第二电阻R2的第一端、第四电阻R4的第一端和第五电阻R5的第一端，第二电阻R2的第二端连接第三电阻R3的第一端，第三电阻R3的第二端接地；第四电阻R4的第二端连接第一开关管T1的第一端，第一开关管T1的第二端连接选择电路30的第一输出端3001；第五电阻R5的第二端连接第二开关管T2的第一端，第二开关管T2的第二端连接选择电路30的第二输出端3002；控制器40包括第一控制端4001和第二控制端4002，第一控制端4001连接第一开关管T1的控制端，第二控制端4002连接第二开关管T2的控制端；
当第一预驱动电路11的第一输入端1101和第二输入端1102输入高频差分信号时，控 制器40控制第一开关管T1和第二开关管T2导通；
当第一预驱动电路11的第一输入端1101和第二输入端1102输入低频差分信号时，控制器40控制第一开关管T1和第二开关管T2关断。
本发明实施例中，高压电源VDD_HV与低压电源VDD_LV的大小可以由集成电路的工艺确定。例如，对于采用28nm工艺的集成电路而言，VDD_LV＝0.9V，VDD_HV＝3.3V。采用高压电源VDD_HV为选择电路30供电，可以保证选择电路30能够输出满足主驱动电路20所需要的第一共模电压VCM。
从图7可以看出，第一共模电压VCM＝I 1×(R2+R3)，其中I 1为第一电流源N1提供的偏置电流，R2为第二电阻R2的阻值，R3为第三电阻R3的阻值。第一共模电压VCM的大小可以通过选择电路30中的第一电流源N1的偏置电流、第二电阻R2和第三电阻R3来确定。可以设计选择电路30中的电流源的偏置电流、第二电阻R2和第三电阻R3来设计第一共模电压VCM的大小，以使第一共模电压VCM能够满足主驱动电路20的需求。
当第一预驱动电路11的第一输入端1101和第二输入端1102输入高频差分信号时，控制器40控制第一开关管T1和第二开关管T2导通。其中，高频差分信号由信号VIN_P和信号VIN_N组成，信号VIN_P与信号VIN_N幅值相同，相位相反，并且信号VIN_P和信号VIN_N的电平变化频率大于或等于传输协议规定的最低工作频率。当信号VIN_P为高电平时，信号VIN_N为低电平，当信号VIN_P为低电平时，信号VIN_N为高电平。
当第一开关管T1和第二开关管T2导通时，选择电路30的第一输出端3001和第二输出端3002输出第一共模电压VCM，选择电路30的第一输出端3001和第二输出端3002输出第一共模电压VCM与第一预驱动电路11的第一输出端1103的第一输出端1103和第二输出端1104输出的共模电压为零的高频差分信号进行叠加，形成共模电压为第一共模电压VCM的高频差分信号(信号VPRE_P和信号VPRE_N)，该共模电压为第一共模电压VCM的高频差分信号用于驱动主驱动电路20，信号VPRE_P和信号VPRE_N作为主驱动电路20的输入信号。
当第一开关管T1和第二开关管T2关断时，选择电路30的第一输出端3001和第二输出端3002的输出为零。第一开关管T1和第二开关管T2的导通条件为高电平导通或者低电平导通。举例来说，如果第一开关管T1和第二开关管T2为N型金属氧化物半导体(N-Metal-Oxide-Semiconductor，NMOS)晶体管，则第一开关管T1和第二开关管T2的导通条件为高电平导通；如果第一开关管T1和第二开关管T2为P型金属氧化物半导体(P-Metal-Oxide-Semiconductor，PMOS)晶体管，则第一开关管T1和第二开关管T2导通条件为低电平导通。
第一预驱动电路11的第一输出端1103输出的信号为信号VO2_P通过第一隔直电容C1之后的信号。选择电路30的第一输出端3001输出的信号为第一共模电压VCM。请参阅图8(a)，图8(a)是本发明实施公开的一种选择电路30的输出与第一预驱动电路11的输出的叠加波形示意图。如图8(a)所示，信号VO2_P通过第一隔直电容C1之后的信号与第一共模电压VCM叠加后形成信号VPRE_P，信号VPRE_P的共模电压为第一共模电压VCM。
请参阅图8(b)，图8(b)是本发明实施公开的另一种选择电路30的输出与第一预驱 动电路11的输出的叠加波形示意图。如图8(b)所示，信号VO2_N通过第二隔直电容C2之后的信号与第一共模电压VCM叠加后形成信号VPRE_N，信号VPRE_N的共模电压为第一共模电压VCM。
图5和图7所示的驱动电路适用于第一预驱动电路11输入高频差分信号的情况。当第一预驱动电路11输入低频差分信号时，如果仍然采用图5和图7所示的驱动电路，由于第一预驱动电路11中的第一隔直电容C1和第二隔直电容C2对低频差分信号的阻隔作用，则会导致信号VPRE_P和信号VPRE_N中的低频差分信号出现较大衰减，导致第一预驱动电路11的输出波动较大，进而导致主驱动电路20的输出异常，导致差分信号失真。
请参阅图9，图9是本发明实施例公开的一种第一预驱动电路11输入高频差分信号与低频差分信号的对比示意图。如图9所示，左图为第一预驱动电路11输入高频差分信号时，主驱动电路20的输入信号(信号VPRE_P和信号VPRE_N)的示意图；右图为第一预驱动电路11输入低频差分信号时，主驱动电路20的输入信号(信号VPRE_P和信号VPRE_N)的示意图。当第一预驱动电路11输入高频差分信号时，信号VPRE_P和信号VPRE_N没有出现衰减；当第一预驱动电路11输入低频差分信号时，信号VPRE_P和信号VPRE_N出现了较明显的衰减。
本发明实施例公开了第二预驱动电路，第二预驱动电路用于对输入的低频差分信号进行处理，并且不会导致低频差分信号出现衰减。
请参阅图10，图10是本发明实施例公开的另一种驱动电路的结构示意图，如图10所示，驱动电路还包括第二预驱动电路12，第二预驱动电路12包括第一输入端1201、第二输入端1202、第一输出端1203和第二输出端1204，选择电路30还包括第一输入端3003和第二输入端3004；
第二预驱动电路12第一输入端1201连接第一预驱动电路11的第一输入端1101，第二预驱动电路12第二输入端1202连接第一预驱动电路11的第二输入端1102，第二预驱动电路12的第一输出端1203连接选择电路30的第一输入端3003，第二预驱动电路12的第二输出端1204连接选择电路30的第二输入端3004；
当第二预驱动电路12的第一输入端1201和第二输入端1202输入低频差分信号时，第二预驱动电路12的第一输出端1203和第二输出端1204输出低频差分控制信号，低频差分控制信号用于控制选择电路30的第一输出端3001和第二输出端3002输出第一低频差分信号，第一低频差分信号用于驱动主驱动电路20。
本发明实施例中，第一低频差分信号是选择电路30在第二预驱动电路12输出的低频差分控制信号的控制下输出的，第一低频差分信号的高电平和低电平大小可以由选择电路30决定。采用第二预驱动电路12，可以让选择电路30的输出稳定，进而保证主驱动电路20的输入信号稳定，不会出现信号失真的问题。
其中，第二预驱动电路12的具体结构以图11为例进行说明。请参阅图11，图11是本发明实施例公开的另一种驱动电路的结构示意图。如图11所示，第二预驱动电路12包括第一电平转换器121和第二电平转换器122；
第一电平转换器121的输入端连接第二预驱动电路12的第一输入端1201，第一电平转换器121的输出端连接第二预驱动电路12的第一输出端1203；第二电平转换器122的 输入端连接第二预驱动电路12的第二输入端1202，第二电平转换器122的输出端连接第二预驱动电路12的第二输出端1204。
本发明实施例中，电平转换器可以对输入的低频差分信号进行处理，当电平转换器输入高频差分信号时，电平转换器的输出为零。电平转换器用于将差分信号中的高电平转换为电平转换器的供电电压，电平转换器对差分信号中的低电平则不进行处理，仍然输出低电平。如图11所示，第一电平转换器121的输入端输入的信号为信号VIN_P，第二电平转换器122的输入端输入的信号为信号VIN_N。如果信号VIN_P为高电平，信号VIN_N为低电平，第一电平转换器121和第二电平转换器122的供电电压为VDD_HV，则第一电平转换器121的输出端输出VDD_HV，第二电平转换器122的输出端仍然输出低电平。
如图11所示，选择电路30还可以包括第三开关管T3、第四开关管T4、第五开关管T5和第六开关管T6；
第一电阻R1的第一端连接第三开关管T3的第一端和第四开关管T4的第一端，第三开关管T3的第二端连接选择电路30的第一输出端3001，第四开关管T4的第二端连接选择电路30的第二输出端3002；
第三电阻R3的第一端连接第五开关管T5的第一端和第六开关管T6的第一端，第五开关管T5的第二端连接选择电路30的第一输出端3001，第六开关管T6的第二端连接选择电路30的第二输出端3002；
选择电路30的第一输入端3003连接第三开关管T3的控制端和第五开关管T5的控制端，选择电路30的第二输入端3004连接第四开关管T4的控制端和第六开关管T6的控制端；
当第二预驱动电路12的第一输入端1201和第二输入端1202输入低频差分信号时，低频差分控制信号用于控制第三开关管T3和第六开关管T6导通，第四开关管T4和第五开关管T5关断，或者控制第四开关管T4和第五开关管T5导通，第三开关管T3和第六开关管T6关断；控制器40控制第一开关管T1和第二开关管T2关断；
当第二预驱动电路12的第一输入端1201和第二输入端1202输入高频差分信号时，控制器40控制第三开关管T3、第四开关管T4、第五开关管T5和第六开关管T6关断。
本发明实施中，第一电平转换器121的输出端连接第二预驱动电路12的第一输出端1203，第二预驱动电路12的第一输出端1203连接选择电路30的第一输入端3003，选择电路30的第一输入端3003连接第三开关管T3的控制端和第五开关管T5的控制端。第一电平转换器121的输出端连接第三开关管T3的控制端和第五开关管T5的控制端。
第二电平转换器122的输出端连接第二预驱动电路12的第二输出端1204，第二预驱动电路12的第二输出端1204连接选择电路30的第二输入端3004，选择电路30的第二输入端3004连接第四开关管T4的控制端和第六开关管T6的控制端。第二电平转换器122的输出端连接第四开关管T4的控制端和第六开关管T6的控制端。
其中，第三开关管T3和第四开关管T4的导通条件为高电平导通，第五开关管T5和第六开关管T6的导通特性为低电平导通；或者，第三开关管T3和第四开关管T4的导通条件为低电平导通，第五开关管T5和第六开关管T6的导通特性为高电平导通。图11中以第三开关管T3和第四开关管T4的导通特性为高电平导通，第五开关管T5和第六开关管 T6的导通特性为低电平导通为例进行说明。如图11所示，以第三开关管T3和第四开关管T4为NMOS晶体管、第五开关管T5和第六开关管T6为PMOS作为示例进行说明。
其中，为了便于说明，可以定义两种工作模式，低频模式指的是第一预驱动电路11或第二预驱动电路12输入的信号为低频差分信号。相应的，高频模式指的是第一预驱动电路11或第二预驱动电路12输入的信号为高频差分信号。
如果第一电平转换器121的输出端输出高电平，第二电平转换器122的输出端低电平，则第三开关管T3导通，第五开关管T5关断，第四开关管T4关断，第六开关管T6导通。由于第一开关管T1和第二开关管T2在低频模式下由控制器40控制其关断，因此，选择电路30的第一输出端3001输出电压VH，选择电路30的第二输出端3002输出电压VL。
如果第一电平转换器121的输出端输出低电平，第二电平转换器122的输出端高电平，则第三开关管T3关断，第五开关管T5导通，第四开关管T4导通，第六开关管T6关断。由于第一开关管T1和第二开关管T2在低频模式下由控制器40控制其关断，因此，选择电路30的第一输出端3001输出电压VL，选择电路30的第二输出端3002输出电压VH。
其中，电压VH组成第一低频差分信号的高电平，电压VL组成第一低频差分信号的低电平。VH＝＝I 1×(R1+R2+R3)，VL＝I 1×R3，其中I 1为第一电流源N1提供的偏置电流，R1为第一电阻R1的阻值，R2为第二电阻R2的阻值，R3为第三电阻R3的阻值。电压VH和电压VL的大小可以通过选择电路30中的第一电流源N1的偏置电流、第二电阻R2和第三电阻R3来确定。可以设计选择电路30中的电流源的偏置电流、第一电阻R1、第二电阻R2和第三电阻R3来设计电压VH和电压VL的大小，以使电压VH和电压VL能够满足主驱动电路20的需求。
当工作在高频模式时，第一预驱动电路11和第二预驱动电路12输入的信号为高频差分信号，第一预驱动电路11工作，第二预驱动电路12停止工作，第二预驱动电路12输出为零，选择电路30输出第一共模电压VCM。具体的，第一预驱动电路11的第一输入端1101和第二预驱动电路12的第一输入端1201输入的信号为信号VIN_P，第一预驱动电路11的第二输入端1102和第二预驱动电路12的第二输入端1202输入信号为信号VIN_N，信号VIN_P与信号VIN_N组成高频差分信号。结合图11可以看出，如果信号VIN_P为高电平，信号VIN_N为低电平，第一预驱动电路11的第一输出端1103输出电压为VDD_LV/2的高电平，第一预驱动电路11的第二输出端1104输出电压为-VDD_LV/2的低电平，控制器40控制选择电路30中的第一开关管T1和第二开关管T2导通，第三开关管T3、第四开关管T4、第五开关管T5和第六开关管T6关断，选择电路30的第一输出端3001和第二输出端3002输出第一共模电压VCM，主驱动电路20的第一输入端2001输入的信号为信号VPRE_P，主驱动电路20的第二输入端2002输入的信号为信号VPRE_N，信号VPRE_P为VDD_LV/2的高电平与第一共模电压VCM叠加后的电平，信号VPRE_N为-VDD_LV/2的高电平与第一共模电压VCM叠加后的电平。如果VDD_LV＝0.9V，VCM＝2.55V，则信号VPRE_P＝3.0V，VPRE_N＝2.1V。类似的，如果信号VIN_P为低电平，信号VIN_N为高电平，则信号VPRE_P为-VDD_LV/2的高电平与第一共模电压VCM叠加后的电平，信号VPRE_N为VDD_LV/2的高电平与第一共模电压VCM叠加后的电平。如果VDD_LV＝0.9V，VCM＝2.55V，则信号VPRE_P＝2.1V，VPRE_N＝3.0V。
当工作在低频模式时，第一预驱动电路11和第二预驱动电路12输入的信号为低频差分信号，第一预驱动电路11输出衰减后的低频差分信号，第二预驱动电路12工作，选择电路30输出第一低频差分信号。具体的，第一预驱动电路11的第一输入端1101和第二预驱动电路12的第一输入端1201输入的信号为信号VIN_P，第一预驱动电路11的第二输入端1102和第二预驱动电路12的第二输入端1202输入信号为信号VIN_N，信号VIN_P与信号VIN_N组成低频差分信号。结合图11可以看出，如果信号VIN_P为高电平，信号VIN_N为低电平，第二预驱动电路12的第一输出端1203输出电压为VDD_HV的高电平，第二预驱动电路12的第二输出端1104输出低电平，控制器40控制选择电路30中的第一开关管T1和第二开关管T2关闭，第二预驱动电路12的第一输出端1203输出的电压(VDD_HV)控制第三开关管T3导通和第五开关管T5关断，第二预驱动电路12的第二输出端1204输出的低电平控制第四开关管T4关断和第六开关管T6导通，选择电路30的第一输出端3001输出电压VH，选择电路30的第二输出端3002输出电压VL，主驱动电路20的第一输入端2001输入的信号为信号VPRE_P，主驱动电路20的第二输入端2002输入的信号为信号VPRE_N，信号VPRE_P为电压VH，信号VPRE_N为电压VL。如果VH＝3.0V，VL＝2.7V，则信号VPRE_P＝3.0V，VPRE_N＝2.7V。类似的，如果信号VIN_P为低电平，信号VIN_N为高电平，则信号VPRE_P为电压VL，信号VPRE_N为电压VH，则信号VPRE_P＝2.7V，VPRE_N＝3.0V。
其中，第二预驱动电路12的供电电压为高压电源VDD_HV，高压电源VDD_HV可以保证第二预驱动电路12输出的高电平VDD_HV达到第三开关管T3或第四开关管T4的导通电压，能够有效控制第三开关管T3或第四开关管T4的导通。
请参阅图12，图12是本发明实施例公开的一种主驱动电路的结构示意图。如图12所示，主驱动电路20的供电电压为高压电源VDD_HV，主驱动电路20包括第二电流源N2、第三电流源N3、第七开关管T7、第八开关管T8、第六电阻R6和第七电阻R7；
高压电源VDD_HV连接第六电阻R6的第一端和第七电阻R7的第一端，第六电阻R6的第二端连接第七开关管T7的第一端，第七开关管T7的第二端连接第二电流源N2的正端，第二电流源N2的负端连接第三电流源N3的正端，第三电流源N3的负端接地；第七电阻R7的第二端连接第八开关管T8的第一端，第八开关管T8的第二端连接第二电流源N2的正端；主驱动电路20的第一输入端2001连接第七开关管T7的控制端，主驱动电路20的第二输入端2002连接第八开关管T8的控制端。
从图12可以看出，主驱动电路20为差分电路，可以将主驱动电路20输入的差分信号转换为符合传输协议的差分信号。主驱动电路20的第一输入端2001输入的信号为信号VPRE_P，主驱动电路20的第二输入端2002输入的信号为信号VPRE_N，主驱动电路20的第一输出端2003输入的信号为信号VTX+，主驱动电路20的第二输出端2004输出的信号为信号VTX-。图12中的第七开关管T7和第八开关管T8以NMOS晶体管为例。
当信号VPRE_P为高电平，信号VPRE_N为低电平时，第七开关管T7导通，第八开关管T8关断，第二电流源N2和第三电流源N3的电流流向为：VDD_HV→R6→T7→N2→N3，信号VTX-输出低电平，信号VTX+输出高电平；当信号VPRE_P为低电平，信号VPRE_N为高电平时，第七开关管T7关断，第八开关管T8导通， 第二电流源N2和第三电流源N3的电流流向为：VDD_HV→R7→T8→N2→N3，信号VTX-输出高电平，信号VTX+输出低电平。
主驱动电路20采用两个电流源(第二电流源N2和第三电流源N3)，可以在主驱动电路20的输入发生变化时，减小主驱动电路20中的偏置电流抖动，从而减小主驱动电路20的输出共模电压的抖动。
其中，第七开关管T7和第八开关管T8为金属-氧化物-半导体场效应晶体管，第七开关管T7和第八开关管T8为厚栅管。由于第七开关管T7和第八开关管T8采用厚栅管，主驱动电路20中无需增加额外的厚栅管来防止第七开关管T7和第八开关管T8被高压击穿，可以减少主驱动电路20中开关管的数量。
此外，主驱动电路20中由于只有T7和T8一对MOS管，未串联其它MOS管，速度更快。
综上所述，通过实施本发明实施，由于第一共模电压由选择电路预先设定，可控性高，可以保证预驱动电路的输出稳定，进而避免出现主驱动电路的输出波动较大的问题。

Claims (10)

  1. 一种驱动电路，其特征在于，所述驱动电路包括第一预驱动电路、主驱动电路和选择电路，其中：
    所述第一预驱动电路包括第一输入端、第二输入端、第一输出端和第二输出端，所述选择电路包括第一输出端和第二输出端，所述主驱动电路包括第一输入端和第二输入端，所述第一预驱动电路的第一输出端连接所述主驱动电路的第一输入端和所述选择电路的第一输出端，所述第一预驱动电路的第二输出端连接所述主驱动电路的第二输入端和所述选择电路的第二输出端；
    当所述第一预驱动电路的第一输入端和第二输入端输入高频差分信号时，所述第一预驱动电路的第一输出端和第二输出端输出共模电压为零的高频差分信号，所述选择电路的第一输出端和第二输出端输出第一共模电压，所述共模电压为零的高频差分信号和所述第一共模电压叠加形成共模电压为所述第一共模电压的高频差分信号，所述共模电压为所述第一共模电压的高频差分信号用于驱动所述主驱动电路。
  2. 根据权利要求1所述电路，其特征在于，所述第一预驱动电路包括第一反相器、第二反相器、第三反相器、第四反相器、第一隔直电容和第二隔直电容；
    所述第一反相器的输入端连接所述第一预驱动电路的第一输入端，所述第一反相器的输出端连接所述第二反相器的输入端，所述第二反相器的输出端连接所述第一隔直电容的第一端，所述第一隔直电容的第二端连接所述第一预驱动电路的第一输出端；所述第三反相器的输入端连接所述第一预驱动电路的第二输入端，所述第三反相器的输出端连接所述第四反相器的输入端，所述第四反相器的输出端连接所述第二隔直电容的第一端，所述第二隔直电容的第二端连接所述第一预驱动电路的第二输出端。
  3. 根据权利要求2所述电路，其特征在于，所述驱动电路还包括控制器，所述选择电路的供电电压为高压电源，所述选择电路包括第一电流源、第一电阻、第二电阻、第三电阻、第四电阻、第五电阻、第一开关管和第二开关管；
    所述高压电源连接所述第一电流源的正端，所述第一电流源的负端连接所述第一电阻的第一端，所述第一电阻的第二端连接所述第二电阻的第一端、第四电阻的第一端和第五电阻的第一端，所述第二电阻的第二端连接所述第三电阻的第一端，所述第三电阻的第二端接地；所述第四电阻的第二端连接所述第一开关管的第一端，所述第一开关管的第二端连接所述选择电路的第一输出端；所述第五电阻的第二端连接所述第二开关管的第一端，所述第二开关管的第二端连接所述选择电路的第二输出端；所述控制器包括第一控制端和第二控制端，所述第一控制端连接所述第一开关管的控制端，所述第二控制端连接所述第二开关管的控制端；
    当所述第一预驱动电路的第一输入端和第二输入端输入高频差分信号时，所述控制器控制所述第一开关管和所述第二开关管导通；
    当所述第一预驱动电路的第一输入端和第二输入端输入低频差分信号时，所述控制器控制所述第一开关管和所述第二开关管关断。
  4. 根据权利要求3所述电路，其特征在于，所述驱动电路还包括第二预驱动电路，所述第二预驱动电路包括第一输入端、第二输入端、第一输出端和第二输出端，所述选择电路还包括第一输入端和第二输入端；
    所述第二预驱动电路第一输入端连接所述第一预驱动电路的第一输入端，所述第二预驱动电路第二输入端连接所述第一预驱动电路的第二输入端，所述第二预驱动电路的第一输出端连接所述选择电路的第一输入端，所述第二预驱动电路的第二输出端连接所述选择电路的第二输入端；
    当所述第二预驱动电路的第一输入端和第二输入端输入低频差分信号时，所述第二预驱动电路的第一输出端和第二输出端输出低频差分控制信号，所述低频差分控制信号用于控制所述选择电路的第一输出端和第二输出端输出第一低频差分信号，所述第一低频差分信号用于驱动所述主驱动电路。
  5. 根据权利要求4所述电路，其特征在于，所述第二预驱动电路包括第一电平转换器和第二电平转换器；
    所述第一电平转换器的输入端连接所述第二预驱动电路的第一输入端，所述第一电平转换器的输出端连接所述第二预驱动电路的第一输出端；所述第二电平转换器的输入端连接所述第二预驱动电路的第二输入端，所述第二电平转换器的输出端连接所述第二预驱动电路的第二输出端。
  6. 根据权利要求5所述电路，其特征在于，所述选择电路还包括第三开关管、第四开关管、第五开关管和第六开关管；
    所述第一电阻的第一端连接所述第三开关管的第一端和所述第四开关管的第一端，所述第三开关管的第二端连接所述选择电路的第一输出端，所述第四开关管的第二端连接所述选择电路的第二输出端；
    所述第三电阻的第一端连接所述第五开关管的第一端和所述第六开关管的第一端，所述第五开关管的第二端连接所述选择电路的第一输出端，所述第六开关管的第二端连接所述选择电路的第二输出端；
    所述选择电路的第一输入端连接所述第三开关管的控制端和所述第五开关管的控制端，所述选择电路的第二输入端连接所述第四开关管的控制端和所述第六开关管的控制端；
    当所述第二预驱动电路的第一输入端和第二输入端输入低频差分信号时，所述低频差分控制信号用于控制所述第三开关管和所述第五开关管导通，或者控制所述第四开关管和所述第六开关管导通；
    当所述第二预驱动电路的第一输入端和第二输入端输入高频差分信号时，所述控制器控制所述第三开关管、所述第四开关管、所述第五开关管和所述第六开关管关断。
  7. 根据权利要求3～6任一项所述电路，其特征在于，所述主驱动电路的供电电压为所述高压电源，所述主驱动电路包括第二电流源、第三电流源、第七开关管、第八开关管、第六电阻和第七电阻；
    所述高压电源连接所述第六电阻的第一端和所述第七电阻的第一端，所述第六电阻的第二端连接所述第七开关管的第一端，所述第七开关管的第二端连接所述第二电流源的正端，所述第二电流源的负端连接所述第三电流源的正端，所述第三电流源的负端接地；所述第七电阻的第二端连接所述第八开关管的第一端，所述第八开关管的第二端连接所述第二电流源的正端；所述主驱动电路的第一输入端连接所述第七开关管的控制端，所述主驱动电路的第二输入端连接所述第八开关管的控制端。
  8. 根据权利要求7所述电路，其特征在于，所述第七开关管和所述第八开关管为金属-氧化物-半导体场效应晶体管，所述第七开关管和所述第八开关管为厚栅管。
  9. 根据权利要求3～8任一项所述电路，其特征在于，所述第一预驱动电路的供电电压为低压电源；所述第二预驱动电路的供电电压为所述高压电源。
  10. 一种串行解串器，其特征在于，包括串行器和解串器，所述串行器和所述解串器通过数据链路连接，所述串行器包括如权利要求1～9任一项所述驱动电路，所述解串器，用于从所述数据链路上接收所述串行器发送的串行信号并将所述串行信号进行解串处理以得到并行数据。
PCT/CN2019/071539 2018-01-18 2019-01-14 驱动电路以及串行解串器 WO2019141141A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810051033.7A CN110059047B (zh) 2018-01-18 2018-01-18 驱动电路以及串行解串器
CN201810051033.7 2018-01-18

Publications (1)

Publication Number Publication Date
WO2019141141A1 true WO2019141141A1 (zh) 2019-07-25

Family

ID=67301617

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/071539 WO2019141141A1 (zh) 2018-01-18 2019-01-14 驱动电路以及串行解串器

Country Status (2)

Country Link
CN (1) CN110059047B (zh)
WO (1) WO2019141141A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116208142B (zh) * 2023-05-05 2023-08-29 核芯互联科技(青岛)有限公司 差分信号驱动电路及选择差分信号驱动电路的方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1661917A (zh) * 2004-02-27 2005-08-31 罗姆股份有限公司 驱动控制电路、发光控制电路、通信装置及驱动控制方法
CN101471123A (zh) * 2007-12-27 2009-07-01 海力士半导体有限公司 半导体存储装置中的数据输出电路
CN102142273A (zh) * 2010-01-29 2011-08-03 海力士半导体有限公司 半导体集成电路
CN102769442A (zh) * 2011-05-05 2012-11-07 苹果公司 具有阻抗控制的驱动器
CN103347351A (zh) * 2013-07-30 2013-10-09 厦门大学 一种用于塑料光纤通信的光发射芯片的驱动集成电路
CN107066416A (zh) * 2016-12-20 2017-08-18 华为技术有限公司 串行通信系统的驱动电路及驱动方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7352815B2 (en) * 2003-06-23 2008-04-01 International Business Machines Corporation Data transceiver and method for equalizing the data eye of a differential input data signal
US8030968B1 (en) * 2010-04-07 2011-10-04 Intel Corporation Staged predriver for high speed differential transmitter
JP5602662B2 (ja) * 2011-03-02 2014-10-08 ルネサスエレクトロニクス株式会社 信号配線システム及びジッタ抑制回路
EP2713266B1 (en) * 2012-09-26 2017-02-01 Nxp B.V. Driver circuit
DE102015204606A1 (de) * 2015-03-13 2016-09-15 Robert Bosch Gmbh Sende- und Empfangsschaltung zum Übermitteln von differentiellen und single-ended Signalen über Übertragungsleitungen
US10042807B2 (en) * 2016-04-05 2018-08-07 Infineon Technologies Ag Differential bus receiver with four-quadrant input circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1661917A (zh) * 2004-02-27 2005-08-31 罗姆股份有限公司 驱动控制电路、发光控制电路、通信装置及驱动控制方法
CN101471123A (zh) * 2007-12-27 2009-07-01 海力士半导体有限公司 半导体存储装置中的数据输出电路
CN102142273A (zh) * 2010-01-29 2011-08-03 海力士半导体有限公司 半导体集成电路
CN102769442A (zh) * 2011-05-05 2012-11-07 苹果公司 具有阻抗控制的驱动器
CN103347351A (zh) * 2013-07-30 2013-10-09 厦门大学 一种用于塑料光纤通信的光发射芯片的驱动集成电路
CN107066416A (zh) * 2016-12-20 2017-08-18 华为技术有限公司 串行通信系统的驱动电路及驱动方法

Also Published As

Publication number Publication date
CN110059047A (zh) 2019-07-26
CN110059047B (zh) 2022-05-31

Similar Documents

Publication Publication Date Title
TWI740114B (zh) 具有自低電力待機至低頻信號傳輸之快速變換之轉發器
US8659329B2 (en) Pre-emphasis circuit and differential current signaling system having the same
JP4578316B2 (ja) 送信装置
US7352229B1 (en) Reference clock receiver compliant with LVPECL, LVDS and PCI-Express supporting both AC coupling and DC coupling
EP2181503B1 (en) Level shifter having low duty cycle distortion
US8610462B1 (en) Input-output circuit and method of improving input-output signals
US20080117994A1 (en) Use of differential pair as single-ended data paths to transport low speed data
US20040145394A1 (en) Output buffer circuit having pre-emphasis function
JP2006287797A (ja) レベル変換回路
TW200824307A (en) Low to high voltage conversion output driver and conversion method, parallel to serial transmitter and output driver for driving a serial link
JPH1093414A (ja) インタフェース回路及び信号伝送方法
US8749269B2 (en) CML to CMOS conversion circuit
WO2017219700A1 (zh) 电平转换电路及电子设备
US11139843B1 (en) SerDes driver with common-gate-based buffer to use core devices in relatively high power supply domain
WO2019141141A1 (zh) 驱动电路以及串行解串器
JP5400894B2 (ja) Ｃｍｌ信号の論理ファミリ間の変換を行うシステムおよび方法
WO2007032089A1 (ja) コモンモード電圧制御装置
JP3708897B2 (ja) 出力バッファ回路
Partovi et al. Single-ended transceiver design techniques for 5.33 Gb/s graphics applications
US11005477B2 (en) Driver circuit and control method therefor, and transmission/reception system
US7378877B2 (en) Output buffer circuit
WO2020077988A1 (zh) 电平转换电路
KR101405241B1 (ko) 데이터 통신용 송신기
GB2497188A (en) Power efficient high speed backplane driver circuit with high voltage swing
US10418976B1 (en) Charge steering transmitter

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19741643

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19741643

Country of ref document: EP

Kind code of ref document: A1