WO2023236360A1 - 一种晶体管器件及存储器 - Google Patents

一种晶体管器件及存储器 Download PDF

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Publication number
WO2023236360A1
WO2023236360A1 PCT/CN2022/114598 CN2022114598W WO2023236360A1 WO 2023236360 A1 WO2023236360 A1 WO 2023236360A1 CN 2022114598 W CN2022114598 W CN 2022114598W WO 2023236360 A1 WO2023236360 A1 WO 2023236360A1
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semiconductor channel
film layer
layer
gate
thin film
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PCT/CN2022/114598
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English (en)
French (fr)
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李泠
刘明
耿玓
段新绿
陆丛研
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中国科学院微电子研究所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/22—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a transistor device and a memory.
  • Indium Gallium Zinc Oxide As a new semiconductor material, has a higher electron mobility than amorphous silicon ( ⁇ -Si), a larger switching ratio and a smaller leakage current, which reduces power consumption when the device unit is not working, which is more conducive to reducing overall product power consumption.
  • IGZO materials are currently used as semiconductor channels in memories, there are still contradictory problems such as low operating current or difficulty in turning off. That is, increasing the operating current of the device often leads to problems of difficulty in turning off, and improves the turn-off control capability. , often resulting in lower operating current.
  • the present disclosure proposes a transistor device and a memory that can adjust and balance the turn-off control capability of the semiconductor channel and the mobility of the semiconductor channel.
  • a transistor device including: a gate; a semiconductor channel circumferentially arranged outside the surface of the gate; the semiconductor channel includes a multi-layer thin film structure; wherein, the The multi-layer thin film structure includes: an indium oxide thin film layer, a gallium oxide thin film layer and a zinc oxide thin film layer; a first source and drain electrode arranged at the first end of the semiconductor channel; and a second source and drain electrode arranged at the first end of the semiconductor channel. the second end of the semiconductor channel.
  • a memory including: the transistor device according to any one of the foregoing first aspects.
  • a transistor device and a memory are provided, wherein the transistor device includes: a gate; a semiconductor channel that is arranged around the surface of the gate; the semiconductor channel includes a multi-layer thin film structure; wherein, the multi-layer thin film structure includes: an indium oxide thin film layer, a gallium oxide thin film layer and a zinc oxide thin film layer; a first source and drain electrode arranged at the first end of the semiconductor channel; and a second source and drain electrode arranged at at the second end of the semiconductor channel.
  • One or more embodiments of the present disclosure can accurately control the proportion of each element in indium, gallium, and zinc during the manufacturing process through layered structure design, thereby achieving the turn-off control capability of the semiconductor channel and the stability of the semiconductor channel. Mobility is adjusted and balanced.
  • Figures 1, 3, 4, and 8 respectively show schematic structural diagrams of different implementations of transistor devices according to one or more embodiments of the present disclosure
  • FIG. 2 shows a schematic structural diagram of a semiconductor channel of a transistor device in accordance with one or more embodiments of the present disclosure
  • Figure 5 shows a schematic diagram of a gate position structure of a transistor device according to one or more embodiments of the present disclosure
  • 6 and 7 respectively show schematic diagrams of the electric field distribution at the second end of the gates of different transistor devices according to one or more embodiments of the present disclosure
  • FIG. 9 shows a schematic structural diagram of a 2TOC device structure composed of transistor devices according to one or more embodiments of the present disclosure.
  • a layer/element when referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present between them. element. Additionally, if one layer/element is "on” another layer/element in one orientation, then the layer/element can be "under” the other layer/element when the orientation is reversed.
  • the transistor device 10 may also include a substrate, and the gate electrode 11, the gate insulating layer 12, the semiconductor channel 13, etc. are all disposed on the same side of the substrate; the length direction of the gate electrode 11 may be perpendicular to the substrate, or approximately perpendicular to the substrate.
  • the entire transistor device 10 has a vertical structure, which is beneficial to large-scale stacking with higher density.
  • the substrate material can be commonly used substrate materials, such as Si, SiO2, SiC, etc., or even other flexible substrate materials, without limitation.
  • the gate insulating layer 12 is provided around the side of the gate electrode 11 .
  • the gate insulating layer 12 can cover the surface of the gate electrode 11 to achieve insulation isolation between the semiconductor channel 13 and the gate electrode 11 .
  • the gate insulating layer 12 can be made of HfO, HfAlO, Al 2 O 3 and other materials.
  • the gate insulating layer 12 can also be made of a combination of multiple layers of films of different materials, without limitation.
  • the gate insulating layer 12 can completely wrap the second end of the gate electrode 11 , which is beneficial to improving the resistance of the gate electrode 11 to the semiconductor channel 13 control performance; it can also only surround the surface of the second end of the grid 11 (without wrapping the end surface), which is beneficial to connecting wires under the grid 11.
  • the semiconductor channel 13 in this embodiment can be implemented using IGZO material.
  • the semiconductor channel 13 includes a multi-layer thin film structure; the multi-layer thin film structure includes: an indium oxide thin film layer 131, a gallium oxide thin film layer 132 and a zinc oxide thin film layer 133.
  • the indium oxide film layer 131, the gallium oxide film layer 132 and the zinc oxide film layer 133 can be alternately stacked to form a multi-layer film structure. The order of alternating stacks is not limited.
  • the multilayer thin film structure includes multiple unit structure layers, which are stacked in sequence.
  • Each unit structure layer 130 includes: an indium oxide film layer 131, a gallium oxide film layer 132, and a zinc oxide film layer 133. .
  • the indium oxide thin film layer 131, the gallium oxide thin film layer 132 and the zinc oxide thin film layer 133 are cyclically stacked, thereby effectively improving the uniformity of carriers in the semiconductor channel 13 and ensuring better mobility.
  • the proportion of indium oxide material in the unit structure layer 130 is 3/5 to 3/4.
  • the indium oxide material in this proportion can achieve a larger open state under the same gate voltage condition of the transistor device 10 . state current.
  • the proportions of gallium oxide material and zinc oxide material in the unit structure layer 130 can be set to be the same, so as to ensure a larger on-state current and at the same time ensure that the gate 11 has better turn-off of the semiconductor channel 13 performance to achieve a balance between high current and easy turn-off of the semiconductor channel 13. That is to say, in some possible implementations, the ratio range of InO x : GaO x : ZnO x can be determined to be 3:1:1 to 6:1:1, for example, 5:1:1.
  • the semiconductor channel 13 further includes an outer thin film layer; the outer thin film layer is disposed on the surface of the multi-layer thin film structure closest to the gate electrode 11 , and the material of the outer thin film layer is indium oxide. That is to say, after the last unit structure layer 130 is deposited, an additional layer of indium oxide can be deposited to obtain better interface characteristics and improve the sub-threshold characteristics and operating current of the device. For example, if the film structure of the unit structure layer 130 closest to the gate electrode 11 is ZnO x , then an additional layer of InO x is provided on ZnO x to obtain better interface characteristics.
  • the thickness of the semiconductor channel 13 is 3 nm to 5 nm, thereby ensuring that the semiconductor channel 13 has good mobility and is also conducive to the miniaturization and high-density large-scale array of the entire transistor device 10 .
  • the first source and drain electrode 151 may be disposed around a side of the gate insulating layer 12 away from the gate electrode 11 and connected to the first end of the semiconductor channel 13; the second source and drain electrode 152 may be disposed around the side of the gate insulating layer 12 away from the gate electrode 11.
  • the gate insulating layer 12 is on one side away from the gate electrode 11 and connected to the second end of the semiconductor channel 13, as shown in FIG. 3 .
  • the first source and drain electrode 151 may be disposed around a side of the semiconductor channel 13 away from the gate electrode 11
  • the second source and drain electrode 152 may be disposed around a side of the semiconductor channel 13 away from the gate electrode 11 , As shown in Figure 4.
  • This implementation method can achieve a larger contact area between the source and drain electrodes and the semiconductor channel 13, which is beneficial to the conduction efficiency of carriers.
  • the gate electrode 11 also extends into the second source and drain electrode 152 , the second end of the gate electrode 11 can form an electric field in a direction away from the first end of the gate electrode 11 (for convenience of description below, this embodiment (called the first electric field in this embodiment), and at the same time, an electric field can be formed in the direction of the semiconductor channel 13 on the side (for the convenience of subsequent description, it is called the second electric field in this embodiment), and the semiconductor channel 13 in these two directions 13 is connected to the source and drain.
  • the length of the gate 11 extending into the second source and drain electrode 152 can be set to not less than 10 nm, so that there is a second electric field of sufficient width to ensure that the second end of the gate 11 can control the semiconductor channel 13.
  • the semiconductor channel 13 in contact with the two source and drain electrodes 152 has better control performance; at this time, the peripheral diameter of the end of the semiconductor channel 13 extending into the second source and drain electrode 152 can be controlled to less than 50 nm, thereby achieving device shrinkage.
  • the peripheral diameter of the second end of the semiconductor channel 13 can also be set larger, so that the first electric field generated by the gate 11 can sufficiently cover the second source and drain 152 , can also achieve better control of the gate 11, as shown in Figures 7 and 8; and at this time, the control ability of the gate 11 on the second end of the semiconductor junction channel is mainly determined by the first electric field. Therefore, the gate The length of 11 extending into the second source and drain electrode 152 may not be limited to less than 10 nm.
  • the first source-drain electrode 151 and the second source-drain electrode 152 can be formed of materials such as TiN, W, and Mo.
  • the work functions of these materials can be better adapted to IGZO materials and have better oxidation resistance.
  • the gate electrode 11 of the transistor device 10 in this embodiment penetrates upward and the second source and drain electrode 152 is located below, it is easy to form a 2T0C device structure and occupies a small area. As shown in 9, a The gate electrode 11 of the transistor device is connected to the second source and drain electrode 152 of another transistor device.
  • a transistor device provided in one or more embodiments of the present disclosure includes: a gate; a semiconductor channel that is arranged around the surface of the gate; the semiconductor channel includes a multi-layer thin film structure; wherein , the multi-layer thin film structure includes: an indium oxide thin film layer, a gallium oxide thin film layer and a zinc oxide thin film layer; a first source and drain electrode, arranged at the first end of the semiconductor channel; and a second source and drain electrode, arranged at The second end of the semiconductor channel.
  • One or more embodiments of the present disclosure can accurately control the proportion of each element in indium, gallium, and zinc during the manufacturing process through layered structure design, thereby achieving the turn-off control capability of the semiconductor channel and the stability of the semiconductor channel. Mobility is adjusted and balanced.
  • another embodiment of the present disclosure also provides a memory, including: the transistor device described in any of the previous embodiments.
  • the embodiments of the present disclosure provide a memory that uses the transistor device in the previous embodiments. Therefore, the beneficial effects of the memory can be referred to the explanations in the previous embodiments, and will not be described again in this embodiment. .
  • the specific process when the transistor device and each structure in the memory is manufactured can be implemented using existing process technology, and is not limited in this embodiment.

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Abstract

本公开公开了一种晶体管器件及存储器，其中晶体管器件包括：栅极；半导体沟道，环绕设置在所述栅极的表面外；所述半导体沟道包括多层薄膜结构；其中，所述多层薄膜结构中包括：氧化铟薄膜层、氧化镓薄膜层和氧化锌薄膜层；第一源漏极，设置在所述半导体沟道的第一端；以及第二源漏极，设置在所述半导体沟道的第二端。本公开可实现对半导体沟道的关断控制能力和半导体沟道的迁移率进行调整和平衡。

Description

一种晶体管器件及存储器
相关申请的交叉引用
本公开要求于2022年06月10日提交、申请号为202210657914X且名称为“一种晶体管器件及存储器”的中国专利申请的优先权，其全部内容通过引用合并于此。
技术领域
本公开涉及半导体技术领域，尤其涉及一种晶体管器件及存储器。
背景技术
氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为一个新型的半导体材料，因其有着比非晶硅(α-Si)更高的电子迁移率，以及有着较大的开关比和较小的漏电流，这使得器件单元不工作的时候功耗降低，更加有利于降低整体产品功耗。但是目前IGZO材料作为半导体沟道应用于存储器中时，仍然存在着工作电流较低或难以关断的矛盾问题，即提高了器件工作电流往往会出现难以关断的问题，提高了关断控制能力，往往导致工作电流较低。
因此，如何较好的平衡晶体管器件的工作电流和对半导体沟道的关断控制能力成为了目前亟待解决的问题。
发明内容
鉴于上述问题，本公开提出了一种晶体管器件及存储器，可实现对半导体沟道的关断控制能力和半导体沟道的迁移率进行调整和平衡。
在本公开的第一方面，提供了一种晶体管器件，包括：栅极；半导体沟道，环绕设置在所述栅极的表面外；所述半导体沟道包括多层薄膜结构；其中，所述多层薄膜结构中包括：氧化铟薄膜层、氧化镓薄膜层和氧化锌薄膜层；第一源漏极，设置在所述半导体沟道的第一端；以及第二源 漏极，设置在所述半导体沟道的第二端。
在本公开的第二方面，提供了一种存储器，包括：前述第一方面中任一所述的晶体管器件。
在本公开的一个或多个实施例中提供了一种晶体管器件及存储器，其中晶体管器件包括：栅极；半导体沟道，环绕设置在栅极的表面外；半导体沟道包括多层薄膜结构；其中，多层薄膜结构中包括：氧化铟薄膜层、氧化镓薄膜层和氧化锌薄膜层；第一源漏极，设置在所述半导体沟道的第一端；以及第二源漏极，设置在半导体沟道的第二端。本公开的一个或多个实施例通过分层结构设计可在制造过程中准确的控制铟、镓及锌中每种元素的比例，从而实现对半导体沟道的关断控制能力和半导体沟道的迁移率进行调整和平衡。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1、图3、图4、图8分别示出了依据本公开内容的一个或多个实施方式的晶体管器件不同实现方式的结构示意图；
图2示出了依据本公开内容的一个或多个实施方式中的晶体管器件的半导体沟道的结构示意图；
图5示出了依据本公开内容的一个或多个实施方式中的晶体管器件的栅极位置结构示意图；
图6、图7分别示出了依据本公开内容的一个或多个实施方式中的不同晶体管器件的栅极的第二端电场分布示意图；
图9示出了依据本公开内容的一个或多个实施方式中的晶体管器件组成的2T0C器件结构的结构示意图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
请参阅图1，在本实施例中提供的一种晶体管器件10，包括：栅极11、栅绝缘层12、半导体沟道13、电极绝缘层14、第一源漏极151和第二源漏极152。
栅极11，可设置为柱状结构，该柱状结构的两端的直径可以不同。栅极11的垂直于长度方向的截面可以是圆形、椭圆形、方形等形状不做限制。例如，在一些实现方式中可采用非圆形的形状，可保证具有较大表面积，提高栅极11的控制性能。另外，介于工艺成本可采用圆形截面的栅极11，或椭圆形等近视于圆形截面的栅极11，实现较好的栅极控制性 能，避免提升制造成本。栅极11的材料可采用ITO、IZO、TiN、等等，可具备较好的导电性能，另外也可采用有利于ALD(Atomic layer deposition，原子层沉积)工艺生长的金属或其他导电性强的氧化物。
在一些实现方式中，晶体管器件10还可包括衬底，栅极11、栅绝缘层12、半导体沟道13等均设置在衬底的同一侧；栅极11的长度方向可垂直于衬底，或近似的垂直于衬底。使得整个晶体管器件10为垂直结构，有利于进行更高密度的大规模堆叠。衬底材料可采用常用的衬底材料，例如Si、SiO2、SiC、等等，甚至其他柔性衬底材料，不做限制。
栅绝缘层12，环绕设置在栅极11侧面。在一些实现方式中，栅绝缘层12可包覆在栅极11的表面，实现半导体沟道13和栅极11之间绝缘隔离。栅绝缘层12可采用HfO、HfAlO、Al 2O 3等材料实现，当然栅绝缘层12也可是采用多层不同材料薄膜组合而成，不做限制。当半导体沟道13的第一端为远离衬底的一端时，则一些实现方式中，栅绝缘层12可完全将栅极11第二端包裹，有利于提高栅极11对半导体沟道13的控制性能；也可仅仅环绕在栅极11第二端的表面(不包裹端面)，有利于对栅极11下穿接线。
半导体沟道13，环绕设置在栅极11的表面外。在一些实现方式中，可环绕在栅绝缘层12远离栅极11的一侧。该结构使得半导体沟道13和栅极11之间形成CAA结构(Channel-All-Around，沟道全环绕)，即半导体沟道13环绕在栅极11外侧，这样可有效的增加半导体沟道13的面积，提升半导体沟道13载流子数量，提高了电流传导效率；同时，半导体沟道13由于是全环绕在栅极11外侧的，有效的增加了半导体沟道13与栅极11相对应的面积，从而提高了栅极11对半导体沟道13的控制性能。该种设计结构，在有限的体积下增加了栅极11对半导体沟道13的控制面积，以及半导体沟道13的面积，可实现更小的微缩。
在一些实现方式中，本实施例中半导体沟道13的可采用IGZO材料实现。请参阅图2，在一些实现方式中，半导体沟道13包括多层薄膜结 构；多层薄膜结构中包括：氧化铟薄膜层131、氧化镓薄膜层132和氧化锌薄膜层133。具体的，可由氧化铟薄膜层131、氧化镓薄膜层132和氧化锌薄膜层133交替层叠形成多层薄膜结构。交替层叠的顺序不做限制。铟的比例高的半导体沟道13在相同的栅压下可以达到更大的开态电流，但器件的阈值电压比较靠负，也就是说器件的阈值电压小于0V，且距离0V较远；铟的比例低的半导体沟道13晶体管阈值电压相关对更靠正，也就是说器件的阈值电压大于0V，或者说小于0V但距离0V较近，但器件开态电流会小一些。需要说明的是，根据对器件预期性能的要求的不同，判断靠正或靠负的基准可能会发生变化；例如，可以将-1V作为基准，大于-1V为靠正，小于-1V为靠负。因此，在本实施例中通过分层结构设计可在制造过程中准确的控制铟、镓及锌中每种元素的比例，从而实现对半导体沟道13的关断控制能力和半导体沟道13的迁移率进行调整和平衡。
在一些实现方式中，多层薄膜结构包括多个单元结构层，多个单元结构层依次堆叠，每个单元结构层130包括：氧化铟薄膜层131、氧化镓薄膜层132和氧化锌薄膜层133。通过该结构实现氧化铟薄膜层131、氧化镓薄膜层132和氧化锌薄膜层133循环堆叠，从而有效的提高了半导体沟道13内载流子的均匀性，保证较好的迁移率。
在一些实现方式中，该单元结构层130由远离所述栅极11的方向靠近所述栅极11的方向依次堆叠为：氧化铟薄膜层131、氧化镓薄膜层132和氧化锌薄膜层133；还可堆叠为：氧化锌薄膜层133、氧化铟薄膜层131和氧化镓薄膜层132；还可堆叠为：氧化镓薄膜层132、氧化铟薄膜层131和氧化锌薄膜层133；氧化镓薄膜层132、氧化锌薄膜层133和氧化铟薄膜层131。这样的堆叠结构可保证氧化铟薄膜层131和氧化镓薄膜层132相邻，从而可有效抑制氧空位的形成，提高器件的可控性。
在一些实现方式中，单元结构层130中氧化铟材料的占比为3/5～3/4，该比例下的氧化铟材料可在晶体管器件10相同的栅极电压条件下达到更大的开态电流。可选的，可设置单元结构层130中的氧化镓材料和氧化锌 材料的占比相同，这样在保证达到较大开态电流的同时保证栅极11对半导体沟道13具有较好的关断性能，实现半导体沟道13的大电流和易关断之间的平衡。也就是说，在一些可能的实现方式中，可将InO x：GaO x：ZnO x的比例范围确定在3:1:1～6:1:1，例如为5:1:1。
在一些实现方式中，本实施例中每层氧化铟薄膜层131、每层氧化镓薄膜层132和每层氧化锌薄膜层133的厚度均小于1埃。这样即使是交替沉积不同层的化合物，最终形成的多元素的半导体薄膜也并不能看出分层结构，仍然可以被等效认为是这几种元素的完全混合物，保证IGZO材料的其他特性。
在一些实现方式中，半导体沟道13还包括外层薄膜层；外层薄膜层设置在多层薄膜结构的最靠近栅极11的表面，外层薄膜层的材料为氧化铟。也就是说，可在沉积完最后一个单元结构层130后，额外再沉积一层氧化铟，从而获得更好的界面特性，提高器件的亚阈值特性和工作电流。例如，最靠近栅极11的单元结构层130的薄膜结构为ZnO x，则在ZnO x上再额外设置一层InO x，从而获得更好的界面特性。
在一些实现方式中，半导体沟道13的厚度为3nm～5nm，从而保证半导体沟道13具有较好的迁移率，同时也有利于整个晶体管器件10的微缩和高密度大规模阵列。
第一源漏极151，设置在半导体沟道13的第一端，并与半导体沟道13连接；第二源漏极152，设置在半导体沟道13的第二端，并于半导体沟道13连接。半导体沟道13的第一端可为远离衬底的一端，半导体沟道13的第二端可为靠近衬底的一端。电极绝缘层14环绕设置在半导体沟道13远离栅极11的一侧，并且位于第一源漏极151和第二源漏极152之间；电极绝缘层14用于隔离第一源漏极151和第二源漏极152，避免第一源漏极151和第二源漏极152之间短路。
在一些实现方式中，第一源漏极151可环绕设置在栅绝缘层12远离栅极11的一侧，并与半导体沟道13的第一端连接；第二源漏极152可 环绕设置在栅绝缘层12远离栅极11的一侧，并与半导体沟道13的第二端连接，如图3所示。另一些实现方式中，第一源漏极151可环绕设置在半导体沟道13的远离栅极11的一侧，第二源漏极152设置在半导体沟道13的远离栅极11的一侧，如图4所示。该种实现方式可实现源漏极与半导体沟道13之间形成更大的接触面积；有利于载流子的传导效率。
在一些实现方式中，第二源漏极152包裹设置在半导体沟道13的第二端。也就是说，第二源漏极152将半导体沟道13第二端的栅绝缘层12包裹；半导体沟道13的第二端和栅极11的第二端伸入至第二源漏极152内，如图5所示。栅极11和半导体沟道13深入第二源漏极152内，半导体沟道13和第二源漏极152之间的接触面积会更大。
请参阅图6，由于栅极11也伸入第二源漏极152内，栅极11的第二端可向远离栅极11第一端的方向形成电场(为了便于后文表述，本实施例中称之为第一电场)，同时可向侧面的半导体沟道13方向形成电场(为了便于后文表述，本实施例中称之为第二电场)，而该两个方向上是半导体沟道13与源漏极连接的位置。因此，栅极11和半导体沟道13伸入第二源漏极152的结构，可进一步的增强栅极11对半导体沟道13上与第二源漏极152接触位置的控制能力，从而提升整个器件的性能，避免产生漏电流。
为了保证栅极11第二端对半导体沟道13的控制能力，可将栅极11伸入第二源漏极152的长度设置为不小于10nm，从而有足够宽度的第二电场，保证对第二源漏极152接触的半导体沟道13的控制性能更好；此时，可将半导体沟道13伸入第二源漏极152的端部的外围直径控制在小于50nm，实现器件微缩。当然，在一些实现方式中，还可将半导体沟道13的第二端端部的外围直径设置的更大，从而使得栅极11产生的第一电场足够较好的覆盖第二源漏极152，同样可实现较好的栅极11控制，如图7和图8所示；并且，此时栅极11对半导体结沟道的第二端的控制能力主要有第一电场决定，因此，栅极11伸入第二源漏极152的长度可不限定 于小于10nm。
在一些实现方式中，若采用了更大外围直径的半导体沟道13，可能会造成器件体积难以缩小；因此，为了保证栅极11的第二端对半导体沟道13的第二端具有良好的控制性能，可控制半导体沟道13伸入第二源漏极152的端部的外围直径与栅极11伸入第二源漏极152的长度满足关系：H≥0.5×(120nm-D)，其中，H为栅极11伸入第二源漏极152的长度，D为半导体沟道13伸入第二源漏极152的端部的外围直径，并且此时可控制D≤100nm。从而实现第一电场和第二电场之间的平衡，保证栅极11对半导体沟道13第二端的控制性能的同时，有利于器件进一步的微缩、做小，如图5所示。不仅如此，当将半导体沟道13伸入第二源漏极152且并未穿透时，半导体沟道13靠近第二源漏极152的端部的端面和侧面均能够和第二源漏极152形成良好的接触，有效的降低了接触电阻；另外，当将半导体沟道13的第二端端部直径设计得更大时，可进一步的增加半导体沟道13与第二源漏极152的接触面积，降低接触电阻。
在一些实现方式中，第二源漏极152可环绕设置在半导体沟道13的远离栅极11的表面，并位于半导体沟道13的第二端。该种结构可便于在制造过程中将第二源漏极152刻蚀至穿透，从而在孔内沉积半导体沟道13、栅绝缘层12和栅极11，免于对第二源漏极152进行刻蚀厚度的控制。
第一源漏极151和第二源漏极152可采用TiN、W、Mo等材料形成，这些材料的功函数可较好的与IGZO材料相适应，并且具备较好的抗氧化性能。
还需要说明的是，由于本实施例中的晶体管器件10由于栅极11向上穿透，且第二源漏极152位于下方，可便于形成2T0C器件结构，占用面积小，如9所示，一晶体管器件的栅极11与另一晶体管器件的第二源漏极152连接。
综上所述，本公开的一个或多个实施例中提供的一种晶体管器件，包括：栅极；半导体沟道，环绕设置在栅极的表面外；半导体沟道包括多 层薄膜结构；其中，多层薄膜结构中包括：氧化铟薄膜层、氧化镓薄膜层和氧化锌薄膜层；第一源漏极，设置在所述半导体沟道的第一端；以及第二源漏极，设置在半导体沟道的第二端。本公开的一个或多个实施例通过分层结构设计可在制造过程中准确的控制铟、镓及锌中每种元素的比例，从而实现对半导体沟道的关断控制能力和半导体沟道的迁移率进行调整和平衡。
基于同一发明构思，在本公开的又一实施例中还提供了一种存储器，包括：前述实施例中任一所述的晶体管器件。
需要说明的是，本公开的实施例提供的一种存储器，其采用了前述实施例中的晶体管器件，因此该存储器具备的有益效果可参照前述实施例中的阐述，本实施例中不再赘述。另外，晶体管器件以及存储器中每个结构被制作时的具体工艺实现可采用现有的工艺技术，本实施例中不作限制。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (10)

  1. 一种晶体管器件，包括：
    栅极；
    半导体沟道，环绕设置在所述栅极的表面外；所述半导体沟道包括多层薄膜结构；其中，所述多层薄膜结构中包括：氧化铟薄膜层、氧化镓薄膜层和氧化锌薄膜层；
    第一源漏极，设置在所述半导体沟道的第一端；以及
    第二源漏极，设置在所述半导体沟道的第二端。
  2. 如权利要求1所述的晶体管器件，其中，所述多层薄膜结构包括多个单元结构层，所述多个单元结构层依次堆叠，每个所述单元结构层包括：氧化铟薄膜层、氧化镓薄膜层和氧化锌薄膜层。
  3. 如权利要求2所述的晶体管器件，其中，所述单元结构层中的膜层由远离所述栅极的方向靠近所述栅极的方向依次堆叠为：氧化铟薄膜层、氧化镓薄膜层和氧化锌薄膜层。
  4. 如权利要求2所述的晶体管器件，其中，所述单元结构层中氧化铟材料的占比为
    Figure PCTCN2022114598-appb-100001
  5. 如权利要求2所述的晶体管器件，其中，所述单元结构层中氧化镓材料和氧化锌材料的占比相同。
  6. 如权利要求2所述的晶体管器件，其中，每层所述氧化铟薄膜层、每层所述氧化镓薄膜层和每层氧化锌薄膜层的厚度均小于1埃。
  7. 如权利要求1所述的晶体管器件，其中，所述半导体沟道还包括外层薄膜层；所述外层薄膜层设置在所述多层薄膜结构的最靠近所述栅极的表面，所述外层薄膜层的材料为氧化铟。
  8. 如权利要求1所述的晶体管器件，其中，所述半导体沟道的厚度为3nm～5nm。
  9. 如权利要求1所述的晶体管器件，其中，所述第一源漏极环绕设置在所述半导体沟道的远离所述栅极的一侧；所述第二源漏极设置在所述半导体沟道的远离所述栅极的一侧。
  10. 一种存储器，包括：权利要求1-9中任一所述的晶体管器件。
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