WO2023236359A1 - 一种晶体管器件及存储器 - Google Patents

一种晶体管器件及存储器 Download PDF

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WO2023236359A1
WO2023236359A1 PCT/CN2022/114595 CN2022114595W WO2023236359A1 WO 2023236359 A1 WO2023236359 A1 WO 2023236359A1 CN 2022114595 W CN2022114595 W CN 2022114595W WO 2023236359 A1 WO2023236359 A1 WO 2023236359A1
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gate
source
semiconductor channel
drain electrode
electrode
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PCT/CN2022/114595
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English (en)
French (fr)
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李泠
刘明
耿玓
段新绿
陆丛研
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中国科学院微电子研究所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a transistor device and a memory.
  • Fin Field Effect Transistor Fin Field Effect Transistor
  • the present disclosure proposes a transistor device and a memory, which enhances the gate's ability to control the semiconductor channel and is conducive to further shrinking the device size.
  • a first aspect of the present disclosure provides a transistor device, including: a gate; a gate insulating layer surrounding and disposed on the side of the gate; and a semiconductor channel surrounding and disposed on a side of the gate insulating layer away from the gate.
  • a transistor device including: a gate; a gate insulating layer surrounding and disposed on the side of the gate; and a semiconductor channel surrounding and disposed on a side of the gate insulating layer away from the gate.
  • one side a first source and drain electrode, which is arranged around the side of the gate insulating layer away from the gate electrode and is located at the first end of the gate electrode; and a second source and drain electrode, which is arranged on the gate electrode.
  • the side of the insulating layer away from the gate electrode is located at the second end of the gate electrode.
  • a second aspect of the present disclosure provides a memory including the transistor device according to any of the preceding embodiments.
  • One or more embodiments of the present disclosure provide a transistor device and a memory, wherein in the transistor device, the gate insulating layer is arranged around the side of the gate; the semiconductor channel is arranged around the side of the gate insulating layer away from the gate; The first source and drain electrodes are arranged around the side of the gate insulating layer away from the gate electrode and located at the first end of the gate electrode; the second source and drain electrodes are arranged around the side of the gate insulating layer away from the gate electrode and located at the gate electrode. The second end of the pole.
  • the composed transistor device structure forms a semiconductor channel that completely surrounds the gate, which increases the area corresponding to the semiconductor channel and the gate, effectively enhances the gate's ability to control the semiconductor channel, and is conducive to further shrinking the device size.
  • the semiconductor The channel can have a larger area, increasing the number of carriers and improving performance.
  • Figures 1, 2, 3 and 7 respectively show different structural schematic diagrams of transistor devices according to one or more embodiments of the present disclosure
  • Figure 4 shows a schematic diagram of a gate position structure of a transistor device according to one or more embodiments of the present disclosure
  • 5 and 6 respectively show schematic diagrams of electric field distribution at the second end of the gate of different transistor devices according to one or more embodiments of the present disclosure
  • FIG. 8 shows a schematic structural diagram of a semiconductor channel of a transistor device in accordance with one or more embodiments of the present disclosure
  • FIG. 9 shows a schematic structural diagram of a 2TOC device structure composed of transistor devices according to one or more embodiments of the present disclosure.
  • a layer/element when referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present between them. element. Additionally, if one layer/element is "on” another layer/element in one orientation, then the layer/element can be "under” the other layer/element when the orientation is reversed.
  • an embodiment of the present disclosure provides a transistor device 10 .
  • the transistor device 10 includes: a gate electrode 11 , a gate insulating layer 12 , a semiconductor channel 13 , a first source-drain electrode 151 and a second source-drain electrode 151 . Extreme 152.
  • the gate insulating layer 12 is provided around the side of the gate electrode 11; it can be understood that the gate insulating layer 12 can be attached to the surface of the gate electrode 11, that is, the gate insulating layer 12 is wrapped around the surface of the gate electrode 11; Other film layer structures may also exist between the gate electrode 11 and the gate insulating layer 12 without limitation.
  • the semiconductor channel 13 is provided around the side of the gate insulating layer 12 away from the gate electrode 11 ; for example, it can be wrapped around the side of the gate insulating layer 12 away from the gate electrode 11 .
  • the first source and drain electrode 151 is disposed around the side of the gate insulating layer 12 away from the gate electrode 11 and is located at the first end of the gate electrode 11; and the second source and drain electrode 152 is disposed on the side of the gate insulating layer 12 away from the gate electrode. one side of gate 11 and located at the second end of gate 11.
  • a CAA (Channel-All-Around) structure is formed between the semiconductor channel 13 and the gate 11, that is, the semiconductor channel 13 surrounds the outside of the gate 11, which can effectively increase the number of semiconductors.
  • the area of the channel 13 increases the number of carriers in the semiconductor channel 13 and improves the current conduction efficiency; at the same time, because the semiconductor channel 13 completely surrounds the outside of the gate 11, it effectively increases the distance between the semiconductor channel 13 and the gate. 11 corresponding area, thereby improving the control ability of the gate electrode 11 on the semiconductor channel 13 .
  • This design structure increases the control area of the semiconductor channel 13 by the gate 11 and the area of the semiconductor channel 13 in a limited volume, and can achieve smaller shrinkage.
  • the contact method between the semiconductor channel 13 and the first source-drain electrode 151 and the second source-drain electrode 152 can be achieved in at least two ways, as follows:
  • first source-drain electrode 151 and the second source-drain electrode 152 are both arranged around the side of the gate insulating layer 12 away from the gate electrode 11; the first source-drain electrode 151 is connected to the semiconductor trench. The first end of the channel 13 is connected, and the second source and drain electrode 152 is connected to the second end of the semiconductor channel 13 . That is to say, the first source-drain electrode 151 and the second source-drain electrode 152 are connected to the ends of the semiconductor channel 13, as shown in Figure 2;
  • first source and drain electrode 151 can be disposed around the surface of the semiconductor channel 13 away from the gate 11 and located at the first end of the semiconductor channel 13; the second source and drain electrode 152 is disposed on the surface of the semiconductor channel 13 away from the gate 11 and located at the second end of the semiconductor channel 13, as shown in FIG. 3 .
  • This implementation method can achieve a larger contact area between the source and drain electrodes and the semiconductor channel 13, which is beneficial to the conduction efficiency of carriers.
  • the patterning mask process can be reduced, and the semiconductor channel 13 does not need to be etched.
  • the second source and drain electrode 152 is wrapped around the second end of the semiconductor channel 13 . That is to say, the second source and drain electrode 152 wraps the gate insulating layer 12 at the second end of the semiconductor channel 13 , and the second end of the semiconductor channel 13 and the second end of the gate electrode 11 extend into the second source and drain electrode 152 ,As shown in Figure 4.
  • the gate electrode 11 and the semiconductor channel 13 extend into the second source and drain electrode 152, and the contact area between the semiconductor channel 13 and the second source and drain electrode 152 will be larger.
  • the gate electrode 11 is also deep into the second source and drain electrode 152 , the second end of the gate electrode 11 can form an electric field in a direction away from the first end of the gate electrode 11 (for convenience of description below, in this embodiment, It is called the first electric field 21), and at the same time, an electric field can be formed in the direction of the semiconductor channel 13 on the side (for convenience of description later, it is called the second electric field 22 in this embodiment), and the two directions are the semiconductor trench.
  • the channel 13 is connected to the source and drain. Therefore, the gate 11 and the semiconductor channel 13 extend into the second source and drain 152, which can further enhance the connection between the gate 11 and the second source and drain on the semiconductor channel 13. 152 contact position control capabilities, thereby improving the performance of the entire device and avoiding leakage current.
  • the length of the gate 11 extending into the second source and drain electrode 152 can be set to no less than 10 nm, so that the second end of the gate 11 has a sufficient width.
  • the second electric field 22 ensures better control performance of the semiconductor channel 13 in contact with the second source and drain electrode 152; at this time, the peripheral diameter of the end of the semiconductor channel 13 extending into the second source and drain electrode 152 can be controlled to be less than 50nm, achieving device shrinkage.
  • the peripheral diameter of the second end of the semiconductor channel 13 can also be set larger, as shown in FIGS.
  • the length of the electrode 11 extending into the second source and drain electrode 152 may not be limited to less than 10 nm.
  • the peripheral diameter of the end of the semiconductor channel 13 extending into the second source-drain electrode 152 and the length of the gate electrode 11 extending into the second source-drain electrode 152 can be controlled to satisfy the relationship: H ⁇ 0.5 ⁇ (120nm–D), Wherein, H is the length of the gate electrode 11 extending into the second source and drain electrode 152, and D is the peripheral diameter of the end of the semiconductor channel 13 extending into the second source and drain electrode 152; and at this time, D can be controlled to ⁇ 100 nm.
  • the second source and drain electrode 152 is disposed around a surface of the semiconductor channel 13 away from the gate electrode 11 and is located at the second end of the semiconductor channel 13 .
  • This structure can facilitate etching the second source and drain electrode 152 until it penetrates during the manufacturing process, as shown in FIG. 3 , thereby depositing the semiconductor channel 13 , the gate insulating layer 12 and the gate electrode 11 in the hole to avoid damage to the hole.
  • the second source and drain electrode 152 controls the etching thickness.
  • the transistor device 10 may further include: an electrode insulating layer; the electrode insulating layer surrounds a surface of the semiconductor channel 13 away from the gate 11 and is located at the first source-drain electrode 151 and the second source-drain electrode 151 . 152; the electrode insulation layer is used to isolate the first source-drain electrode 151 and the second source-drain electrode 152.
  • the transistor device 10 may further include a substrate disposed on a side of the second source-drain electrode 152 away from the first source-drain electrode 151; the gate electrode 11 may be disposed perpendicular to the substrate, such that a single transistor The device 10 will occupy less area of the substrate, facilitate large-scale arrays, and reduce the size of the final product. It should be noted that vertical in this example refers to relative vertical or approximately vertical, rather than vertical in an absolute sense.
  • the substrate can use commonly used substrate materials, such as Si, SiO 2 , SiC, etc., or even other flexible substrate materials, without limitation.
  • the gate 11 can be made of ITO, IZO, TiN, etc., which can have good conductive properties. In addition, it can also be made of metal or other highly conductive oxides that are beneficial to the growth of ALD (Atomic layer deposition, atomic layer deposition) process. .
  • the gate insulating layer 12 can be made of HfO, HfAlO, Al 2 O 3 and other materials. Of course, the gate insulating layer 12 can also be made of a combination of multiple layers of films of different materials.
  • the semiconductor channel 13 can be implemented by IGZO (Indium Gallium Zinc Oxide), and can also be implemented by low leakage, high mobility derivatives such as IZTO (Indium Zinc Tin Oxide), IGZTO (Indium Gallium Zinc Tin Oxide).
  • the first source-drain electrode 151 and the second source-drain electrode 152 can be formed of materials such as TiN, W, Mo, etc. The work functions of these materials can be better adapted to the IGZO material and have better oxidation resistance.
  • the semiconductor channel 13 can be realized by IGZO material; the semiconductor channel 13 includes a multi-layer thin film structure; the multi-layer thin film structure includes: an indium oxide thin film layer 131 and a gallium oxide thin film. layer and zinc oxide film layer. Specifically, the indium oxide film layer 131, the gallium oxide film layer 132 and the zinc oxide film layer 133 can be alternately stacked to form a multi-layer film structure. The order of alternating stacks is not limited.
  • the semiconductor channel 13 with a high proportion of indium can achieve a larger on-state current under the same gate voltage, but the threshold voltage of the device is relatively negative, that is to say, the threshold voltage of the device is less than 0V and is far away from 0V; indium
  • the threshold voltage correlation of semiconductor channel 13 transistors with a low proportion is more positive, that is to say, the threshold voltage of the device is greater than 0V, or less than 0V but closer to 0V, but the on-state current of the device will be smaller.
  • the benchmark for judging positive or negative may change; for example, -1V can be used as the benchmark, greater than -1V is positive, and less than -1V is negative .
  • the proportion of each element in indium, gallium and zinc can be accurately controlled during the manufacturing process, thereby achieving the ability to control the turn-off of the semiconductor channel 13 and the semiconductor channel 13
  • the mobility is adjusted and balanced.
  • the multi-layer thin film structure includes multiple unit structure layers 130, which are stacked in sequence.
  • Each unit structure layer 130 includes: an indium oxide film layer 131, a gallium oxide film layer 132, and a zinc oxide film.
  • Layer 133 The indium oxide thin film layer 131, the gallium oxide thin film layer 132 and the zinc oxide thin film layer 133 are cyclically and alternately stacked, thereby effectively improving the uniformity of carriers in the semiconductor channel 13 and ensuring better mobility.
  • the film layers in the unit structure layer 130 are stacked sequentially from a direction away from the gate 11 to a direction close to the gate 11 as: an indium oxide film layer 131, a gallium oxide film layer 132, and a zinc oxide film layer. 133; It can also be stacked as: zinc oxide film layer 133, indium oxide film layer 131 and gallium oxide film layer 132; it can also be stacked as: gallium oxide film layer 132, indium oxide film layer 131 and zinc oxide film layer 133; gallium oxide Thin film layer 132, zinc oxide thin film layer 133 and indium oxide thin film layer 131.
  • Such a stacked structure can ensure that the indium oxide film layer 131 and the gallium oxide film layer 132 are adjacent, thereby effectively inhibiting the formation of oxygen vacancies and improving the controllability of the device.
  • the proportion of indium oxide material in the unit structure layer 130 is The indium oxide material in this ratio can achieve a larger on-state current under the same gate voltage condition of the transistor device 10; further, the proportion of gallium oxide material and zinc oxide material in the unit structure layer 130 can be set to be the same, This ensures that the gate 11 has better turn-off performance for the semiconductor channel 13 while ensuring a larger on-state current, thereby achieving a balance between the large current and easy turn-off of the semiconductor channel 13 . That is to say, in some possible implementations, the ratio range of InO x : GaO x : ZnO x can be determined to be 3:1:1 to 6:1:1, for example, 5:1:1.
  • each indium oxide film layer 131, each gallium oxide film layer 132, and each zinc oxide film layer 133 is less than 1 angstrom. In this way, even if different layers of compounds are alternately deposited, the final multi-element semiconductor film cannot see a layered structure, and can still be considered as a complete mixture of these elements, ensuring other characteristics of the IGZO material.
  • the semiconductor channel 13 also includes an outer thin film layer; the outer thin film layer is disposed on the surface of the multi-layer thin film structure closest to the gate electrode 11 , and the material of the outer thin film layer is indium oxide. That is to say, after the last unit structure layer 130 is deposited, an additional layer of indium oxide can be deposited to obtain better interface characteristics and improve the sub-threshold characteristics and operating current of the device. For example, if the film structure of the unit structure layer 130 closest to the gate electrode 11 is ZnO x , then an additional layer of InO x is provided on the ZnO x , as shown in Figure 8, to obtain better interface characteristics.
  • the thickness of the semiconductor channel 13 is 3 nm to 5 nm, thereby ensuring that the semiconductor channel 13 has good mobility and is also conducive to the miniaturization and high-density large-scale array of the entire transistor device 10 .
  • the gate electrode 11 of the transistor device 10 in this embodiment penetrates upward and the second source and drain electrode 152 is located below, it is easy to form a 2T0C device structure and occupies a small area. As shown in 9, a The gate electrode 11 of the transistor device 10 is connected to the second source and drain electrode 152 of another transistor device 10 .
  • a transistor device in one or more embodiments of the present disclosure is wrapped and arranged on the gate surface through a gate insulating layer; a semiconductor channel is wrapped and arranged on a surface of the gate insulating layer away from the gate; the first source The drain electrode is arranged around the side of the gate insulating layer away from the gate electrode and is located at the first end of the gate electrode; the second source and drain electrode is arranged on the side of the gate insulating layer away from the gate electrode and is located at the third end of the gate electrode. Two ends.
  • the composed transistor device structure forms a semiconductor channel that completely surrounds the gate, which increases the area corresponding to the semiconductor channel and the gate, effectively enhances the gate's ability to control the semiconductor channel, and is conducive to further shrinking the device size.
  • the semiconductor The channel can have a larger area, increasing the number of carriers and improving performance.
  • another embodiment of the present disclosure also provides a memory, including the transistor device described in any of the previous embodiments.
  • this embodiment provides a memory that uses the transistor device in the previous embodiment. Therefore, the beneficial effects of the memory can be referred to the description in the previous embodiment, and will not be described again in this embodiment.
  • the specific process when the transistor device and each structure in the memory is manufactured can be implemented using existing process technology, and is not limited in this embodiment.

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Abstract

本公开公开了一种晶体管器件及存储器，其中晶体管器件包括：栅极；栅绝缘层，包裹设置在栅极表面；半导体沟道，包裹设置在栅绝缘层的远离所述栅极的表面；第一源漏极，环绕设置在栅绝缘层的远离栅极的一侧，并位于栅极的第一端；以及第二源漏极，设置在栅绝缘层的远离栅极的一侧，并位于栅极的第二端。本公开组成的晶体管器件结构形成半导体沟道全环绕栅极，增加了半导体沟道和栅极对应的面积，有效的增强了栅极对半导体沟道的控制能力，有利于进一步的微缩器件尺寸，同时半导体沟道可具备更大面积，增加了载流子数量，提高了性能。

Description

一种晶体管器件及存储器
相关申请的交叉引用
本公开要求于2022年06月10日提交、申请号为2022106579493且名称为“一种晶体管器件及存储器”的中国专利申请的优先权，其全部内容通过引用合并于此。
技术领域
本公开涉及半导体技术领域，尤其涉及一种晶体管器件及存储器。
背景技术
目前集成电路不断向更细微尺寸发展，先进制程是集成电路制造中最为顶尖的若干节点之一。晶体管体积不断缩小的同时，平面结构的晶体管结构逐渐显现出较高的漏电流等缺陷。因此，为了满足较好的栅控制性能，避免漏电流，目前主流的发展方向是制作三维结构的鳍式场效晶体管(Fin Field effect transistor，FinFET)。但是目前的工艺制程在该结构上已经难以继续缩小沟道面积，整个器件结构难以进一步微缩。
因此，如何保证器件良好的栅控能力，进一步的缩小器件尺寸成为了目前亟待解决的问题。
发明内容
鉴于上述问题，本公开提出了一种晶体管器件及存储器，增强了栅极对半导体沟道的控制能力，有利于进一步的微缩器件尺寸。
本公开的第一方面提供了一种晶体管器件，包括：栅极；栅绝缘层，环绕设置在所述栅极侧面；半导体沟道，环绕设置在所述栅绝缘层的远离所述栅极的一侧；第一源漏极，环绕设置在所述栅绝缘层的远离所述栅极的一侧，并位于所述栅极的第一端；以及第二源漏极，设置在所述栅绝缘层的远离所述栅极的一侧，并位于所述栅极的第二端。
本公开的第二方面提供了一种存储器，包括前述实施例中任一所述的晶体管器件。
本公开的一个或多个实施例提供的一种晶体管器件及存储器，其中晶体管器件中，栅绝缘层环绕设置在栅极侧面；半导体沟道环绕设置在栅绝缘层的远离栅极的一侧；第一源漏极环绕设置在栅绝缘层的远离栅极的一侧，并位于栅极的第一端；第二源漏极，设置在栅绝缘层的远离栅极的一侧，并位于栅极的第二端。组成的晶体管器件结构形成半导体沟道全环绕栅极，增加了半导体沟道和栅极对应的面积，有效的增强了栅极对半导体沟道的控制能力，有利于进一步的微缩器件尺寸，同时半导体沟道可具备更大面积，增加了载流子数量，提高了性能。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1、图2、图3和图7分别示出了依据本公开内容的一个或多个实施方式的晶体管器件的不同结构示意图；
图4示出了依据本公开内容的一个或多个实施方式中的晶体管器件的栅极位置结构示意图；
图5和图6分别示出了依据本公开内容的一个或多个实施方式中的不同晶体管器件的栅极的第二端的电场分布示意图；
图8示出了依据本公开内容的一个或多个实施方式中的晶体管器件 的半导体沟道的结构示意图；
图9示出了依据本公开内容的一个或多个实施方式中的晶体管器件组成的2T0C器件结构的结构示意图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
请参阅图1，在本公开实施例种提供了一种晶体管器件10，该晶体管器件10包括：栅极11、栅绝缘层12、半导体沟道13、第一源漏极151以及第二源漏极152。
在一些实现方式中，栅绝缘层12环绕设置在栅极11的侧面；可以理解的是，栅绝缘层12可以贴附栅极11表面设置，也即栅绝缘层12包裹在栅极11表面；也可在栅极11和栅绝缘层12之间存在其他膜层结构，不做限制。半导体沟道13环绕设置在栅绝缘层12的远离栅极11的一侧；例如，可以包裹在栅绝缘层12远离栅极11的侧面上。第一源漏极151环绕设置在栅绝缘层12的远离栅极11的一侧，并位于栅极11的第一端； 以及第二源漏极152，设置在栅绝缘层12的远离栅极11的一侧，并位于栅极11的第二端。
通过上述结构设计，使得半导体沟道13和栅极11之间形成CAA(Channel-All-Around，沟道全环绕)结构，即半导体沟道13环绕在栅极11外侧，这样可有效的增加半导体沟道13的面积，提升半导体沟道13载流子数量，提高了电流传导效率；同时，半导体沟道13由于是全环绕在栅极11外侧的，有效的增加了半导体沟道13与栅极11相对应的面积，从而提高了栅极11对半导体沟道13的控制能力。该种设计结构，在有限的体积下增加了栅极11对半导体沟道13的控制面积，以及半导体沟道13的面积，可实现更小的微缩。
在本实施例中半导体沟道13和第一源漏极151以及第二源漏极152之间的接触方法至少可通过两种方式实现，如下：
一种可选的实现方式为，第一源漏极151和第二源漏极152均环绕设置在栅绝缘层12的远离所述栅极11的一侧；第一源漏极151与半导体沟道13的第一端连接，第二源漏极152与半导体沟道13的第二端连接。也就是说，第一源漏极151和第二源漏极152连接在半导体沟道13的端部，如图2所示；
另一种可选的实现方式为，第一源漏极151可环绕设置在半导体沟道13的远离栅极11的表面，并位于半导体沟道13的第一端；第二源漏极152设置在半导体沟道13的远离栅极11的表面，并位于半导体沟道13的第二端，如图3所示。该种实现方式可实现源漏极与半导体沟道13之间形成更大的接触面积；有利于载流子的传导效率。另外，在制造过程中，可以减少图形化掩膜工艺，不必对半导体沟道13进行刻蚀。
在一些实现方式中，第二源漏极152包裹设置在半导体沟道13的第二端。也就是说，第二源漏极152将半导体沟道13第二端的栅绝缘层12包裹，半导体沟道13的第二端和栅极11的第二端伸入至第二源漏极152内，如图4所示。栅极11和半导体沟道13伸入第二源漏极152内， 半导体沟道13和第二源漏极152之间的接触面积会更大。
请参阅图5，由于栅极11也深入第二源漏极152内，栅极11的第二端可向远离栅极11第一端的方向形成电场(为了便于后文表述，本实施例中称之为第一电场21)，同时可向侧面的半导体沟道13方向形成电场(为了便于后文表述，本实施例中称之为第二电场22)，而该两个方向上是半导体沟道13与源漏极连接的位置，因此，栅极11和半导体沟道13伸入第二源漏极152的结构，可进一步的增强栅极11对半导体沟道13上与第二源漏极152接触位置的控制能力，从而提升整个器件的性能，避免产生漏电流。
在一些实现方式中，为了保证栅极11第二端对半导体沟道13的控制能力，可将栅极11伸入第二源漏极152的长度设置为不小于10nm，从而有足够宽度的第二电场22，保证对第二源漏极152接触的半导体沟道13的控制性能更好；此时，可将半导体沟道13伸入第二源漏极152的端部的外围直径控制在小于50nm，实现器件微缩。当然，在另一些实现方式中，还可将半导体沟道13的第二端端部的外围直径设置的更大，如图6和图7所示；从而使得栅极11产生的第一电场21足够较好的覆盖第二源漏极152，同样可实现较好的栅极11控制；并且，此时栅极11对半导体结沟道的第二端的控制能力主要由第一电场21决定，栅极11伸入第二源漏极152的长度可不限定于小于10nm。
在一些实现方式中，若采用了更大外围直径的半导体沟道13，可能会造成器件体积难以缩小；因此，为了保证栅极11的第二端对半导体沟道13的第二端具有良好的控制性能，可控制半导体沟道13伸入第二源漏极152的端部的外围直径与栅极11伸入第二源漏极152的长度满足关系：H≥0.5×(120nm–D)，其中，H为栅极11伸入第二源漏极152的长度，D为半导体沟道13的伸入第二源漏极152的端部的外围直径；并且此时可控制D≤100nm。从而实现第一电场21和第二电场22之间的平衡，保证栅极11对半导体沟道13第二端的控制性能的同时，有利于器件进一步 的微缩、做小，如图4所示。不仅如此，当将半导体沟道13伸入第二源漏极152且并未穿透时，半导体沟道13靠近第二源漏极152的端部的端面和侧面均能够和第二源漏极152形成良好的接触，有效的降低了接触电阻；另外，当将半导体沟道13的第二端端部直径设计得更大时，可进一步的增加半导体沟道13与第二源漏极152的接触面积，降低接触电阻。
在一些实现方式中，第二源漏极152环绕设置在半导体沟道13的远离栅极11的表面，并位于半导体沟道13的第二端。该种结构可便于在制造过程中将第二源漏极152刻蚀至穿透，如图3所示，从而在孔内沉积半导体沟道13、栅绝缘层12和栅极11，免于对第二源漏极152进行刻蚀厚度的控制。
在一些实现方式中，晶体管器件10还可包括：电极绝缘层；该电极绝缘层环绕设置在半导体沟道13的远离栅极11的表面，且位于第一源漏极151和第二源漏极152之间；电极绝缘层用于隔离第一源漏极151和第二源漏极152。
在一些实现方式中，晶体管器件10还可包括衬底，衬底设置在第二源漏极152远离第一源漏极151的一侧；栅极11可垂直于该衬底设置，这样单个晶体管器件10将占用更少面积的衬底，有利于进行大规模阵列，缩小最终产品体积。需要说明的是，本示例中的垂直是指相对垂直或大致垂直，而非绝对意义上的垂直。
在一些实现方式中，衬底可采用常用的衬底材料，例如Si、SiO 2、SiC、等等，甚至其他柔性衬底材料，不做限制。栅极11可采用ITO、IZO、TiN、等等，可具备较好的导电性能，另外也可采用有利于ALD(Atomic layer deposition，原子层沉积)工艺生长的金属或其他导电性强的氧化物。栅绝缘层12可采用HfO、HfAlO、Al 2O 3等材料实现，当然栅绝缘层12也可是采用多层不同材料薄膜组合而成。半导体沟道13可采用IGZO(铟镓锌氧化物)，另外还可采用IZTO(铟锌锡氧化物)、IGZTO(铟镓锌锡氧化物)等低漏电、高迁移率的衍生物实现。第一源漏极151和第二源漏 极152可采用TiN、W、Mo等材料形成，这些材料的功函数可较好的与IGZO材料相适应，并且具备较好的抗氧化性能。
请参阅图8，对于半导体沟道13而言，半导体沟道13的可采用IGZO材料实现；半导体沟道13包括多层薄膜结构；多层薄膜结构中包括：氧化铟薄膜层131、氧化镓薄膜层和氧化锌薄膜层。具体的，可由氧化铟薄膜层131、氧化镓薄膜层132和氧化锌薄膜层133交替层叠形成多层薄膜结构。交替层叠的顺序不做限制。铟的比例高的半导体沟道13在相同的栅压下可以达到更大的开态电流，但器件的阈值电压比较靠负，也就是说器件的阈值电压小于0V，且距离0V较远；铟的比例低的半导体沟道13晶体管阈值电压相关对更靠正，也就是说器件的阈值电压大于0V，或者说小于0V但距离0V较近，但器件开态电流会小一些。需要说明的是，根据对器件预期性能的要求的不同，判断靠正或靠负的基准可能会发生变化；例如，可以将-1V作为基准，大于-1V为靠正，小于-1V为靠负。因此，在本实施例中通过该分层结构设计可在制造过程中准确的控制铟、镓及锌中每种元素的比例，从而实现对半导体沟道13的关断控制能力和半导体沟道13的迁移率进行调整和平衡。
在一些实现方式中，多层薄膜结构包括多个单元结构层130，多个单元结构层130依次堆叠，每个单元结构层130包括：氧化铟薄膜层131、氧化镓薄膜层132和氧化锌薄膜层133。通过该结构实现氧化铟薄膜层131、氧化镓薄膜层132和氧化锌薄膜层133循环交替堆叠，从而有效的提高了半导体沟道13载流子的均匀性，保证较好的迁移率。
在一些实现方式中，该单元结构层130中的膜层由远离所述栅极11的方向靠近栅极11的方向依次堆叠为：氧化铟薄膜层131、氧化镓薄膜层132和氧化锌薄膜层133；还可堆叠为：氧化锌薄膜层133、氧化铟薄膜层131和氧化镓薄膜层132；还可堆叠为：氧化镓薄膜层132、氧化铟薄膜层131和氧化锌薄膜层133；氧化镓薄膜层132、氧化锌薄膜层133和氧化铟薄膜层131。这样的堆叠结构可保证氧化铟薄膜层131和氧化镓薄膜层132 相邻，从而可有效抑制氧空位的形成，提高器件的可控性。
在一些实现方式中，单元结构层130中氧化铟材料的占比为
Figure PCTCN2022114595-appb-000001
该比例下的氧化铟材料可在晶体管器件10相同的栅极电压条件下达到更大的开态电流；进一步的，可设置单元结构层130中的氧化镓材料和氧化锌材料的占比相同，这样在保证达到较大开态电流的同时保证栅极11对半导体沟道13具有较好的关断性能，实现半导体沟道13的大电流和易关断之间的平衡。也就是说，在一些可能的实现方式中，可将InO x：GaO x：ZnO x的比例范围确定在3:1:1～6:1:1，例如为5:1:1。
进一步的，本实施例中每层氧化铟薄膜层131、每层氧化镓薄膜层132和每层氧化锌薄膜层133的厚度均小于1埃。这样即使是交替沉积不同层的化合物，最终形成的多元素的半导体薄膜也并不能看出分层结构，仍然可以被等效认为是这几种元素的完全混合物，保证IGZO材料的其他特性。
在一些可选的实现方式中，半导体沟道13还包括外层薄膜层；外层薄膜层设置在多层薄膜结构的最靠近栅极11的表面，外层薄膜层的材料为氧化铟。也就是说，可在沉积完最后一个单元结构层130后，额外再沉积一层氧化铟，从而获得更好的界面特性，提高器件的亚阈值特性和工作电流。例如，最靠近栅极11的单元结构层130的薄膜结构为ZnO x，则在ZnO x上再额外设置一层InO x，如图8所示，从而获得更好的界面特性。
在一些实现方式中，半导体沟道13的厚度为3nm～5nm，从而保证半导体沟道13具有较好的迁移率，同时也有利于整个晶体管器件10的微缩和高密度大规模阵列。
还需要说明的是，由于本实施例中的晶体管器件10由于栅极11向上穿透，且第二源漏极152位于下方，可便于形成2T0C器件结构，占用面积小，如9所示，一晶体管器件10的栅极11与另一晶体管器件10的第二源漏极152连接。
综上所述，本公开的一个或多个实施例中的一种晶体管器件通过栅 绝缘层包裹设置在栅极表面；半导体沟道包裹设置在栅绝缘层的远离栅极的表面；第一源漏极环绕设置在栅绝缘层的远离栅极的一侧，并位于栅极的第一端；第二源漏极，设置在栅绝缘层的远离栅极的一侧，并位于栅极的第二端。组成的晶体管器件结构形成半导体沟道全环绕栅极，增加了半导体沟道和栅极对应的面积，有效的增强了栅极对半导体沟道的控制能力，有利于进一步的微缩器件尺寸，同时半导体沟道可具备更大面积，增加了载流子数量，提高了性能。
基于同一发明构思，在本公开的又一实施例中还提供了一种存储器，包括前述实施例中任一所述的晶体管器件。
需要说明的是，本实施例提供的一种存储器，其采用了前述实施例中的晶体管器件，因此该存储器具备的有益效果可参照前述实施例中的阐述，本实施例中不再赘述。另外，晶体管器件以及存储器中每个结构被制作时的具体工艺实现可采用现有的工艺技术，本实施例中不作限制。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (10)

  1. 一种晶体管器件，包括：
    栅极；
    栅绝缘层，环绕设置在所述栅极的侧面；
    半导体沟道，环绕设置在所述栅绝缘层的远离所述栅极的一侧；
    第一源漏极，环绕设置在所述栅绝缘层的远离所述栅极的一侧，并位于所述栅极的第一端；以及
    第二源漏极，设置在所述栅绝缘层的远离所述栅极的一侧，并位于所述栅极的第二端。
  2. 如权利要求1所述的晶体管器件，其中，所述第一源漏极和所述第二源漏极均环绕设置在所述半导体沟道的远离所述栅极的表面。
  3. 如权利要求1所述的晶体管器件，其中，所述第一源漏极和所述第二源漏极均环绕设置在所述栅绝缘层的远离所述栅极的表面；所述第一源漏极与所述半导体沟道的第一端连接，所述第二源漏极与所述半导体沟道的第二端连接。
  4. 如权利要求1所述的晶体管器件，其中，所述第二源漏极包裹设置在所述半导体沟道的第二端。
  5. 如权利要求1所述的晶体管器件，其中，所述栅极伸入所述第二源漏极的长度不小于10nm。
  6. 如权利要求1所述的晶体管器件，其中，所述半导体沟道的伸入第二源漏极的端部的外围直径小于50nm。
  7. 如权利要求1所述的晶体管器件，其中，所述半导体沟道伸 入第二源漏极的端部的外围直径与所述栅极伸入所述第二源漏极的长度满足关系：H≥0.5×(120nm-D)，其中，H为所述栅极伸入所述第二源漏极的长度，D为所述半导体沟道伸入第二源漏极的端部的外围直径。
  8. 如权利要求1所述的晶体管器件，其中，所述第二源漏极环绕设置在所述半导体沟道的远离所述栅极的表面，并位于所述半导体沟道的第二端。
  9. 如权利要求1所述的晶体管器件，还包括：电极绝缘层，环绕设置在所述半导体沟道的远离所述栅极的表面，且位于所述第一源漏极和所述第二源漏极之间；所述电极绝缘层用于隔离所述第一源漏极和所述第二源漏极。
  10. 一种存储器，包括权利要求1-9中任一所述的晶体管器件。
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