CN112242393A - 电路架构 - Google Patents

电路架构 Download PDF

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Publication number
CN112242393A
CN112242393A CN201910806631.5A CN201910806631A CN112242393A CN 112242393 A CN112242393 A CN 112242393A CN 201910806631 A CN201910806631 A CN 201910806631A CN 112242393 A CN112242393 A CN 112242393A
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transistor
gate structure
channel
circuit architecture
channel layer
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CN201910806631.5A
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CN112242393B (zh
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陈骏盛
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Powerchip Technology Corp
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Powerchip Technology Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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Abstract

本发明公开一种电路架构，其包括第一栅极结构、第一多连通通道层以及第二晶体管。第一栅极结构具有第一延伸方向，且第一栅极结构具有相对的第一端与第二端。第一多连通通道层完全环绕第一栅极结构，且第一多连通通道层的平面方向垂直于第一栅极结构的第一延伸方向。第一栅极结构以及第一多连通通道层构成第一晶体管。第二晶体管设置在第一多连通通道层中，第二晶体管的第二栅极结构或通道与第一多连通通道层相互电连接。

Description

电路架构
技术领域
本发明涉及一种电路架构，且特别是涉及一种具有通过多连通通道层进行信号传输的电路架构。
背景技术
金属氧化物半导体场效晶体管(MOSFET)的微缩，持续推动电子产业的进步。从结构上来看，金属氧化物半导体场效晶体管的演化路径是沿着平面式(planar)往鳍式(finfet)再往纳米线(nanowire)迈进，其中纳米线有各种变形如栅极全环绕(Gate All-Around，GAA)场效晶体管。
栅极全环绕场效晶体管的目的是利用弹道传输(ballistic transport)，提高载流子迁移率(carrier mobility)，降低次临界摆幅(sub-threshold swing)，增加单位面积的输出电流。
然而，栅极全环绕场效晶体管是栅极封闭通道的结构，所以其场效应由单一个栅极所贡献，当多个栅极全环绕场效晶体管电性上并联或结构上并排时，通道中任一点的电位仍然由单一个栅极所贡献。
发明内容
本发明提供一种电路架构，通过多连通通道进行晶体管间的信号传输，可降低传输电阻，提升信号传输效益。
本发明的电路架构包括第一栅极结构、第一多连通通道层以及第二晶体管。第一栅极结构具有第一延伸方向，且第一栅极结构具有相对的第一端与第二端。第一多连通通道层完全环绕第一栅极结构，且第一多连通通道层的平面方向垂直于第一栅极结构的第一延伸方向。其中第一栅极结构以及第一多连通通道层构成第一晶体管。第二晶体管设置在第一多连通通道层中，第二晶体管的第二栅极结构或通道与第一多连通通道层相互电连接。
基于上述，本发明的电路架构，使多个晶体管共同设置在多连通通道层中，并通过多连通通道层，使第一晶体管的通道可以与第二晶体管的第二栅极结构或通道相互电连接。如此一来，电路架构中，晶体管间的信号传输通道的连接电阻可以有效降低，有效提升其间的信号传输效益。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附的附图作详细说明如下。
附图说明
图1是本发明的第一实施例的一种半导体装置的透视示意图；
图2是本发明的第二实施例的一种金属-绝缘层-半导体电容(Metal-Insulator-Semiconductor Capacitor，MISC)的透视示意图；
图3是本发明的第三实施例的一种场效晶体管(Field-Effect Transistor，FET)的透视示意图；
图4是本发明的第四实施例的一种金属-绝缘层-半导体场效晶体管(Metal-Insulator-Semiconductor FET，MISFET)的透视示意图；
图5是本发明的第五实施例的一种隧穿场效晶体管(Tunnel FET，TFET)的透视示意图；
图6是本发明的第六实施例的一种栅极通道全环绕(Gate-Channel All-Around，GCAA)场效晶体管的透视示意图；
图7是本发明的第七实施例的一种场效晶体管的上视示意图；
图8A与图8B是本发明的第八实施例的两种半导体装置的上视示意图；
图8C是模拟图8A的电位-电场图；
图9是本发明的第九实施例的一种半导体装置的上视示意图；
图10A与图10B是本发明的第十实施例的两种场效晶体管的上视示意图；
图11A至图11E是本发明的第十一实施例的一种半导体装置的制造流程剖面示意图；
图12A至图12E是本发明的第十二实施例的一种半导体装置的制造流程剖面示意图；
图13A为本发明一实施例的电路架构的示意图；
图13B为电路架构1300的等效电路图；
图14为本发明另一实施例的电路架构的示意图；
图15A为本发明另一实施例的电路架构的上视示意图；
图15B为电路架构1500的等效电路图；
图16A为本发明另一实施例的电路架构的上视图；
图16B以及图16C分别为电路架构1600的不同实施方式的等效电路图；
图17A为本发明另一实施例的电路架构的上视图；
图17B与图17C分别为电路架构1700的不同实施方式的等效电路的示意图；
图18A至图18C为本发明实施例的电路架构的多个实施方式的示意图；
图19A至图19C为本发明实施例的电路架构的多个实施方式的示意图；
图20为本发明电路架构的一实施方式的示意图；
图21A为本发明的电路架构的一实施方式的上视示意图；
图21B为电路架构2100的等效电路图；
图22为本发明电路架构的一实施方式的上视图；
图23为本发明电路架构的一实施方式的电路图；
图24为本发明电路架构的一实施方式的立体结构示意图；
图25为本发明电路架构的一实施方式的立体结构示意图；
图26为本发明电路架构的一实施方式的电路图。
符号说明
100：通道全环绕半导体装置
102、602、1000a、1000b、1114、1216、G1～G9、GA2、GA3、GA4、GS：栅极结构
102a：第一端
102b：第二端
104、1102、1210a、1301、1401、1402、1510、1610、1710、2410、2510：多连通通道层
106：通道
200：金属-绝缘层-半导体电容
202、906：介电层
300：场效晶体管
302、502、1108、1208、S1、S2：源极区
304、504、1116、1214、D1、D2：漏极区
306a、306b、I1、I2、I3、I4、IA2～IA4：绝缘间隔层
400：金属-绝缘层-半导体场效晶体管
402：栅极绝缘层
500：隧穿场效晶体管
506：口袋型掺杂区
600：GCAA场效晶体管
604：内部封闭通道结构
900：栅极全环绕元件
902：封闭式通道
904：外部栅极
1100、1200：基板
1104、1204：掩模层
1106：栅极孔道
1107、1207：掺杂制作工艺
1110、1202：导体材料
1112、1212：膜层
1118：隔离结构
1206：连通沟槽
1210：通道材料
1300、1400、1500、1600、1700、1810、1820、1910、1920、1930、2000、2100、2200、2300、2400、2500、2600：电路架构
1410：导线层
2201～2204：掺杂区
A1、A1B、B1、B1B：信号
BL、BLB：位线
CA2、CA3、CA4：隔离通道层
CE1～CE4、CER1、CE、CPE2：通道端
CK1、CK2、CK3、CK1B、CK2B、CK3B：时钟脉冲信号
COUT、COUT1～COUT3：通道输出信号
d1：延伸方向
d2：平面方向
DIR1：延伸方向
DE1～DE4、DE、DPE2：漏极端
DOUT、DOUT1～DOUT3：漏极输出信号
EW1：连接导线
GE1～GE4、GAE1、GAE4、GARE1：栅极端
GS1、GS1B、GS2、GS2B、GS3、GS3B：控制信号
IN、IN1、IN2、C0～C3、AIN1～AIN4：输入信号
OUT、OUT0～OUT3、OUTT：输出信号
s1、s2：间距
s3：距离
SE1、SE2：源极端
SIN：源极输入信号
T1～T8、TR1～TR4、TO1、TS1～TS4、TP1、TP2：晶体管
VDD：操作电压
VSS：参考接地电压
WL：字符线
Z1～Z3：区域
具体实施方式
图1是依照本发明的第一实施例的一种半导体装置的透视示意图。
请参照图1，第一实施例的通道全环绕半导体装置100包括数个栅极结构102以及一个多连通通道(Multi-connected Channel)层104。所述栅极结构102具有相同的一延伸方向d1，且每个栅极结构102具有相对的第一端102a与第二端102b。多连通通道层104则完全环绕这些栅极结构102，且多连通通道层104的平面方向d2垂直于延伸方向d1，以使这些栅极结构102的通道106都相互(电性)连通。本发明中的「多连通」是指单一通道全环绕半导体装置100的通道106内，可以存在有三维几何上任意一个不可以收缩成一个点(No loopscan be contracted to a point)的虚拟封闭路径(曲线)。若是以电特性来看，所述「多连通通道」也可表示为连接两终端或多终端的电传导通道。在一实施例中，上述栅极结构102的间距s1例如小于栅极结构102的第一端102a与第二端102b的距离，所述间距s1是两个栅极结构102垂直延伸方向d1的距离。在图1中的栅极结构102的断面为圆形或椭圆形，但本发明并不限于此，栅极结构102的断面也可为矩形、十字型、多边形或不规则形状，且上述断面是垂直于延伸方向d1。
图2是依照本发明的第二实施例的一种金属-绝缘层-半导体电容(Metal-Insulator-Semiconductor Capacitor，MISC)的透视示意图，其中使用与第一实施例相同的元件符号来代表相同或相似的元件，且相同的构件的说明可参照第一实施例，于此不再赘述。
请参照图2，第二实施例的半导体装置是金属-绝缘层-半导体电容200，其中除了栅极结构102与多连通通道层104，还有设置在每个栅极结构102与所述多连通通道层104之间的一层介电层202，其中介电层202的材料例如氧化物或其他适用于电容的介电材料。
图3是依照本发明的第三实施例的一种场效晶体管(Field-Effect Transistor，FET)的透视示意图，其中使用与第一实施例相同的元件符号来代表相同或相似的元件，且相同的构件的说明可参照第一实施例，于此不再赘述。
请参照图3，第三实施例的半导体装置属于场效晶体管300，其中除了栅极结构102与多连通通道层104，还有源极区302、漏极区304和数个绝缘间隔层306a、306b。源极区302环绕每个栅极结构102的第一端102a，漏极区304环绕每个栅极结构102的第二端102b。绝缘间隔层306a则位于源极区302与栅极结构102之间，绝缘间隔层306b则位于漏极区304与栅极结构102之间。绝缘间隔层306a、306b的作用在于使栅极结构102与源极区302以及漏极区304之间不短路，所以绝缘间隔层306a、306b为绝缘材料，如氧化物或其他绝缘材料。由于场效晶体管300的通道载流子没有被栅极结构102阻隔局限，额外三维空间里的自由度使场效晶体管300可以有多重电流路径(由漏极区304到源极区302)，包括沿延伸方向d1的路径、垂直延伸方向d1的路径以及先沿延伸方向d1再转为垂直延伸方向d1的路径。至于栅极结构102的间距s2可设定在源极区302与漏极区304的距离s3的一倍以内，且所述间距s2是两个栅极结构102垂直延伸方向d1的距离。当栅极结构102的间距s2在上述范围内，较有利于多连通通道层104内产生多连通通道。
请继续参照图3，场效晶体管300中的多连通通道层104内任一点，其电位为这些栅极结构102的个别电位所叠加(纯量和)。若第i个单一栅极结构102的个别电位为Qi/Ri，则多连通通道的总电位则为
Figure BDA0002183859430000071
Figure BDA0002183859430000072
在多连通通道内某一个点，其与第p个栅极结构102的距离为Rp，这一个栅极结构102的电位为Qp/Rp。在多连通通道内某一个点若下式成立，则场效晶体管300的栅控制能力(Gate Control)估计会优于单一通道全环绕式(Channel All-Around，CAA)场效晶体管。
Figure BDA0002183859430000073
特别当上式两边相等时，相当于两个栅极(double gate)的电位和。也就是说，单纯考虑栅极的电位分布，忽略载流子的屏蔽效应，本发明具有的多连通通道的场效晶体管300都优于两个栅极的场效晶体管(如SOI MOSFET含正面栅极与背面栅极的架构)。而且，由于随着栅极尺寸变小，能使1/R迅速提升，所以本发明能通过更小的栅极尺寸搭配较多的栅极结构而得到更大的栅极总电位。
在一实施例中，栅极结构102与多连通通道层104若形成一P-N结，则场效晶体管300可为结场效晶体管(Junction Field-Effect Transistor，JFET)。
在一实施例中，栅极结构102与多连通通道层104若形成一金属半导体接触，则场效晶体管300可为金属半导体场效晶体管(Metal-Semiconductor Field-EffectTransistor，MESFET)。
在一实施例中，栅极结构102与多连通通道层104之间若有异质结构(未绘示)，则场效晶体管300可为异质结构隔离栅场效晶体管(Heterostructure Isolated Gate FET，HIGFET)，其中所述异质结构为无掺杂(undoped)异质结构；或者，场效晶体管300可为调制掺杂场效晶体管(Modulation-doped FET，MODFET)，其中所述异质结构为调制掺杂(Modulation-doped)异质结构。
上述数个栅极结构102中若为属于不同元件的栅极结构，可经由电流或电位阻绝不同元件的栅极结构；或者，直接在不同元件之间设置如浅沟槽隔离结构(STI)的一般元件隔离结构。
图4是依照本发明的第四实施例的一种金属-绝缘层-半导体场效晶体管(Metal-Insulator-Semiconductor FET，MISFET)的透视示意图，其中使用与第三实施例相同的元件符号来代表相同或相似的元件，且相同的构件的说明可参照第三实施例，于此不再赘述。
请参照图4，第四实施例的半导体装置是金属-绝缘层-半导体场效晶体管400，其中除了栅极结构102、多连通通道层104、源极区302、漏极区304和数个绝缘间隔层306a、306b，还有位于每个栅极结构102与多连通通道层104之间的栅极绝缘层402，其中栅极绝缘层402的材料例如氧化硅。在图4中，绝缘间隔层306a、306b的厚度大于栅极绝缘层402的厚度，但本发明并不限于此。绝缘间隔层306a、306b的厚度也可等于栅极绝缘层402的厚度。而且，绝缘间隔层306a、306b与栅极绝缘层402如选用相同材料及相同厚度，还可简化制作工艺，而同时制作出绝缘间隔层306a、306b与栅极绝缘层402。
图5是依照本发明的第五实施例的一种隧穿场效晶体管(Tunnel FET，TFET)的透视示意图，其中使用与第四实施例相同的元件符号来代表相同或相似的元件，且相同的构件的说明可参照第四实施例，于此不再赘述。
请参照图5，第五实施例的半导体装置是隧穿场效晶体管500，其中除了栅极结构102、多连通通道层104、源极区502、漏极区504、绝缘间隔层306a、306b和栅极绝缘层402，还有位于源极区502内并环绕每个栅极结构的口袋型掺杂区506。在本实施例中，源极区502与漏极区504为不同导电型、口袋型掺杂区506与源极区502为不同导电型。也就是说，口袋型掺杂区506与漏极区504是相同导电型。举例来说，源极区502是N+区、漏极区504是P+区以及口袋型掺杂区506是P+区。利用P+型的口袋型掺杂区506与N+型的源极区502能在附近所造成的高电场，引起能带间隧穿电流(Band-to-Band Tunneling current，BTBT隧穿电流)。
图6是依照本发明的第六实施例的一种栅极通道全环绕(Gate-Channel All-Around，GCAA)场效晶体管的透视示意图，其中使用与第三实施例相同的元件符号来代表相同或相似的元件，且相同的构件的说明可参照第三实施例，于此不再赘述。
请参照图6，第六实施例的半导体装置为GCAA场效晶体管600，其中除了多连通通道层104、源极区302、漏极区304和数个绝缘间隔层306a、306b，每个栅极结构602为中空结构，且于每个栅极结构602的中空区域内形成有内部封闭通道结构604。因此，第六实施例的装置能同时拥有内部封闭通道与外部的多连通通道。
图7是依照本发明的第七实施例的一种场效晶体管的上视示意图，其中使用与第三实施例相同的元件符号来代表相同或相似的元件，且相同的构件的说明可参照第三实施例，于此不再赘述。
在图7中，漏极区304的断面的面积小于多连通通道层104的平面的面积，其中所述断面垂直于延伸方向(图3的d1)。由于漏极区304的断面面积较小，所以能使多连通通道层104内的通道都受到控制，而抑制漏电路径。此外，在图7的虚线框起来的区域还能构成金属-绝缘体-半导体-绝缘体-金属(metal-insulator-semiconductor-insulator-metal，MISIM)二极管结构。
图8A与图8B是依照本发明的第八实施例的两种通道全环绕半导体装置的上视示意图，其中使用与第一实施例相同的元件符号来代表相同或相似的元件，且相同的构件的说明可参照第一实施例，于此不再赘述。在本发明中，栅极结构102在平面方向的排列可为成对排列、规则排列或不规则排列。举例来说，第一实施例的栅极结构102在平面方向的排列为规则的四边形排列，而在第八实施例中，栅极结构102在平面方向的规则排列可为三角形排列(如图8A)或者六边形排列(如图8B)，但本发明还可有其他选择，譬如五边形排列等。从图8C的模拟电位-电场图可知，多个同电位的电场线与电位线相互垂直，电场的强度若足以使通道形成，多个同电位栅极的等电位线也能具象表现出通道多连通的意涵，而达到通道多连通的效果。因此，上述排列也可适用于其他实施例中。
图9是依照本发明的第九实施例的一种通道全环绕半导体装置的上视示意图，其中使用与第二实施例相同的元件符号来代表相同或相似的元件，且相同的构件的说明可参照第二实施例，于此不再赘述。
在第九实施例中是在第二实施例的半导体装置中另外包括至少一栅极全环绕(Gate All Around)元件900，例如图9的半导体装置是由设置于多连通通道层104中的一个十字型的金属-绝缘层-半导体电容200以及四个栅极全环绕元件900构成，且所述栅极全环绕元件900的延伸方向与栅极结构102的延伸方向相同。栅极全环绕元件900基本上包括封闭式通道902、外部栅极904以及两者之间的介电层906。然而，本发明并不以此为限，金属-绝缘层-半导体电容200也可变更为其他实施例的半导体装置，其中栅极全环绕元件900以及本发明的半导体装置之数量、断面形状等均可根据需求改变。
图10A与图10B是依照本发明的第十实施例的两种场效晶体管的上视示意图，其中使用与第三实施例相同的元件符号来代表相同或相似的元件，并省略绘示漏极区和源极区，且相同的构件的说明可参照第三实施例，于此不再赘述。
在图10A与图10B中有部分栅极结构1000a、1000b沿平面方向延伸出多连通通道层104，使得能产生多连通通道的范围小于栅极结构1000a、1000b的范围，使多连通通道层104内的通道都受到控制，而抑制漏电路径。而且，多连通通道层104以外虽未绘示其他结构，但应知多连通通道层104之外可通过元件隔离结构(未绘示)包围，并与周围其它元件作电性隔离。
图11A至图11E是依照本发明的第十一实施例的一种通道全环绕半导体装置的制造流程剖面示意图。
请先参照图11A，在基板1100上先形成一多连通通道层1102，形成上述多连通通道层1102的方法例如在基板1100上进行外延制作工艺。另外，为了后续蚀刻制作工艺，可先在多连通通道层1102上形成掩模层1104，且掩模层1104可为单层或多层结构。
然后，请参照图11B，在多连通通道层1102内形成数个栅极孔道1106，且这些栅极孔道1106具有相同的一延伸方向，以使后续形成的栅极结构具有相同的延伸方向。形成栅极孔道1106之后还可根据元件设计进行掺杂制作工艺1107，以于栅极孔道1106中的基板1100内形成源极区1108。
接着，请参照图11C，在栅极孔道1106内填满导体材料1112，再平坦化所述导体材料1110，以去除栅极孔道1106外的导体材料。而且，为了形成不同的半导体装置，可于栅极孔道1106的内面先共形地形成其他膜层1112(如介电层、绝缘间隔层或异质结构)，再进行导体材料1110的沉积与平坦化。
之后，请参照图11D，去除掩模层1104之后，可进行再结晶或选择性外延，以形成栅极结构1114。多连通通道层1102则完全环绕这些栅极结构1114，且多连通通道层1114的平面方向垂直于栅极结构1114的延伸方向，以使这些栅极结构1114的通道相互(电性)连通。形成栅极结构1114之后还可根据元件设计进行掺杂制作工艺1107，以于多连通通道层1102表面形成漏极区1116。
最后，请参照图11E，在漏极区1116之间可形成隔离结构1118将不同栅极结构1114的漏极区1116隔开。隔离结构1118例如是浅沟槽隔离结构或其他绝缘结构。
图12A至图12E是依照本发明的第十二实施例的一种通道全环绕半导体装置的制造流程剖面示意图。
请先参照图12A，在基板1200上先形成导体材料1202，形成上述导体材料1202的方法例如在基板1200上进行外延制作工艺。另外，为了后续蚀刻制作工艺，可先在导体材料1202上形成掩模层1204，且掩模层1204可为单层或多层结构。
接着，请参照图12B，在导体材料1202内形成连通沟槽1206。由于本图是剖面图，所以连通沟槽1206是分开的，但是实际上连通沟槽1206应如同图1的多连通通道层104的位置是相互连通的。形成上述连通沟槽1206之后还可根据元件设计进行掺杂制作工艺1207，以于连通沟槽1206中的基板1200内形成源极区1208。
然后，请参照图12C，在连通沟槽1206内形成通道材料1210。在一实施例中，形成通道材料1210之前还可包括于连通沟槽1206内共形地沉积其他膜层1212(如介电层、绝缘间隔层或异质结构)。上述的通道材料1210例如硅、砷化镓、氮化镓、硅锗、磷化铟等外延层。导体材料1202例如多晶硅、铝、氮化钛、钛铝合金、金、钨等金属。
之后，请参照图12D，平坦化上一图的通道材料1210，以去除连通沟槽1206外的通道材料，并得到连通沟槽1206内的多连通通道层1210a。此外，平坦化通道材料之后，还可根据元件设计进行掺杂制作工艺1207，以于多连通通道层1210a的表面形成漏极区1214。
最后，请参照图12E，金属化导体材料1202，使其成为栅极结构1216。
请参照图13A，图13A绘示本发明一实施例的电路架构的示意图。电路架构1300包括栅极结构G1、G2以及多连通通道层1301。栅极结构G1、G2具有相同的延伸方向DIR1，栅极结构G1、G2并均具有第一端以及第二端。栅极结构G1、G2设置在多连通通道层1301中，且多连通通道层1301完全环绕栅极结构G1、G2。栅极结构G1的第一端上，另具有漏极区D1，栅极结构G1的第二端上，则另具有源极区S1。漏极区D1与源极区S1与栅极结构G1间分别具有绝缘间隔层I1以及I2。绝缘间隔层I1以及I2用以防止漏极区D1与源极区S1与栅极结构G1间产生短路。此外，栅极结构G2的第一端上，另具有漏极区D2，栅极结构G2的第二端上，则另具有源极区S2。漏极区D2与源极区S2与栅极结构G2间分别具有绝缘间隔层I3以及I4。绝缘间隔层I3以及I4用以防止漏极区D2与源极区S2与栅极结构G2间产生短路。
在本实施例中，栅极结构G1与多连通通道层1301，配合漏极区D1与源极区S1可形成第一晶体管。栅极结构G2与多连通通道层1301，配合漏极区D2与源极区S2则可形成第二晶体管。其中，第一晶体管的通道可形成在多连通通道层1301中，且第二晶体管的通道可相同的形成在多连通通道层1301中。如此一来，第一晶体管与第二晶体管的通道可相互电连接。
下请同步参照图13A以及图13B，其中图13B绘示电路架构1300的等效电路图。在图13B中，由栅极结构G1以及多连通通道层1301所共同形成的第一晶体管T1可具有四个端点，分别为栅极端GE1、源极端SE1、漏极端DE1以及通道端CE1。而由栅极结构G2以及多连通通道层1301所共同形成的第二晶体管T2同样可具有四个端点，分别为栅极端GE2、源极端SE2、漏极端DE2以及通道端CE2。通过图13A绘示的晶体管架构1300，通过晶体管T1、T2所共用的多连通通道层1301，晶体管T1、T2可通过通道端CE1、CE2形成通道内电连接的结构。如此，可使晶体管T1、T2形成相互串接或者相互并接的结构。并且，通过通道端CE1、CE2间的相互连接，晶体管T1、T2的通道中的电荷可在相对低的传输电阻的条件下，进行传输的动作，有效提升晶体管T1、T2间的信号传输效益。
在另一方面，在电路架构1300中，可通过使晶体管T1中的漏极端DE1以及晶体管T1中的通道端CE1相互短路，并且使晶体管T2中的漏极端DE2以及晶体管T2中的通道端CE2相互短路。如此可使晶体管T1中的通道端CE1与漏极端DE1，以及晶体管T2中的通道端CE2与漏极端DE2同为电荷汲取端。并且，在本发明实施例中，可另通过外接的连接导线EW1方式，来使漏极端DE1、DE2间电连接，进一步提升晶体管T1、T2间的信号传输效益。
在本实施例中，晶体管T1、T2可以为P型晶体管。其中，晶体管T1、T2的导电型态可以依据多连通通道层1301的导电型态来决定(与多连通通道层1301的导电型态相同)。而基于晶体管T1、T2共用多连通通道层1301，晶体管T1、T2的导电型态是相同的。在本发明其他实施例中，晶体管T1、T2也可以同为N型晶体管。
通过上述实施例的做法，本发明实施例的电路架构1300可实现通道内逻辑(in-channel logic)的架构。
以下请参照图14，图14绘示本发明另一实施例的电路架构的示意图。电路架构1400包括栅极结构G1、G2、多连通通道层1401、1402以及导线层1410。多连通通道层1401、1402分别具有不同(互补)的导电型态，并分别环绕栅极结构G1、G2。栅极结构G1、G2具有相同的延伸方向。栅极结构G1的第一端以及第二端上分别设置源极区S1以及漏极区D1，栅极结构G2的第一端以及第二端上则分别设置源极区S2以及漏极区D2。此外，在本实施例中，导线层1410设置以环绕漏极区D1以及漏极区D2，并使漏极区D1以及漏极区D2电连接。
在本实施例中，栅极结构G1以及多连通通道层1401可建构出第一晶体管，栅极结构G2以及多连通通道层1402则可建构出第二晶体管。并且，通过导线层1410使漏极区D1以及漏极区D2电连接，可使第一晶体管以及第二晶体管间形成串联或并联的组态。值得注意的，通过导线层1410以使漏极区D1以及漏极区D2电连接，可使第一晶体管以及第二晶体管的通道形成伪(pseudo)连接的状态，并形成通道内逻辑的结构。
以下请参照图15A，图15A绘示本发明另一实施例的电路架构的上视示意图。电路架构1500包括多个栅极结构G1～G4以及多连通通道层1510。栅极结构G1～G4设置在相同的多连通通道层1510中，并使多连通通道层1510环绕栅极结构G1～G4。栅极结构G1～G4并与多连通通道层1510形成相互串联的多个晶体管。栅极结构G1上的源极区可用以接收源极输入信号SIN，栅极结构G4上的通道以及漏极区可分别产生通道输出信号COUT以及漏极输出信号DOUT。在此可请参照图15B绘示的电路架构1500的等效电路图。其中，栅极结构G1～G4与多连通通道层1510分别形成晶体管T1～T4。而通过共用多连通通道层1510，晶体管T1～T4可形成依序串联的组态，其中晶体管T1～T4具有分别对应栅极结构G1～G4的栅极端GE1～GE4，栅极端GE1～GE4可用以接收相同或不相同的控制信号。
在另一方面，晶体管T1的源极端SE1可接收源极输入信号SIN，晶体管T4的通道端CE4以及漏极端DE4可产生输出信号OUT。输出信号OUT可以为通道输出信号COUT以及漏极输出信号DOUT中的任一，或为通道输出信号COUT以及漏极输出信号DOUT的组合。
在本实施例中，电路架构1500可以为一晶体管传输逻辑(pass transistorlogic,PTL)，并通过通道内电荷转移(in-channel charge transfer)进行信号传输。而晶体管T1～T4通过通道内连接的架构，可降低晶体管传输逻辑的传输电阻，提升信号传输的效益，降低内电阻所产生的压降失真(IR drop)。
请参照图16A，图16A绘示本发明另一实施例的电路架构的上视图。电路架构1600包括栅极结构G1、GA2以及多连通通道层1610。多连通通道层1610完全环绕栅极结构G1、GA2，并且，栅极结构GA2具有一封闭区域，封闭区域中设置绝缘层IA2以及隔离通道层CA2，其中，绝缘层IA2设置在栅极结构GA2以及隔离通道层CA2间，用以防止栅极结构GA2以及隔离通道层CA2直接短路。在本实施例中，栅极结构G1以及多连通通道层1610可形成第一晶体管，栅极结构GA2、绝缘层IA2以及隔离通道层CA2则可形成第二晶体管。
基于栅极结构GA2直接设置在多连通通道层1610中，并为多连通通道层1610完全环绕，因此，第一晶体管的通道可直接电连接至第二晶体管的栅极端。以下可参照图16B以及图16C分别绘示的电路架构1600的不同实施方式的等效电路图。在图16B中，栅极结构G1以及多连通通道层1610所形成的第一晶体管T1，栅极结构GA2以及多连通通道层1610所形成的第二晶体管T2。基于栅极结构GA2与多连通通道层1610相接触，第一晶体管T1的通道端CE1可与第二晶体管T2的栅极端GAE1直接电连接。如此一来，第一晶体管T1的通道端CE1与第二晶体管T2的栅极端GAE1间的传输电阻可以降低，提升信号传输效益。
在图16A的实施例中，多连通通道层1610以及隔离通道层CA2的导电型态可以是相同的，例如都为N型。如此一来，图16A中的第一晶体管T1以及第二晶体管T2可以都为N型晶体管。相对的，多连通通道层1610以及隔离通道层CA2的导电型态也可以都为P型，如图16C的实施方式所示，栅极结构G1以及多连通通道层1610所形成的第一晶体管T3，以及栅极结构GA2以及多连通通道层1610所形成的第二晶体管T4，可以都为P型晶体管。
此外，在图16C中，通过栅极结构GA2与多连通通道层1610相接触，第一晶体管T3的通道端CE3可与第二晶体管T4的栅极端GAE4直接电连接。如此一来，第一晶体管T1的通道端CE3与第二晶体管T4的栅极端GAE4间的传输电阻可以降低，提升信号传输效益。
请参照图17A，图17A绘示本发明另一实施例的电路架构的上视图。电路架构1700包括栅极结构G1、GA3以及多连通通道层1710。多连通通道层1710完全环绕栅极结构G1、GA3，并且，栅极结构GA3具有一封闭区域，封闭区域中设置绝缘层IA3以及隔离通道层CA3，其中，绝缘层IA3设置在栅极结构GA3以及隔离通道层CA3间，用以防止栅极结构GA3以及隔离通道层CA3直接短路。在本实施例中，栅极结构G1以及多连通通道层1610可形成第一晶体管，栅极结构GA3、绝缘层IA3以及隔离通道层CA3则可形成第二晶体管。
值得一提的，多连通通道层1710以及隔离通道层CA3的导电型态可以是相反的。以下请同步参照图17A至图17C，其中图17B与图17C分别绘示电路架构1700的不同实施方式的等效电路的示意图。以多连通通道层1710以及隔离通道层CA3的导电型态分别为N型以及P型为范例，在图17B中，多连通通道层1710以及栅极结构G1所构成的第一晶体管TR1可以为N型晶体管，栅极结构GA3、绝缘层IA3以及隔离通道层CA3所构成的第二晶体管TR2可以为P型晶体管。并且，通过使多连通通道层1710以及栅极结构GA3相互接触，第一晶体管TR1的通道端CER1可直接电连接第二晶体管TR2的栅极端GARE1。
在另一方面，以多连通通道层1710以及隔离通道层CA3的导电型态分别为P型以及N型为范例，在图17C中，多连通通道层1710以及栅极结构G1所构成的第一晶体管TR3可以为P型晶体管，栅极结构GA4、绝缘层IA4以及隔离通道层CA4所构成的第二晶体管TR4可以为N型晶体管。并且，通过使多连通通道层1710以及栅极结构GA4相互接触，第一晶体管TR3的通道端CER3可直接电连接第二晶体管TR4的栅极端GARE4。
请参照图18A至图18C，图18A至图18C绘示本发明实施例的电路架构的多个实施方式的示意图。其中，图18A至图18C的电路架构为复位式逻辑电路。在图18A中，电路架构1810包括第一晶体管T1以及第二晶体管T2。第一晶体管T1具有栅极端GE1、源极端SE1、漏极端DE1以及通道端CE1。第二晶体管T2则具有栅极端GE2、源极端SE2、漏极端DE2以及通道端CE2。在本实施方式中，电路架构1810为一反向器电路，其中的第一晶体管T1可以为P型晶体管，晶体管T2可以为N型晶体管。第一晶体管T1的源极端SE1接收操作电压VDD，第一晶体管T1的栅极端SE1接收输入信号IN，第一晶体管T1的漏极端DE1以及通道端CE1则可在区域Z1，通过设置外接导线的方式，与第二晶体管T2的漏极端DE2以及通道端CE2相互电连接。此外，第二晶体管T2的栅极端GE2接收输入信号IN，第二晶体管T2的源极端SE2耦接至参考接地电压VSS。并且，第一晶体管T1的通道端CE1以及第二晶体管T2的通道端CE2相互电连接，并用以产生通道输出信号COUT。第一晶体管T1的漏极端DE1以及第二晶体管T2的漏极端CE2相互电连接，并产生漏极输出信号DOUT。
值得一提的，在本实施方式中，第一晶体管T1的漏极端DE1以及通道端CE1可以相互电连接，第二晶体管T2的漏极端DE2以及通道端CE2也可以相互电连接，并使通道输出信号COUT与漏极输出信号DOUT相同。
在本实施方式中，输入信号IN、通道输出信号COUT以及漏极输出信号DOUT均可以为逻辑信号，且电路架构1810为反向器逻辑电路，输入信号IN反向于通道输出信号COUT以及漏极输出信号DOUT。
基于第一晶体管T1以及第二晶体管T2的导电型态相反，本实施方式可应用电路架构1400来实施。
在图18B中，电路架构1820包括第一晶体管T1、第二晶体管T2、第三晶体管T3以及第四晶体管T4。第一晶体管T1的源极端SE1以及第二晶体管T2的源极端SE2共同接收操作电压VDD，第一晶体管T1的栅极端GE1以及第二晶体管T2的栅极端GE2分别接收输入信号IN1以及IN2。第一晶体管T1的通道端CE1以及第二晶体管T2的通道端CE2共同产生通道输出信号COUT，第一晶体管T1的漏极端DE1以及第二晶体管T2的漏极端DE2则共同产生漏极输出信号DOUT。其中第一晶体管T1与第二晶体管T2呈并联耦接的状态。
此外，第三晶体管T3的通道端CE3以及漏极端DE3分别耦接至第一晶体管T1的通道端CE1以及漏极端DE1，第三晶体管T3的栅极端GE3接收输入信号IN2。第四晶体管T4的通道端CE4以及漏极端DE4的至少其中之一，可通过在区域Z2中设置导线以电连接至第三晶体管T3的源极端SE3。另外，第四晶体管T4的源极端SE4接收参考接地电压VSS，第四晶体管T4的栅极端GE4则接收输入信号IN1。其中第三晶体管T3与第四晶体管T4呈串联耦接的状态，且在本发明其他实施方式中，第三晶体管T3与第四晶体管T4的位置可以互换。
电路架构1820为一与非门(反及闸)逻辑电路，用以针对输入信号IN1以及IN2执行与非(NAND)逻辑运算，以产生通道输出信号COUT以及漏极输出信号DOUT。
在图18C中，电路架构1830包括第一晶体管T1、第二晶体管T2、第三晶体管T3以及第四晶体管T4。其中，第一晶体管T1与第二晶体管T2相互串联耦接，第三晶体管T3与第四晶体管T4相互并联耦接。值得一提的，第一晶体管T1的通道端CE1、漏极端DE1，可通过在区域Z3中设置导线以电连接第二晶体管T2的源极端SE2。电路架构1830为一或非门(反或闸)逻辑电路，用以针对输入信号IN1以及IN2执行或非(NOR)逻辑运算，以产生通道输出信号COUT以及漏极输出信号DOUT。
在此请注意，在图18B以及图18C的实施方式中，基于第一晶体管T1以及第二晶体管T2为相同导电型态(P型)的晶体管，因此可通过前述实施例的电路架构1300的设置。基于第一晶体管T3以及第二晶体管T3为相同导电型态(N型)的晶体管，因此同样可通过前述实施例的电路架构1300的设置。然而基于第一晶体管T1的导电型态与第三晶体管T3的导电型态相反，因此用以设置第一晶体管T1以及第二晶体管T2的多连通通道层，与设置第三晶体管T3以及第四晶体管T4的多连通通道层不相同，并可通过电路架构1400的方式来建构。
以下请参照图19A至图19C，图19A至图19C绘示本发明实施例的电路架构的多个实施方式的示意图。其中，图19A至图19C绘示本发明实施例的电路架构1910、1920以及1930分别为反向器逻辑电路、与非门逻辑电路以及或非门逻辑电路。值得一提的，在电路架构1910、1920以及1930中，第一晶体管T1用以形成一二极管，其中，通过使第一晶体管T1的栅极端GE1(通过区域Z1～Z3中的导线)耦接至其通道端CE1及漏极端DE1的至少其中之一，可以第一晶体管T1形成二极管组态，并作为一上拉电路。
在图19B中，第二晶体管T2以及第三晶体管T3相互串联耦接，并分别接收输入信号IN1、IN2。如此，配合接收操作电压VDD的第一晶体管T1，电路架构1920可以为与非门逻辑电路。
在图19C中，第二晶体管T2以及第三晶体管T3相互并联耦接，并分别接收输入信号IN1、IN2。如此，配合接收操作电压VDD的第一晶体管T1，电路架构1920可以为或非门逻辑电路。
接着请参照图20，图20绘示本发明电路架构的一实施方式的示意图。电路架构2000包括第一晶体管T1至第六晶体管T6。其中的第一晶体管T1至第三晶体管T3为相同导电型态(P型)，第一晶体管T4至第三晶体管T6为相同导电型态(N型)。第一晶体管T1与第四晶体管T4的源极端相互电连接，第一晶体管T1与第四晶体管T4的通道端以及漏极端相互电连接。第一晶体管T1与第四晶体管T4的栅极端分别接收控制信号GS1以及GS1B，且控制信号GS1以及GS1B互为反向信号。第二晶体管T2与第五晶体管T5的源极端相互电连接，第二晶体管T2与第五晶体管T5的通道端以及漏极端相互电连接。第二晶体管T2与第五晶体管T5的栅极端分别接收控制信号GS2以及GS2B，且控制信号GS2以及GS2B互为反向信号。并且，第三晶体管T3与第六晶体管T6的源极端相互电连接，第三晶体管T3与第六晶体管T6的通道端以及漏极端相互电连接。第三晶体管T3与第六晶体管T6的栅极端分别接收控制信号GS3以及GS3B，且控制信号GS3以及GS3B互为反向信号。
在本实施方式中，电路架构2000为一切换式逻辑电路。其中互耦接的晶体管对形成一传输闸(传输门)，并用以传输信号V1～V3以分别产生通道输出信号COUT1～COUT3以及漏极输出信号DOUT1～DOUT3。
在本实施方式中，基于第一晶体管T1至第三晶体管T3具有相同的导电型态，第一晶体管T1至第三晶体管T3可依据电路架构1300的方式，通过共用相同的一第一多连通通道层进行建构。基于第四晶体管T4至第六晶体管T6具有相同的导电型态，第四晶体管T4至第六晶体管T6可依据电路架构1300的方式，通过共用相同的一第二多连通通道层进行建构。第一多连通通道层与第二多连通通道层的导电型态不相同，则可依据电路架构1400的方式来建构。
接着请参照图21A以及图21B，图21A绘示本发明的电路架构的一实施方式的上视示意图，图21B绘示电路架构2100的等效电路图。在图21A中，电路架构2100包括多连通通道层2110以及多个栅极结构G1～G8。多连通通道层2110完全环绕栅极结构G1～G8。其中，栅极结构G1、G3、G5、G7分别对应栅极结构G2、G4、G6、G8进行排列。
并且，栅极结构G3、G7接收信号A1；栅极结构G1、G5接收信号A1B；栅极结构G6、G8接收信号B1；栅极结构G2、G4接收信号B1B，其中信号A1为信号A1B的反向，信号B1为信号B1B的反向。配合多连通通道层2110，栅极结构G1～G8可分别形成第一晶体管T1至第八晶体管T8(如图21B所示)。第一晶体管T1的源极端用以接收输入信号C0；第三晶体管T3的源极端用以接收输入信号C1；第五晶体管T5的源极端用以接收输入信号C2；第七晶体管T7的源极端用以接收输入信号C3。
以第一至第八晶体管T1～T8都为N型晶体管为范例，在当信号A1B、B1B为逻辑高电平时(信号A1、B1为逻辑低电平)，第一晶体管T1以及第二晶体管T2产生通道，并通过通道间相互形成通道内连接，通过传输输入信号C0以产生输出信号OUT1。在当信号A1、B1B为逻辑高电平时(信号A1B、B1为逻辑低电平)，第三晶体管T3以及第四晶体管T4产生通道，并通过通道间相互形成通道内连接，通过传输输入信号C1以产生输出信号OUT1。在当信号A1B、B1为逻辑高电平时(信号A1、B1B为逻辑低电平)，第五晶体管T5以及第六晶体管T6产生通道，并通过通道间相互形成通道内连接，通过传输输入信号C2以产生输出信号OUT2。在当信号A1、B1为逻辑高电平时(信号A1B、B1B为逻辑低电平)，第七晶体管T7以及第八晶体管T8产生通道，并通过通道间相互形成通道内连接，通过传输输入信号C3以产生输出信号OUT3。
此外，本实施方式更通过使晶体管T2、T4、T6、T8的漏极端及/或通道端相互电连接，以组合输出信号OUT0～OUT3以产生输出信号OUTT。
以下请参照图22，图22绘示本发明电路架构的一实施方式的上视图。电路架构2200包括多个栅极结构G1～G6以及多连通通道层2210。多连通通道层2210完全环绕栅极结构G1～G6。栅极结构G1～G6用以形成多个晶体管，上述的多个晶体管具有共同的通道端CE以及漏极端DE。栅极结构G1～G6并依据对称方式，以对称于通道端CE以及漏极端DE的方式进行排列。
多连通通道层2210并设置多个N加强型(N+)掺杂区2201～2204，以作为分别接收多个输入信号AIN1～AIN4的信号接收介面。在本实施方式中，电路架构2200为一模拟电路，输入信号AIN1～AIN4都为模拟信号，并且，输入信号AIN1～AIN4可以为两组差动信号，例如输入信号AIN1、AIN2互为差动信号，输入信号AIN3、AIN4互为另一组差动信号。
以下请参照图23，图23绘示本发明电路架构的一实施方式的电路图。通过本发明实施例提供的晶体管架构，电路架构2300可通过具有通道端CE以及漏极端DE的晶体管TO1来建构运算放大器OP1的输出级。如此一来，通过使晶体管TO1的通道端CE所提供的通道输出信号COUT来通过通道内反馈(in-channel feedback)，来进行反馈动作，可降低信号反馈路径的传输电阻，并提高反馈信号的品质。另外，晶体管TO1的漏极端DE可用以提供漏极输出信号DOUT至外部电路。如此一来，可降低反馈信号(通道输出信号COUT)因外部电路所产生的干扰现象，提升电路的稳定性。
以下请参照图24，图24绘示本发明电路架构的一实施方式的立体结构示意图。电路架构2400通过在多连通通道层2410中设置多个栅极结构GS，并使栅极结构GS依据一阵列形式进行排列。电路架构2400可以形成一功率晶体管，并通过多个栅极结构GS以及多连通通道层2410来产多个并联的通道。电路架构2400可通过多个通道提供多个通道输出信号，并通过多个晶体管的漏极端提供多个漏极输出信号。并藉以提升通道输出信号以及漏极输出信号的驱动能力。
以下请参照图25，图25绘示本发明电路架构的一实施方式的立体结构示意图。电路架构2500包括多连通通道层2510以及多个栅极结构G1～G9。栅极结构G1～G9设置在多连通通道层2510中，并使多连通通道层2510完全环绕栅极结构G1～G9。栅极结构G1～G9配合多连通通道层2510以形成多个晶体管，在本实施方式中，栅极结构G1、G4接收时钟脉冲信号CK1；栅极结构G2、G6接收时钟脉冲信号CK2；栅极结构G3、G8接收时钟脉冲信号CK3；栅极结构G5、G7、G9则分别接收时钟脉冲信号CK1B、CK2B以及CK3B。其中，时钟脉冲信号CK1B、CK2B以及CK3B分别为时钟脉冲信号CK1、CK2以及CK3的反向信号，且时钟脉冲信号CK1、CK2以及CK3可以为依序被致能的周期性信号。
电路架构2500可以为电荷转移电路，并可用以实施电荷泵电路，为一种模拟式的切换性电源供应电路(switching power supplier)。
在此请注意，在本实施方式中，通过共用相同的多连通通道层2510，所形成的多个晶体管的多个通道，可通过内通道连接的方式，进行电荷转移的动作。在具有相对低传输电阻的效益下，可提升电荷转移的转换效能。
以下请参照图26，图26绘示本发明电路架构的一实施方式的电路图。电路架构2600为一存储器电路(例如为一静态存储单元)。电路架构2600包括晶体管TS1～TS4以及TP1、TP2。晶体管TS1、TS2为P型晶体管，并共同接收工作电压VDD。晶体管TS3、TS4为N型晶体管，并分别与晶体管TS1、TS2串联耦接。晶体管TS3、TS4则接收参考接地电压VSS。此外，晶体管TS1、TS3的栅极端共同耦接至晶体管TS2、TS4的通道端CE2、CE4，及/或耦接至晶体管TS2、TS4的漏极端DE2、DE4。晶体管TS2、TS4的栅极端则共同耦接至晶体管TS1、TS3的通道端CE1、CE3，及/或耦接至晶体管TS1、TS3的漏极端DE1、DE3。
在另一方面，晶体管TP1的栅极端耦接字符线WL，晶体管TP1的源极端耦接位线BL，晶体管TP1通过其通道端CPE1及/或漏极端DPE1耦接至晶体管TS1、TS3的通道端CE1、CE3及漏极端DE1、DE3。晶体管TP2的栅极端耦接字符线WL，晶体管TP2的源极端耦接位线BLB，晶体管TP2通过其通道端CPE2及/或漏极端DPE2耦接至晶体管TS2、TS4的通道端CE2、CE4及漏极端DE2、DE4。
在此请注意，晶体管TP1、TP2的连接方式没有限制要如图26所示。晶体管TP1、TP2也可通过通道端CE2、CE4及漏极端DE2、DE4来分别耦接至位线BL、BLB。
在本实施方式中，晶体管TS1～TS4、TP1、TP2间通过，通道内连接的方式，可提升电荷存储的效能，确保数据的稳定性。
综上所述，本发明的电路架构中，通过将通道设计在通道全环绕半导体装置的栅极的外部，所以这样的通道不会被阻隔局限在单一栅极结构中，而在三维空间里具有多重电流路径。若是应用于场效晶体管，则能在相同次临界摆幅下，大幅增加单位面积的输出电流，因此预期可进一步增加元件密度。
虽然结合以上实施例公开了本发明，然而其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (13)

1.一种电路架构，其特征在于，该电路架构包括：
第一栅极结构，所述第一栅极结构具有第一延伸方向，且所述第一栅极结构具有相对的第一端与第二端；
第一多连通通道层，完全环绕所述第一栅极结构，且所述第一多连通通道层的平面方向垂直于所述第一栅极结构的所述第一延伸方向，
其中所述第一栅极结构以及所述第一多连通通道层构成第一晶体管；以及
第二晶体管，设置在所述第一多连通通道层中，所述第二晶体管的第二栅极结构或通道与所述第一多连通通道层相互电连接。
2.如权利要求1所述的电路架构，其中所述第二晶体管包括：
所述第二栅极结构，所述第二栅极结构具有与所述第一栅极结构相同的所述第一延伸方向，且所述第二栅极结构具有相对的第一端与第二端，其中所述第一多连通通道层完全环绕所述第二栅极结构，所述第二栅极结构并在所述第一多连通通道层中形成所述第二晶体管的所述通道。
3.如权利要求2所述的电路架构，其中所述第一晶体管通过所述第一多连通通道层与所述第二晶体管的通道相互电连接。
4.如权利要求1所述的电路架构，其中所述第二晶体管包括：
所述第二栅极结构，所述第二栅极结构具有与所述第一栅极结构相同的所述第一延伸方向，且所述第二栅极结构具有相对的第一端与第二端，其中所述第二栅极结构设置在所述第一多连通通道层中，并环绕一封闭区域；以及
隔离通道层，设置在所述封闭区域中，其中所述隔离通道层与多连通通道层的导电型态相同或相反。
5.如权利要求4所述的电路架构，其中所述第一晶体管通过所述第一多连通通道层与所述第二晶体管的所述第二栅极结构相互电连接。
6.如权利要求1所述的电路架构，还包括：
第三栅极结构，所述第三栅极结构具有第二延伸方向，所述第三栅极结构具有相对的第一端与第二端；以及
第二多连通通道层，完全环绕所述第三栅极结构，且所述第二多连通通道层的平面方向垂直于所述第二栅极结构的所述第二延伸方向，
其中所述第三栅极结构以及所述第二多连通通道层构成第三晶体管。
7.如权利要求6所述的电路架构，其中所述第一晶体管还包括：
第一源极区与第一漏极区，所述第一晶体管的所述第一源极区与所述第一漏极区分别环绕所述第一栅极结构的所述第一端与所述第二端，
所述第三晶体管还包括：
第二源极区与第二漏极区，所述第三晶体管的所述第二源极区与所述第二漏极区分别环绕所述第三栅极结构的所述第一端与所述第二端，
所述电路架构还包括导线层，用以使该第一漏极区以及所述第二漏极区电连接。
8.如权利要求7所述的电路架构，其中所述第一多连通通道层以及第二多连通通道层的导电型态相反。
9.如权利要求7所述的电路架构，其中所述第一晶体管还包括：
多个第一绝缘间隔层，分别位于所述第一源极区与所述第一栅极结构之间以及位于所述第一漏极区与所述第一栅极结构之间，
其中所述第三晶体管还包括：
多个第二绝缘间隔层，分别位于所述第二源极区与所述第三栅极结构之间以及位于所述第二漏极区与所述第三栅极结构之间。
10.如权利要求1所述的电路架构，其中所述电路架构为逻辑电路、模拟电路以及存储器电路的至少其中之一。
11.如权利要求10所述的电路架构，其中所述电路架构包括所述逻辑电路时，所述电路架构通过通道内逻辑执行一逻辑运算。
12.如权利要求10所述的电路架构，其中所述电路架构包括所述模拟电路时，所述电路架构通过通道内反馈已传送反馈信号。
13.如权利要求10所述的电路架构，其中所述电路架构通过通道内电荷转移以进行信号传输。
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